CN109427797B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN109427797B CN109427797B CN201710734937.5A CN201710734937A CN109427797B CN 109427797 B CN109427797 B CN 109427797B CN 201710734937 A CN201710734937 A CN 201710734937A CN 109427797 B CN109427797 B CN 109427797B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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Abstract
A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate including a cell memory region and a content addressable memory region; forming a grid structure on a substrate, wherein the grid structure comprises a tunneling oxide layer and a floating grid layer positioned on the tunneling oxide layer; forming a first source-drain doped region in the substrate at two sides of the grid structure of the unit memory region; and forming second source-drain doped regions in the substrate at two sides of the grid structure of the content addressable memory region, wherein the doping concentration of the second source-drain doped regions is less than that of the first source-drain doped regions. The doping concentration of the second source-drain doping region is reduced to improve the initial threshold voltage of the content addressable memory, and accordingly electrons of the floating gate layer in an eigen state are increased, so that the trap-assisted tunneling effect can be improved, and the data storage capacity of the content addressable memory is improved; in addition, the doping concentration of the first source-drain doping region is not affected, so that the performance of the unit memory region is not affected.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
At present, Flash memory (Flash), also known as Flash memory, has become the mainstream of non-volatile memory. Flash memories are classified into Nor Flash (Nor Flash) and NAND Flash (NAND Flash) according to their structures. The flash memory has the main characteristics of long-term storage information retention without power-on, and has the advantages of high integration level, high access speed, easy erasing and rewriting and the like, thereby being widely applied to various fields such as microcomputer, automatic control and the like.
The NAND Flash includes not only a Cell Memory but also a Content Addressable Memory (CAM). A content addressable memory is a special memory that can be searched in a single operation for the entire memory, so in search applications, the content addressable memory is faster than normal memory. The fast search feature of the CAM makes the CAM particularly suitable for applications such as network devices, CPUs (central Processing units), DSPs (Digital Signal processors), and video codecs.
However, the performance of prior art content addressable memories has yet to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can improve the performance of a content addressable memory.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate including a cell memory area and a content addressable memory area; forming a grid structure on the substrate, wherein the grid structure comprises a tunneling oxide layer and a floating grid layer positioned on the tunneling oxide layer; forming first source-drain doped regions in the substrate on two sides of the grid structure of the unit memory region; and forming second source-drain doped regions in the substrate at two sides of the grid structure of the content addressable memory region, wherein the doping concentration of the second source-drain doped regions is less than that of the first source-drain doped regions.
Optionally, a first source-drain implantation process is used to form the first source-drain doped region, a second source-drain implantation process is used to form the second source-drain doped region, and the implantation dose of the second source-drain implantation process is smaller than that of the first source-drain implantation process.
Optionally, the step of forming the first source-drain doped region includes: forming a first graphic layer on the substrate of the content addressable memory area, wherein the first graphic layer also covers the grid structure of the content addressable memory area; performing a first source-drain injection process on the substrate on two sides of the grid structure of the unit memory area by taking the first graphic layer as a mask; and removing the first pattern layer after the first source-drain injection process.
Optionally, the parameters of the first source-drain implantation process include: the implanted ions include one or more of P ions, As ions, and Sb ions, the implantation energy is 10Kev to 20Kev, and the implantation dose is 7E12 atoms per square centimeter to 1.2E13 atoms per square centimeter.
Optionally, the step of forming the second source-drain doped region includes: forming a second graphic layer on the substrate of the unit memory area, wherein the second graphic layer also covers the grid structure of the unit memory area; performing a second source-drain injection process on the substrates on two sides of the grid structure of the content addressable memory area by taking the second graphic layer as a mask; and removing the second pattern layer after the second source-drain implantation process.
Optionally, the parameters of the second source-drain implantation process include: the dopant ions include one or more of P ions, As ions, and Sb ions, the implantation energy is 10Kev to 20Kev, and the implantation dose is 5E12 atoms per square centimeter to 1E13 atoms per square centimeter.
Optionally, the step of forming the first source-drain doped region includes: forming first grooves in the substrate on two sides of the grid electrode structure of the unit memory area; forming a first semiconductor layer in the first groove, and in-situ self-doping ions in the process of forming the first semiconductor layer; or, the step of forming the first source-drain doped region includes: forming first grooves in the substrate on two sides of the unit memory area grid structure; forming a first semiconductor layer in the first groove; and doping ions to the first semiconductor layer.
Optionally, the step of forming the second source-drain doped region includes: forming second grooves in the substrate on two sides of the grid structure of the content addressable memory area; forming a second semiconductor layer in the second groove, and self-doping ions in situ in the process of forming the second semiconductor layer, wherein the doping concentration of the second semiconductor layer is less than that of the first semiconductor layer; or, the step of forming the second source-drain doped region includes: forming second grooves in the substrate at two sides of the grid structure of the content addressable memory area; forming a second semiconductor layer in the second groove; and doping ions into the second semiconductor layer, wherein the doping concentration of the second semiconductor layer is less than that of the first semiconductor layer.
Optionally, the first semiconductor layer is made of Si or SiC, the doped ions in the first semiconductor layer are N-type ions, and the N-type ions include one or more of P ions, As ions, and Sb ions; the material of the first semiconductor layer is Si or SiC, the doped ions in the first semiconductor layer are N-type ions, and the N-type ions comprise one or more of P ions, As ions and Sb ions.
Optionally, after the first source-drain doped region is formed, forming a second source-drain doped region; or after the second source-drain doped region is formed, the first source-drain doped region is formed.
Optionally, in the step of forming a gate structure on the substrate, the gate structure further includes: the gate dielectric layer is positioned on the floating gate layer, and the control gate layer is positioned on the gate dielectric layer.
Accordingly, the present invention also provides a semiconductor structure comprising: a base including a cell memory area and a content addressable memory area; the grid structure is positioned on the substrate and comprises a tunneling oxide layer and a floating grid layer positioned on the tunneling oxide layer; the first source-drain doped region is positioned in the substrate at two sides of the grid structure of the unit memory region; and the second source-drain doped region is positioned in the substrate at two sides of the grid structure of the content addressable memory region, and the doping concentration of the second source-drain doped region is less than that of the first source-drain doped region.
Optionally, the doping ions of the first source-drain doping region include one or more of P ions, As ions, and Sb ions.
Optionally, the doping ions of the second source-drain doping region include one or more of P ions, As ions, and Sb ions.
Optionally, the gate structure further includes: the gate dielectric layer is positioned on the floating gate layer, and the control gate layer is positioned on the gate dielectric layer.
Optionally, the first source-drain doped region is made of a first semiconductor material with doped ions, and the second source-drain doped region is made of a second semiconductor material with doped ions.
Optionally, the first semiconductor material is Si or SiC, and the doped ions in the first semiconductor material include one or more of P ions, As ions and Sb ions; the second semiconductor material is Si or SiC, and the doping ions in the second semiconductor material comprise one or more of P ions, As ions and Sb ions.
Compared with the prior art, the technical scheme of the invention has the following advantages:
forming a first source-drain doped region in the substrate on two sides of the grid structure of the unit memory region and forming a second source-drain doped region in the substrate on two sides of the grid structure of the content addressable memory region respectively, wherein the doping concentration of the second source-drain doped region is less than that of the first source-drain doped region; compared with the scheme that the doping concentration of the first source-drain doping region is the same as that of the second source-drain doping region, the Initial threshold voltage (Initial Vt) of the content addressable memory is increased by reducing the doping concentration of the second source-drain doping region, and accordingly electrons of a Floating Gate (FG) in an intrinsic state are increased; therefore, when programming (Program), for the same programming voltage, the electrons required to be captured by the floating gate layer are reduced, and accordingly, the Trap charges in a Tunnel Oxide layer (Tunnel Oxide) caused by programming can be reduced, that is, the Trap-assisted Tunneling (TAT) effect can be improved, so that the problem of device leakage current is improved, the threshold voltage characteristic of the content addressable memory is improved, the Data Retention (Data Retention) capability of the content addressable memory is improved, and the performance of the content addressable memory is improved; moreover, after programming, the number of electrons stored in the floating gate layer is reduced, and accordingly, the problem of electron loss of the floating gate layer caused by other effects can be solved, and the data storage capacity of the content addressable memory can be further improved; in addition, the first source-drain doped region and the second source-drain doped region are formed respectively, so that the doping concentration of the first source-drain doped region is not influenced, and the performance of the unit memory region is not influenced.
Drawings
FIG. 1 is a graph of threshold voltage of a content addressable memory cell corresponding to a content addressable memory versus a sample number of the content addressable memory cell;
FIG. 2 is a graph of the threshold voltage of the content addressable memory cell versus the number of samples of the content addressable memory cell after the content addressable memory of FIG. 1 is subjected to a baking process;
FIG. 3 is a schematic diagram of a semiconductor structure;
FIGS. 4-7 are schematic diagrams illustrating steps of a method of forming a semiconductor structure according to an embodiment of the present invention;
fig. 8 is a graph showing the relationship between the threshold voltage of the content addressable memory cell and the sample number of the content addressable memory cell after the baking process is performed on the formed content addressable memory under the condition that different source-drain implantation doses are used in the embodiments shown in fig. 4 to 7.
Detailed Description
As is known in the art, the performance of a Content Addressable Memory (CAM) needs to be improved.
Specifically, after the content addressable memory is subjected to baking (baker) processing of a reliability test or after a long-term Idle (Idle), the content addressable memory is prone to problems of Data Retention Fail (Data Retention Fail) and threshold voltage Shift (Vt Shift).
Referring to fig. 1 and 2 in combination, fig. 1 is a graph of threshold voltage of a content addressable memory cell corresponding to a content addressable memory versus a sample number of the content addressable memory cell; fig. 2 is a graph of threshold voltage of the content addressable memory cell versus a sample number of content addressable memory cells after a baking process for the content addressable memory of fig. 1. Wherein the abscissa of fig. 1 and 2 represents the threshold voltage and the ordinate represents the number of samples.
Specifically, fig. 2 is a graph of the relationship between the content addressable memory in fig. 1 after baking at 250 degrees celsius for 2 hours, and a dashed line a in fig. 1 and fig. 2 is a threshold voltage standard value of the content addressable memory unit, that is, when the threshold voltages of the content addressable memory units corresponding to the content addressable memory are all greater than the threshold voltage standard value, it is determined that the programming of the content addressable memory is successful.
As can be seen, after the baking process, the threshold voltage of the content addressable memory is reduced, and the threshold voltage shift of the Left half (i.e., Left-tail) of the graph (as shown by the dashed circle in FIG. 2) is especially severe.
The cause of the performance degradation of the CAM is analyzed in conjunction with a schematic diagram of a semiconductor structure. Referring to fig. 3, a schematic diagram of a semiconductor structure is shown.
The semiconductor structure includes: a substrate 10, the substrate 10 including a cell memory area I and a content addressable memory area II; a Gate structure (not labeled) on the substrate 10, where the Gate structure includes a tunneling oxide layer 21, a floating Gate layer 22 on the tunneling oxide layer 21, a Gate dielectric layer 23 on the floating Gate layer 22, and a Control Gate (CG) layer 24 on the Gate dielectric layer 23; and the source-drain doped regions 30 are positioned in the substrates 10 at two sides of the grid structure of the unit memory region I and in the substrates 10 at two sides of the grid structure of the content addressable memory region II.
Typically, the programming voltage (Program Vt) and the Read voltage (Read Vt) of a content addressable memory are both larger than the cell memory; the higher programming voltage indicates that after the content addressable memory is programmed, the number of electrons stored in the floating gate layer 22 is larger, and accordingly, the Trap charges in the Tunneling oxide layer 21 are also larger, so that a Trap-assisted Tunneling (TAT) effect is easily generated, and the electrons in the floating gate layer 22 are easily leaked through the Tunneling oxide layer 21 where the TAT effect is generated, so that the threshold voltage of the content addressable memory is easily shifted, and the data storage capability of the content addressable memory is reduced.
In order to solve the technical problem, the initial threshold voltage of the content addressable memory is improved by reducing the doping concentration of the second source-drain doping region, so that electrons of the floating gate layer in an intrinsic state are increased correspondingly; therefore, during programming, for the same programming voltage, the number of electrons required to be captured by the floating gate layer is reduced, and accordingly, the trap charges in the tunneling oxide layer caused by programming can be reduced, namely, the trap-assisted tunneling effect can be improved, so that the leakage current problem of the device is improved, the threshold voltage characteristic of the content addressable memory is improved, the data storage capacity of the content addressable memory is further improved, and the performance of the content addressable memory is improved; moreover, after programming, the number of electrons stored in the floating gate layer is reduced, and accordingly, the problem of electron loss of the floating gate layer caused by other effects can be solved, and the data storage capacity of the content addressable memory can be further improved; in addition, the doping concentration of the first source-drain doping region can be unaffected by forming the first source-drain doping region and the second source-drain doping region respectively, so that the performance of the unit memory region is unaffected.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 8 are schematic diagrams corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 4, a substrate 100 is provided, the substrate 100 including a cell memory area I and a content addressable memory area II.
The substrate 100 provides a process operation basis for subsequent processes.
Specifically, the substrate 100 is used to form a NAND Flash (NAND Flash) device.
In this embodiment, the formed semiconductor structure is a planar structure, and correspondingly, the substrate 100 is a planar substrate. In other embodiments, the formed semiconductor structure may further have a fin structure, that is, the formed device is a fin field effect transistor, and the substrate respectively includes a substrate and a discrete fin portion on the substrate.
In this embodiment, the base 100 is a silicon substrate. In other embodiments, the material of the base may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium, and the base may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration.
In this embodiment, the substrate 100 includes a cell memory region I and a content addressable memory region II, the substrate 100 of the cell memory region I is used to form a cell memory, and the substrate 100 of the content addressable memory region II is used to form a content addressable memory.
In this embodiment, the unit memory area I and the content addressable memory area II are not disposed adjacent to each other. In other embodiments, the unit memory area and the content addressable memory area may also be adjacently disposed.
Referring to fig. 5, a Gate structure (not labeled) is formed on the substrate 100, and the Gate structure includes a Tunnel Oxide (Tunnel Oxide)210 and a Floating Gate (FG) 220 on the Tunnel Oxide 210.
In the step of forming the gate structure on the substrate 100, the gate structure further includes: a Gate dielectric layer 230 on the floating Gate layer 220, and a Control Gate (CG) layer 240 on the Gate dielectric layer 230.
Specifically, the step of forming the gate structure includes: forming a tunnel oxide material layer on the substrate 100; forming a floating gate material layer on the tunneling oxide material layer; forming a gate dielectric material layer on the floating gate material layer; forming a control gate material layer on the gate dielectric material layer; the control gate material layer, the gate dielectric material layer, the floating gate material layer and the tunneling oxide material layer are patterned in sequence, the remaining tunneling oxide material layer is used as a tunneling oxide layer 210, the remaining floating gate material layer is used as a floating gate layer 220, the remaining gate dielectric material layer is used as a gate dielectric layer 230, and the remaining control gate material layer is used as a control gate layer 240, and the tunneling oxide layer 210, the floating gate layer 220, the gate dielectric layer 230 and the control gate layer 240 are used for forming the gate structure.
In this embodiment, the floating gate layer 220 and the control gate layer 240 are made of polysilicon; the tunneling oxide layer 210 is made of silicon oxide; the gate dielectric layer 230 includes a first silicon Oxide layer, a silicon Nitride layer on the first silicon Oxide layer, and a second silicon Oxide layer on the silicon Nitride layer, that is, the gate dielectric layer 230 is an ONO (Oxide-Nitride-Oxide) structure.
The technical scheme for forming the gate structure is the same as that of the prior art, and the description of the embodiment is omitted.
Referring to fig. 6, first source-drain doped regions 315 are formed in the substrate 100 at both sides of the cell memory region igate structure (not labeled).
The first source-drain doped region 315 is used as a source region or a drain region of the formed cell memory.
In this embodiment, a first source-drain implantation (CSD Implant) process 310 is used to form the first source-drain doped region 315.
Specifically, the step of forming the first source-drain doped region 315 includes: forming a first graphic layer 300 on the substrate 100 of the content addressable memory region II, wherein the first graphic layer 300 also covers the gate structure of the content addressable memory region II; performing a first source-drain implantation process 310 on the substrate 100 on both sides of the unit memory region I gate structure by using the first pattern layer 300 as a mask; after the first source-drain implantation process 310, the first pattern layer 300 is removed.
In this embodiment, the device type of the formed unit memory is an N-type device, so the implanted ions of the first source-drain implantation process 310 are N-type ions, and the parameters of the first source-drain implantation process 310 are determined according to actual process requirements and device performance requirements.
In some embodiments, the parameters of the first source-drain implantation process 310 include: the implant ions include one or more of P ions, As ions, and Sb ions, the implant energy is 10Kev to 20Kev, and the implant dose is 7E12 atoms per square centimeter to 1.2E13 atoms per square centimeter.
It should be noted that, in this embodiment, because the distance between the adjacent gate structures is smaller, the first source-drain doped region 315 between the adjacent gate structures is shared by the cell memories to which the two gate structures belong.
In this embodiment, the first pattern layer 300 is made of photoresist, and after the first source/drain implantation process 310, the first pattern layer 300 is removed by ashing or a wet process.
In other embodiments, in order to further improve the performance of the formed cell memory, an Epitaxial (EPI) technique is introduced during the process of forming the first source/drain doped region, so as to improve the carrier mobility of the cell memory.
Specifically, the step of forming the first source-drain doped region includes: forming first grooves in the substrate on two sides of the grid electrode structure of the unit memory area; forming a first semiconductor layer in the first groove, and in-situ self-doping ions in the process of forming the first semiconductor layer; or doping ions into the first semiconductor layer after the first semiconductor layer is formed in the first groove.
Correspondingly, the material of the first semiconductor layer is Si or SiC, the doped ions in the first semiconductor layer are N-type ions, and the N-type ions include one or more of P ions, As ions and Sb ions.
Referring to fig. 7, a second source/drain doped region 415 is formed in the substrate 100 on both sides of the content addressable memory region II gate structure (not labeled), and the doping concentration of the second source/drain doped region 415 is less than the doping concentration of the first source/drain doped region 315.
The second source-drain doped region 415 is used as a source region or a drain region of the formed content addressable memory.
In this embodiment, the doping concentration of the second source-drain doping region 415 is smaller than the doping concentration of the first source-drain doping region 315.
Compared with the scheme that the doping concentration of the first source-drain doping region is the same as that of the second source-drain doping region, the doping concentration of the second source-drain doping region 415 is reduced to improve the initial threshold voltage of the content addressable memory, so that electrons of the floating gate layer 220 of the content addressable memory in an intrinsic state are increased correspondingly, and therefore, the electrons required to be captured by the floating gate layer 220 are reduced for the same programming voltage during programming.
Since the floating gate layer 220 captures electrons from the substrate 100, and the tunnel oxide layer 210 is located between the floating gate layer 220 and the substrate 100, by reducing the electrons required to be captured by the floating gate layer 220, the trapped charges in the tunnel oxide layer 210 caused by programming can be correspondingly reduced, that is, the Trap-assisted Tunneling (TAT) effect can be improved, so as to improve the problem of device leakage current, improve the threshold voltage characteristic of the content addressable memory, avoid the problem of threshold voltage shift, further improve the data storage capability of the content addressable memory, and improve the performance of the content addressable memory; moreover, after programming, the number of charges stored in the floating gate layer 220 is reduced, and accordingly, the problem of electron loss of the floating gate layer 220 caused by other effects can be solved, which is beneficial to further improving the data storage capacity of the content addressable memory.
In addition, if the initial threshold voltage of the unit memory is increased, although the data storage capability of the unit memory may be improved, the repeated read/write (i.e., Cycling) capability of the unit memory may be deteriorated accordingly; therefore, the first source-drain doped region 315 and the second source-drain doped region 415 are formed in different processes, that is, under the condition of reducing the doping concentration of the second source-drain doped region 415, the doping concentration of the first source-drain doped region 315 can not be affected, so that the performance of the formed unit memory region is not affected.
In this embodiment, the second source-drain doping region 415 is formed by using a second source-drain implantation process 410, and an implantation dose of the second source-drain implantation process 410 is smaller than an implantation dose of the first source-drain implantation process 310 (shown in fig. 6).
Specifically, the step of forming the second source/drain doped region 415 includes: forming a second graphic layer 400 on the substrate 100 of the unit memory region I, wherein the second graphic layer 400 also covers the gate structure of the unit memory region I; performing a second source-drain implantation process 410 on the substrate 100 on both sides of the gate structure of the content addressable memory region II by using the second pattern layer 400 as a mask; after the second source-drain implantation process 410, the second pattern layer 400 is removed.
In this embodiment, the device type of the formed content addressable memory is an N-type device, and thus the implanted ions of the second source/drain implantation process 410 are N-type ions.
In some embodiments, the parameters of the second source-drain implantation process 410 include: the implanted ions include one or more of P ions, As ions and Sb ions, and the implantation energy is 10Kev to 20 Kev.
It should be noted that the implantation dose of the second source/drain implantation process 410 is not too small or too large. If the implantation dose of the second source-drain implantation process 410 is too small, the saturation current of the formed content addressable memory is too small, and the read current is too small; if the implantation dose of the second source-drain implantation process 410 is too large, the effect of increasing the initial threshold voltage of the formed content addressable memory is not obvious, and accordingly, the effect of improving the performance of the content addressable memory is not obvious. For this reason, in this embodiment, the implantation dose of the second source/drain implantation process 410 is 5E12 atoms per square centimeter to 1E13 atoms per square centimeter.
It should be further noted that the implantation dose of the second source/drain implantation process 410 is not limited to 5E12 atoms per square centimeter to 1E13 atoms per square centimeter, and in an actual process, the implantation dose may be adjusted according to actual process conditions and device performance requirements.
In addition, in this embodiment, because the distance between adjacent gate structures is small, the second source-drain doped region 415 between adjacent gate structures is shared by the content addressable memory to which the two gate structures belong.
In this embodiment, the second pattern layer 400 is made of photoresist, and after the second source/drain implantation process 410, the second pattern layer 400 is removed by ashing or a wet process.
In other embodiments, in order to further improve the performance of the formed content addressable memory, an epitaxial technique is introduced during the process of forming the second source-drain doped region, so as to improve the carrier mobility of the content addressable memory.
Specifically, the step of forming the second source-drain doped region includes: forming second grooves in the substrate on two sides of the grid structure of the content addressable memory area; forming a second semiconductor layer in the second groove, and self-doping ions in situ in the process of forming the second semiconductor layer, wherein the doping concentration of the second semiconductor layer is less than that of the first semiconductor layer; or doping ions into the second semiconductor layer after forming the second semiconductor layer in the second groove, wherein the doping concentration of the second semiconductor layer is less than that of the first semiconductor layer.
Correspondingly, the material of the second semiconductor layer is Si or SiC, and the doped ions in the second semiconductor layer are N-type ions, where the N-type ions include one or more of P ions, As ions, and Sb ions.
It should be noted that, in this embodiment, the first source/drain doped region 315 is formed first, and then the second source/drain doped region 415 is formed. In other embodiments, the first source-drain doped region may be formed after the second source-drain doped region is formed.
With reference to fig. 8, a graph of a relation between a threshold voltage of a content addressable memory cell corresponding to the content addressable memory and a sample number of the content addressable memory cell after the content addressable memory is subjected to a baking process in the foregoing embodiment under the condition of using different source-drain implant doses.
The abscissa represents the threshold voltage, the ordinate represents the number of samples, the source-drain implant dose adopted by the content addressable memory shown in the curve H is a first dose, the source-drain implant dose adopted by the content addressable memory shown in the curve G is a second dose, and the source-drain implant dose adopted by the content addressable memory shown in the curve F is a third dose, where the second dose is smaller than the first dose and the second dose is greater than the third dose, for example, the first dose, the second dose, and the third dose are respectively 8E12 atoms per square centimeter, 6E12 atoms per square centimeter, and 4E12 atoms per square centimeter.
As can be seen from the graph, after the same programming process, after two hours of baking process, the threshold voltage of the content addressable memory shown by the curve G is greater than that of the content addressable memory shown by the curve H, and the threshold voltage of the content addressable memory shown by the curve F is greater than that of the content addressable memory shown by the curve G.
Therefore, by reducing the doping concentration of the second source/drain doping region 415 (as shown in fig. 7), the threshold voltage of the content addressable memory after the baking process is increased, the threshold voltage shift problem of the Left half (i.e., Left-tail) of the relation graph (as shown by the dashed circle in fig. 8) is improved, and the leakage current problem of the content addressable memory is improved, so that the data storage capability of the content addressable memory is improved, and the performance of the content addressable memory is improved.
Correspondingly, the invention also provides a semiconductor structure formed by adopting the forming method.
With continued reference to fig. 7, a schematic structural diagram of an embodiment of the semiconductor structure of the present invention is shown. The semiconductor structure includes:
a substrate 100, the substrate 100 including a cell memory area I and a content addressable memory area II; a gate structure (not labeled) on the substrate 100, the gate structure including a tunnel oxide layer 210 and a floating gate layer 220 on the tunnel oxide layer 210; the first source-drain doped region 315 is located in the substrate 100 at two sides of the unit memory region I gate structure; and a second source-drain doped region 415 located in the substrate 100 at two sides of the gate structure of the content addressable memory region II, wherein the doping concentration of the second source-drain doped region 415 is less than the doping concentration of the first source-drain doped region 315.
In this embodiment, the semiconductor structure is a planar structure, and correspondingly, the substrate 100 is a planar substrate. In other embodiments, the semiconductor structure may further have a fin structure, that is, the device is a fin field effect transistor, and the substrate respectively includes a substrate and a discrete fin portion on the substrate.
Specifically, the device on the substrate 100 is a NAND Flash (NAND Flash) device.
In this embodiment, the base 100 is a silicon substrate. In other embodiments, the material of the base may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium, and the base may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration.
In this embodiment, the device in the cell memory region I is a cell memory, and the device in the content addressable memory region II is a content addressable memory.
In this embodiment, the unit memory area I and the content addressable memory area II are not disposed adjacent to each other. In other embodiments, the unit memory area and the content addressable memory area may also be adjacently disposed.
In this embodiment, the gate structure further includes: a gate dielectric layer 230 on the floating gate layer 220, and a control gate layer 240 on the gate dielectric layer 230.
Specifically, the material of the floating gate layer 220 and the control gate layer 240 is polysilicon; the tunneling oxide layer 210 is made of silicon oxide; the gate dielectric layer 230 includes a first silicon oxide layer, a silicon nitride layer on the first silicon oxide layer, and a second silicon oxide layer on the silicon nitride layer, that is, the gate dielectric layer 230 is an ONO structure.
The gate structure is the same as the prior art, and the description of this embodiment is omitted here.
The first source-drain doped region 315 is used as a source region or a drain region of the cell memory.
It should be noted that, in this embodiment, because the distance between the adjacent gate structures is smaller, the first source-drain doped region 315 between the adjacent gate structures is shared by the cell memories to which the two gate structures belong.
In this embodiment, the device type of the unit memory is an N-type device, and therefore the doping ions of the first source/drain doping region 315 are N-type ions, and the N-type ions include one or more of P ions, As ions, and Sb ions. The doping concentration of the first source/drain doped region 315 is determined according to actual process requirements and device performance requirements.
In other embodiments, in order to further improve the performance of the formed cell memory, an Epitaxial (EPI) technique is introduced during the process of forming the first source/drain doped region, so as to improve the carrier mobility of the cell memory.
Correspondingly, the material of the first source-drain doped region is a first semiconductor material with doped ions. Specifically, the first semiconductor material is Si or SiC, and the doping ions in the first semiconductor material include one or more of P ions, As ions, and Sb ions.
The second source-drain doped region 415 is used as a source region or a drain region of the content addressable memory.
It should be noted that in this embodiment, because the distance between the adjacent gate structures is small, the second source-drain doped region 415 between the adjacent gate structures is shared by the addressable memories belonging to the two gate structures.
In this embodiment, the doping concentration of the second source-drain doping region 415 is smaller than the doping concentration of the first source-drain doping region 315.
Compared with the scheme that the doping concentration of the first source-drain doping region is the same as that of the second source-drain doping region, the doping concentration of the second source-drain doping region 415 is reduced to improve the initial threshold voltage of the content addressable memory, so that electrons contained in the floating gate layer 220 of the content addressable memory in an intrinsic state are increased correspondingly, and therefore, in the programming process, the electrons required to be captured by the floating gate layer 220 are reduced.
Since the floating gate layer 220 captures electrons from the substrate 100, and the tunnel oxide layer 210 is located between the floating gate layer 220 and the substrate 100, by reducing the electrons required to be captured by the floating gate layer 220, the trapped charges in the tunnel oxide layer 210 caused by programming can be correspondingly reduced, that is, the Trap-assisted Tunneling (TAT) effect can be improved, so as to improve the problem of device leakage current, improve the threshold voltage characteristic of the content addressable memory, avoid the problem of threshold voltage shift, further improve the data storage capability of the content addressable memory, and improve the performance of the content addressable memory; moreover, after programming, the number of electrons stored in the floating gate layer 220 is reduced, and accordingly, the problem of electron loss of the floating gate layer 220 caused by other effects can be solved, which is beneficial to further improving the data storage capacity of the content addressable memory.
In addition, if the initial threshold voltage of the unit memory is increased, although the data storage capability of the unit memory may be improved, the repeated read/write (i.e., Cycling) capability of the unit memory may be deteriorated accordingly; therefore, under the condition of reducing the doping concentration of the second source-drain doping region 415, the doping concentration of the first source-drain doping region 315 is not affected, so that the performance of the unit memory region is not affected.
In this embodiment, the device type of the content addressable memory is an N-type device, so that the doped ions of the second source/drain doped region 415 are N-type ions, and the N-type ions include one or more of P ions, As ions, and Sb ions. The doping concentration of the second source/drain doped region 415 is determined according to actual process requirements and device performance requirements.
In other embodiments, in order to further improve the performance of the content addressable memory, an epitaxial technique is introduced during the process of forming the second source-drain doped region, so as to improve the carrier mobility of the content addressable memory.
Correspondingly, the second source-drain doped region is made of a second semiconductor material with doped ions. Specifically, the second semiconductor material is Si or SiC, and the doping ions in the second semiconductor material include one or more of P ions, As ions, and Sb ions.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (17)
1. A method of forming a semiconductor structure, comprising:
providing a substrate including a cell memory area and a content addressable memory area; the unit memory area is used for forming a unit memory, and the content addressable memory area is used for forming a content addressable memory;
forming a gate structure on the substrate, wherein the gate structure comprises a tunneling oxide layer and a floating gate layer positioned on the tunneling oxide layer;
forming first source-drain doped regions in the substrate on two sides of the grid structure of the unit memory region;
and forming second source-drain doped regions in the substrate at two sides of the grid structure of the content addressable memory region, wherein the doping concentration of the second source-drain doped regions is less than that of the first source-drain doped regions.
2. The method for forming a semiconductor structure according to claim 1, wherein a first source-drain implantation process is used to form the first source-drain doped region, a second source-drain implantation process is used to form the second source-drain doped region, and an implantation dose of the second source-drain implantation process is smaller than an implantation dose of the first source-drain implantation process.
3. The method for forming the semiconductor structure according to claim 1 or 2, wherein the step of forming the first source-drain doped region comprises: forming a first graphic layer on the substrate of the content addressable memory area, wherein the first graphic layer also covers the grid structure of the content addressable memory area;
performing a first source-drain injection process on the substrate on two sides of the grid structure of the unit memory area by taking the first graphic layer as a mask;
and removing the first pattern layer after the first source-drain injection process.
4. The method for forming a semiconductor structure according to claim 2, wherein the parameters of the first source-drain implantation process include: the implanted ions include one or more of P ions, As ions, and Sb ions, the implantation energy is 10Kev to 20Kev, and the implantation dose is 7E12 atoms per square centimeter to 1.2E13 atoms per square centimeter.
5. The method for forming the semiconductor structure according to claim 1 or 2, wherein the step of forming the second source-drain doped region comprises: forming a second graphic layer on the substrate of the unit memory area, wherein the second graphic layer also covers the grid structure of the unit memory area;
performing a second source-drain injection process on the substrates on two sides of the grid structure of the content addressable memory area by taking the second graphic layer as a mask;
and removing the second pattern layer after the second source-drain injection process.
6. The method for forming a semiconductor structure according to claim 2, wherein the parameters of the second source-drain implantation process include: the dopant ions include one or more of P ions, As ions, and Sb ions, the implantation energy is 10Kev to 20Kev, and the implantation dose is 5E12 atoms per square centimeter to 1E13 atoms per square centimeter.
7. The method for forming a semiconductor structure according to claim 1, wherein the step of forming the first source drain doped region comprises: forming first grooves in the substrate on two sides of the unit memory area grid structure; forming a first semiconductor layer in the first groove, and in-situ self-doping ions in the process of forming the first semiconductor layer;
or,
the step of forming the first source drain doped region comprises the following steps: forming first grooves in the substrate on two sides of the unit memory area grid structure; forming a first semiconductor layer in the first groove; and doping ions into the first semiconductor layer.
8. The method for forming a semiconductor structure according to claim 7, wherein the step of forming the second source-drain doped region comprises: forming second grooves in the substrate at two sides of the grid structure of the content addressable memory area; forming a second semiconductor layer in the second groove, and in-situ self-doping ions in the process of forming the second semiconductor layer, wherein the doping concentration of the second semiconductor layer is less than that of the first semiconductor layer;
or,
the step of forming the second source-drain doped region includes: forming second grooves in the substrate at two sides of the grid structure of the content addressable memory area; forming a second semiconductor layer in the second groove; and doping ions into the second semiconductor layer, wherein the doping concentration of the second semiconductor layer is less than that of the first semiconductor layer.
9. The method for forming the semiconductor structure according to claim 8, wherein a material of the first semiconductor layer is Si or SiC, and the dopant ions in the first semiconductor layer are N-type ions, and the N-type ions include one or more of P ions, As ions, and Sb ions;
the material of the second semiconductor layer is Si or SiC, the doped ions in the second semiconductor layer are N-type ions, and the N-type ions comprise one or more of P ions, As ions and Sb ions.
10. The method for forming a semiconductor structure according to claim 1, wherein the second source-drain doped region is formed after the first source-drain doped region is formed;
or after the second source-drain doped region is formed, the first source-drain doped region is formed.
11. The method of forming a semiconductor structure of claim 1, wherein in the step of forming a gate structure on the substrate, the gate structure further comprises: the gate dielectric layer is positioned on the floating gate layer, and the control gate layer is positioned on the gate dielectric layer.
12. A semiconductor structure, comprising:
a substrate including a cell memory area and a content addressable memory area; the unit memory area is used for forming a unit memory, and the content addressable memory area is used for forming a content addressable memory;
the grid structure is positioned on the substrate and comprises a tunneling oxide layer and a floating grid layer positioned on the tunneling oxide layer;
the first source-drain doped region is positioned in the substrate at two sides of the grid structure of the unit memory region;
and the second source-drain doped region is positioned in the substrate at two sides of the grid structure of the content addressable memory region, and the doping concentration of the second source-drain doped region is less than that of the first source-drain doped region.
13. The semiconductor structure of claim 12, wherein the dopant ions of the first source drain doped region comprise one or more of P ions, As ions, and Sb ions.
14. The semiconductor structure of claim 12, wherein the dopant ions of the second source drain doped region comprise one or more of P ions, As ions, and Sb ions.
15. The semiconductor structure of claim 12, wherein the gate structure further comprises: the gate dielectric layer is positioned on the floating gate layer, and the control gate layer is positioned on the gate dielectric layer.
16. The semiconductor structure of claim 12, wherein the first source drain doped region is made of a first semiconductor material having dopant ions, and the second source drain doped region is made of a second semiconductor material having dopant ions.
17. The semiconductor structure of claim 16, wherein the first semiconductor material is Si or SiC, and the dopant ions in the first semiconductor material comprise one or more of P ions, As ions, and Sb ions;
the second semiconductor material is Si or SiC, and the doping ions in the second semiconductor material comprise one or more of P ions, As ions and Sb ions.
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