CN109427884A - A kind of manufacturing method of dual buried layer groove power device - Google Patents
A kind of manufacturing method of dual buried layer groove power device Download PDFInfo
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- CN109427884A CN109427884A CN201710730491.9A CN201710730491A CN109427884A CN 109427884 A CN109427884 A CN 109427884A CN 201710730491 A CN201710730491 A CN 201710730491A CN 109427884 A CN109427884 A CN 109427884A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 230000009977 dual effect Effects 0.000 title claims description 39
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 229920005591 polysilicon Polymers 0.000 claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 14
- 239000003989 dielectric material Substances 0.000 claims abstract description 9
- 230000003647 oxidation Effects 0.000 claims abstract description 5
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 18
- -1 helium ion Chemical class 0.000 claims description 17
- 238000000407 epitaxy Methods 0.000 claims description 16
- 150000002500 ions Chemical class 0.000 claims description 16
- 238000002347 injection Methods 0.000 claims description 15
- 239000007924 injection Substances 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 6
- 239000001307 helium Substances 0.000 claims description 6
- 229910052734 helium Inorganic materials 0.000 claims description 6
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- REDXJYDRNCIFBQ-UHFFFAOYSA-N aluminium(3+) Chemical compound [Al+3] REDXJYDRNCIFBQ-UHFFFAOYSA-N 0.000 claims description 5
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 10
- 230000015556 catabolic process Effects 0.000 abstract description 8
- 239000012535 impurity Substances 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- 238000002513 implantation Methods 0.000 abstract 2
- 238000000206 photolithography Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 9
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 239000013589 supplement Substances 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000002146 bilateral effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229930002839 ionone Natural products 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
- H10D62/107—Buried supplementary regions, e.g. buried guard rings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
- H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
- H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/113—Isolations within a component, i.e. internal isolations
- H10D62/115—Dielectric isolations, e.g. air gaps
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
本发明涉及一种双重埋层沟槽功率器件的制造方法，制造有源区域，在P型外延层表面生长氧化硅层；采用光刻定义出第一沟槽形成区域；采用刻蚀工艺形成第一沟槽；在第一沟槽底部形成第一P型埋层；对第一沟槽底部进行刻蚀形成第二沟槽；在第二沟槽底部形成第二P型埋层；进行热氧化处理形成厚氧化硅层；填充多晶硅至溢出状态；去除P型外延层表面的氧化硅及多晶硅；沿第一沟槽边缘设置N型注入区域；在第一沟槽上方设置介质材料；填充金属。通过深槽刻蚀配合杂质注入的方法在N型漂移区内引入双重P型埋层，能够提高器件耗尽层耐压，减小器件导通电阻。厚氧化硅层能够提高沟槽底部弯角处的耐压能力，改善器件击穿特性。
The invention relates to a method for manufacturing a double-buried trench power device. The active area is manufactured, a silicon oxide layer is grown on the surface of a P-type epitaxial layer, a first trench formation area is defined by photolithography, and a first trench formation area is formed by an etching process. a trench; a first P-type buried layer is formed at the bottom of the first trench; a second trench is formed by etching the bottom of the first trench; a second P-type buried layer is formed at the bottom of the second trench; thermal oxidation is performed Processing to form a thick silicon oxide layer; filling polysilicon to overflow state; removing silicon oxide and polysilicon on the surface of the P-type epitaxial layer; setting an N-type implantation region along the edge of the first trench; setting a dielectric material above the first trench; filling metal. The double P-type buried layer is introduced into the N-type drift region by means of deep groove etching and impurity implantation, which can improve the withstand voltage of the depletion layer of the device and reduce the on-resistance of the device. The thick silicon oxide layer can improve the withstand voltage at the corners of the trench bottom and improve the breakdown characteristics of the device.
Description
Technical field
The present invention relates to power device fields, more particularly to a kind of manufacturing method of dual buried layer groove power device.
Background technique
Drain-source the two poles of the earth of trench vertical bilateral diffusion field-effect tranisistor (VDMOS) make electric current respectively in the two sides of period
It vertically circulates in device inside, increases current density, improve rated current, the conducting resistance of unit area is also smaller, is
A kind of power device that purposes is very extensive.
In the design process of groove power device, the contradiction of breakdown voltage and conducting resistance is the improved bottle of device performance
Neck.The breakdown point of groove power device concentrates on channel bottom corner, the reduction and ditch groove depth of drift region N-type epitaxy layer concentration
The increase of degree is conducive to reduce the big electric field of corner, but can also conducting resistance be made to become larger simultaneously.
Summary of the invention
To solve the above problems, the present invention adopts the following technical scheme: a kind of manufacture of dual buried layer groove power device
Method manufactures the active region of dual buried layer groove power device, comprising:
S1, selection are successively provided with the substrate of p-type epitaxial layer, N-type epitaxy layer and silicon wafer layer from top to bottom, in p-type epitaxial layer table
It looks unfamiliar long silicon oxide layer；
S2, use photoresist as resist exposure mask, first groove forming region is gone out using lithographic definition；
S3, first groove is formed using etching technics removal photoresist；
S4, in first groove bottom injecting p-type ion, and make P-type ion first groove bottom formed the first p type buried layer；
S5, again first groove bottom is performed etching to form second groove；
S6, again to second groove bottom injecting p-type ion, so that P-type ion is formed the second p type buried layer in second groove bottom；
S7, thermal oxidation is carried out to second groove, so that forming thick silicon oxide layer inside second groove；
S8, polysilicon is filled into first groove to overflow status；
S9, pass through the silica and polysilicon of etching removal p-type epi-layer surface；
S10, N-type injection zone is set along first groove edge, is embedded at N-type injection zone inside p-type epitaxial layer；
S11, dielectric material is set in first groove side, and so that dielectric material is formed medium holes by etching；
S12, metal is filled in p-type epi-layer surface and dielectric material surface, makes metal burden p-type epitaxial layer and dielectric material.
This manufacturing method is directed in slot type power device, the manufacturing method of active region, the manufacture in remaining region
Method is with no restrictions.
The operation principle of the present invention is that: it is introduced in N-type drift region by the method that deep etching cooperates impurity to inject double
Weight p type buried layer, dual p type buried layer can be improved device depletion layer pressure resistance, and identical resistance to pressure can reduce device on-resistance.Ditch
Trench bottom carries out thermal oxide and forms thick silicon oxide layer, can be improved the voltage endurance capability of channel bottom corner, to substantially improve
Breakdown characteristic of device.
Further, silicon oxide thickness is 1 μm ~ 10 μm in the S2 step.
Further, in S4 the and S6 step P-type ion include but is not limited to hydrogen ion, helium ion, boron ion, arsenic from
One of son, aluminium ion and/or a variety of compound ions.
Further, first groove bottom is embedded in inside N-type epitaxy layer, and second groove bottom is still in N-type extension
Layer is internal.
A kind of dual buried layer groove power device, including active region, the active region include that substrate, groove, p-type are buried
Layer, oxide layer and filled layer, the groove are set to substrate surface, and the p type buried layer includes the ring-type for being set to trenched side-wall
First p type buried layer and the second p type buried layer for being set to channel bottom, the oxide layer is set to trench interiors surface, described to fill out
It fills layer and is fastened on substrate surface.
A kind of dual buried layer groove power device improves the consumption of power device by the way that dual p type buried layer is arranged in the trench
Layer pressure resistance to the greatest extent, can reduce device on-resistance in identical resistance to pressure.Channel bottom carries out thermal oxide and forms thick silicon oxide layer energy
Enough improve the pressure resistance of channel bottom corner.So as to improve the breakdown of power device.
Further, the substrate includes p-type epitaxial layer, N-type epitaxy layer and the silicon wafer layer being successively arranged from top to bottom.
Further, the channel bottom is in inside N-type epitaxy layer.
Channel bottom guarantees charge compensation and exhausts to be normally carried out without departing from N-type epitaxy layer.
Further, the slot wedge is provided with N-type injection zone, and the N-type injection zone is embedded at p-type epitaxial layer
Surface.
The notch edges of groove are provided with N-type injection zone, the charge compensation that supplement is carried out with p-type epitaxial layer.
Further, the filled layer includes polysilicon block, medium block and metal layer, and the polysilicon block is set to groove
Inside, the medium block are set to above groove, and the metal layer is covered in substrate and medium block surface.
Filled layer is that polysilicon, the lid of filling in the trench are pressed on the medium block of groove notch, are covered in entire active area
The metal layer on surface collectively forms.For the necessary structure of active region.
Further, the p type buried layer includes but is not limited to by hydrogen ion, helium ion, boron ion, arsenic ion, aluminium ion
One of and/or a variety of compound ions constitute sheath.
The invention has the benefit that the present invention cooperates the method for impurity injection in N-type drift region by deep etching
Dual p type buried layer is introduced, dual p type buried layer can be improved device depletion layer pressure resistance, and identical resistance to pressure can reduce break-over of device
Resistance.Channel bottom carries out thermal oxide and forms thick silicon oxide layer, can be improved the voltage endurance capability of channel bottom corner, thus greatly
It is big to improve breakdown characteristic of device.
Detailed description of the invention
The invention will be further described for attached drawing, but the embodiments in the accompanying drawings do not constitute any limitation to the present invention.
Fig. 1 is a kind of manufacturing method S1 step signal for dual buried layer groove power device that one embodiment of the invention provides
Figure；
Fig. 2 is a kind of manufacturing method S2 step schematic diagram for dual buried layer groove power device that one embodiment of the invention provides；
Fig. 3 is a kind of manufacturing method S3 step schematic diagram for dual buried layer groove power device that one embodiment of the invention provides；
Fig. 4 is a kind of manufacturing method S4 step schematic diagram for dual buried layer groove power device that one embodiment of the invention provides；
Fig. 5 is a kind of manufacturing method S5 and S6 step signal for dual buried layer groove power device that one embodiment of the invention provides
Figure；
Fig. 6 is a kind of manufacturing method S7 step schematic diagram for dual buried layer groove power device that one embodiment of the invention provides；
Fig. 7 is a kind of manufacturing method S8 step schematic diagram for dual buried layer groove power device that one embodiment of the invention provides；
Fig. 8 is a kind of manufacturing method S9 step schematic diagram for dual buried layer groove power device that one embodiment of the invention provides；
Fig. 9 is manufacturing method S10, S11 and S12 step for a kind of dual buried layer groove power device that one embodiment of the invention provides
Rapid schematic diagram；
Figure 10 is a kind of structural schematic diagram for dual buried layer groove power device that one embodiment of the invention provides；
Figure 11 is a kind of overall structure diagram for dual buried layer groove power device that one embodiment of the invention provides.
Specific embodiment
As shown in Fig. 1-11, a kind of manufacturer for dual buried layer groove power device that one embodiment of the invention provides
Method, power device include: that scribe line area 1, cut-off ring 2, partial pressure region 3 and active region 4 manufacture dual as shown in figure 11
The active region 4 of buried layer groove power device, includes the following steps:
S1, selection are successively provided with the substrate 41 of p-type epitaxial layer 413, N-type epitaxy layer 412 and silicon wafer layer 411 from top to bottom, in P
413 surface growing silicon oxide layer 414 of type epitaxial layer, as shown in Figure 1；
S2, use photoresist 415 as resist exposure mask, 421 forming region of first groove is gone out using lithographic definition, such as Fig. 2 institute
Show；
S3, first groove 421 is formed using etching technics removal photoresist 415, as shown in Figure 3；
S4, in 421 bottom injecting p-type ion of first groove, and make P-type ion 421 bottom of first groove formed the first p-type bury
Layer 431, as shown in Figure 4；
S5, again 421 bottom of first groove is performed etching to form second groove 422, as shown in Figure 5；
S6, again to 422 bottom injecting p-type ion of second groove, so that P-type ion is formed the second p-type in 422 bottom of second groove
Buried layer 432, as shown in Figure 5；
S7, thermal oxidation is carried out to second groove 422, so that thick silicon oxide layer 414 is formed inside second groove 422, such as Fig. 6
It is shown；
S8, polysilicon 441 is filled into first groove 421 to overflow status, as shown in Figure 7；
S9, the silicon oxide layer 414 and polysilicon 441 that 413 surface of p-type epitaxial layer is removed by etching, as shown in Figure 8；
S10, N-type injection zone 443 is set along 421 edge of first groove, N-type injection zone 443 is made to be embedded at p-type epitaxial layer
Inside 413, as shown in Figure 9；
S11, medium block 442 is set above first groove 421, and so that medium block 442 is formed medium holes, such as Fig. 9 by etching
It is shown；
S12, metal 444 is filled on 413 surface of p-type epitaxial layer and 442 surface of medium block, makes 444 burden p-type epitaxial layer of metal
413 and medium block 442, as shown in Figure 9.
This manufacturing method is directed in slot type power device, the manufacturing method of active region, the manufacture in remaining region
Method is with no restrictions.
The operation principle of the present invention is that: it is introduced in N-type drift region by the method that deep etching cooperates impurity to inject double
Weight p type buried layer, dual p type buried layer can be improved device depletion layer pressure resistance, and identical resistance to pressure can reduce device on-resistance.Ditch
Trench bottom carries out thermal oxide and forms thick silicon oxide layer 414, can be improved the voltage endurance capability of channel bottom corner, to change significantly
Kind breakdown characteristic of device.
Further, in the S2 step silicon oxide layer 414 with a thickness of 1 μm ~ 10 μm.
Further, in S4 the and S6 step P-type ion include but is not limited to hydrogen ion, helium ion, boron ion, arsenic from
One of son, aluminium ion and/or a variety of compound ions.
Further, 421 bottom of first groove is embedded in inside N-type epitaxy layer 412, and 422 bottom of second groove is still located
Inside N-type epitaxy layer 412.
A kind of dual buried layer groove power device, including active region 4, the active region 4 include substrate 41, groove
42, p type buried layer 43, oxide layer and filled layer 44, the groove 42 are set to 41 surface of substrate, and the p type buried layer 43 includes setting
It is placed in the first p type buried layer of ring-type 431 of 42 side wall of groove and is set to the second p type buried layer 432 of 42 bottom of groove, the oxidation
Layer is set to 42 interior surface of groove, and the filled layer 44 is fastened on 41 surface of substrate.
A kind of dual buried layer groove power device improves power device by the way that dual p type buried layer 43 is arranged in the trench
Depletion layer pressure resistance, can reduce device on-resistance in identical resistance to pressure.42 bottom of groove carries out thermal oxide and forms thick silicon oxide
Layer 414 can be improved the pressure resistance of 42 bottom corner of groove.So as to improve the breakdown of power device.
Further, the substrate 41 includes p-type epitaxial layer 413,412 and of N-type epitaxy layer being successively arranged from top to bottom
Silicon wafer layer 411.
Further, the channel bottom is in inside N-type epitaxy layer 412.
Channel bottom guarantees charge compensation and exhausts to be normally carried out without departing from N-type epitaxy layer 412.
Further, 42 edge of groove is provided with N-type injection zone 443, and the N-type injection zone 443 is embedded at P
413 surface of type epitaxial layer.
The notch edges of groove are provided with N-type injection zone 443, the charge that supplement is carried out with p-type epitaxial layer 413 is mended
It repays.
Further, the filled layer includes 441 pieces of polysilicon, medium block 442 and 444 layers of metal, the polysilicon 441
Block is set to inside groove 42, and the medium block 442 is set to the top of groove 42,444 layers of the metal be covered in substrate 41 and
442 surface of medium block.
Filled layer 44 is the polysilicon 441 being filled in groove 42, covers the medium block 442 for being pressed on 42 notch of groove, covering
444 layers of metal in entire 4 surface of active region collectively form.For the necessary structure of active region 4.
Further, the p type buried layer 43 include but is not limited to by hydrogen ion, helium ion, boron ion, arsenic ion, aluminium from
The sheath that one of son and/or a variety of compound ions are constituted.
Each technical characteristic of embodiment described above can be combined arbitrarily, for simplicity of description, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, all should be considered as described in this specification.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously
It cannot therefore be construed as limiting the scope of the patent.It should be pointed out that coming for those of ordinary skill in the art
It says, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to protection of the invention
Range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.
Claims (10)
1. a kind of manufacturing method of dual buried layer groove power device, which is characterized in that manufacture dual buried layer groove power device
Active region, comprising:
S1, selection are successively provided with the substrate of p-type epitaxial layer, N-type epitaxy layer and silicon wafer layer from top to bottom, in p-type epitaxial layer table
It looks unfamiliar long silicon oxide layer；
S2, use photoresist as resist exposure mask, first groove forming region is gone out using lithographic definition；
S3, first groove is formed using etching technics removal photoresist；
S4, in first groove bottom injecting p-type ion, and make P-type ion first groove bottom formed the first p type buried layer；
S5, again first groove bottom is performed etching to form second groove；
S6, again to second groove bottom injecting p-type ion, so that P-type ion is formed the second p type buried layer in second groove bottom；
S7, thermal oxidation is carried out to second groove, so that forming thick silicon oxide layer inside second groove；
S8, polysilicon is filled into first groove to overflow status；
S9, pass through the silica and polysilicon of etching removal p-type epi-layer surface；
S10, N-type injection zone is set along first groove edge, is embedded at N-type injection zone inside p-type epitaxial layer；
S11, dielectric material is set above first groove, and so that dielectric material is formed medium holes by etching；
S12, metal is filled in p-type epi-layer surface and dielectric material surface, makes metal burden p-type epitaxial layer and dielectric material.
2. the manufacturing method of dual buried layer groove power device according to claim 1, it is characterised in that: in the S2 step
Silicon oxide thickness is 1 μm ~ 10 μm.
3. the manufacturing method of dual buried layer groove power device according to claim 1, it is characterised in that: the S4 and S6 step
P-type ion includes but is not limited to one of hydrogen ion, helium ion, boron ion, arsenic ion, aluminium ion and/or a variety of multiple in rapid
Close ion.
4. the manufacturing method of dual buried layer groove power device according to claim 1, it is characterised in that: first groove bottom
It is embedded in inside N-type epitaxy layer, second groove bottom is still in inside N-type epitaxy layer.
5. a kind of dual buried layer groove power device, it is characterised in that: including active region, the active region include substrate,
Groove, p type buried layer, oxide layer and filled layer, the groove are set to substrate surface, and the p type buried layer includes being set to groove
The first p type buried layer of ring-type of side wall and the second p type buried layer for being set to channel bottom, the oxide layer are set to trench interiors table
Face, the filled layer are fastened on substrate surface.
6. dual buried layer groove power device according to claim 4, it is characterised in that: the substrate include from top to bottom by
P-type epitaxial layer, N-type epitaxy layer and the silicon wafer layer of layer setting.
7. dual buried layer groove power device according to claim 5, it is characterised in that: the channel bottom is in outside N-type
Prolong inside layer.
8. dual buried layer groove power device according to claim 5, it is characterised in that: the slot wedge is provided with N-type
Injection zone, the N-type injection zone are embedded at p-type epi-layer surface.
9. dual buried layer groove power device according to claim 4, it is characterised in that: the filled layer includes polysilicon
Block, medium block and metal layer, the polysilicon block are set to trench interiors, and the medium block is set to above groove, the gold
Belong to layer and is covered in substrate and medium block surface.
10. dual buried layer groove power device according to claim 4, it is characterised in that: the p type buried layer includes but unlimited
In the sheath being made of one of hydrogen ion, helium ion, boron ion, arsenic ion, aluminium ion and/or a variety of compound ions.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710730491.9A CN109427884A (en) | 2017-08-23 | 2017-08-23 | A kind of manufacturing method of dual buried layer groove power device |
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| CN201710730491.9A CN109427884A (en) | 2017-08-23 | 2017-08-23 | A kind of manufacturing method of dual buried layer groove power device |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6566201B1 (en) * | 2001-12-31 | 2003-05-20 | General Semiconductor, Inc. | Method for fabricating a high voltage power MOSFET having a voltage sustaining region that includes doped columns formed by rapid diffusion |
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| CN105826195A (en) * | 2015-01-07 | 2016-08-03 | 北大方正集团有限公司 | Super junction power device and manufacturing method thereof |
| CN106158631A (en) * | 2015-03-25 | 2016-11-23 | 北大方正集团有限公司 | Band buried regions groove power device and preparation method thereof |
| CN106298533A (en) * | 2015-06-08 | 2017-01-04 | 北大方正集团有限公司 | The manufacture method of semiconductor device and semiconductor device |
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Application publication date: 20190305 |