CN109444727B

CN109444727B - Low-power consumption LFSR reseeding test compression method for scanning design

Info

Publication number: CN109444727B
Application number: CN201811097758.6A
Authority: CN
Inventors: 袁海英; 周昌世; 刘昶; 张凯; 郑彤
Original assignee: Beijing University of Technology
Current assignee: Beijing University of Technology
Priority date: 2018-09-20
Filing date: 2018-09-20
Publication date: 2021-01-05
Anticipated expiration: 2038-09-20
Also published as: CN109444727A

Abstract

The invention discloses a low-power consumption LFSR reseeding test compression method oriented to a scanning design structure, which solves the problems of excessive test power consumption caused by the traditional LFSR reseeding technology. The optimized coding algorithm based on the test cube can be flexibly combined with any LFSR reseeding scheme, and can be applied to the built-in self-test and functional verification of industrial-grade VLSI and SoC. The basic idea is as follows: The LFSR reseeding process randomly fills the uncertain bits in the test cube, which leads to an excessively high switching rate and test power consumption. The invention improves the logic consistency between adjacent bits in the test cube by optimizing the coding, and effectively reduces the test power consumption; by reducing the number of confirmed bits and the number of state equations in the test cube, the difficulty of solving the seed vector is reduced, and the test is effectively improved. Data compression ratio, alleviating the challenge of testing storage resources.

Description

Low-power consumption LFSR reseeding test compression method for scanning design

Technical Field

The invention belongs to the technical field of very large scale integrated circuits (VLSI), and particularly relates to a low-power consumption LFSR reseeding test compression method for scan design.

Background

As microelectronic technology and semiconductor technology enter the age of deep submicron systems, the process size of very large scale integrated circuits is gradually reduced and the clock frequency is continuously increased, and chip testing faces more and more challenges. With increasing data volume and excessive test power consumption being major issues facing today. Therefore, many test compression schemes have been proposed to reduce test storage and bandwidth, and the existing test data compression techniques mainly include code compression, broadcast scan compression and linear decompression structure-based compression. In comparison with the former two methods, the LFSR-based reseeding technique is adopted by most commercial tools because it has high test compression rate and low hardware overhead, such as TestKompress by Mentor Graphics, SOC BIST by Synopsys, and SmartBIST by cadence.

In addition, the power consumption density on the chip is also increasing continuously, the power consumption of the chip during testing is higher than that during normal operation, the width of the power consumption gap is changed between 2 and 5 times along with the continuous fluctuation of the function, and in some cases, the peak value of the test can even reach 30 times of the power consumption of the function. Although LFSR reseeding techniques can achieve satisfactory test coverage and higher test compression, they cause higher test power consumption. Since the test cube used for testing contains 95% -99% of the independent bits, during the LFSR reseeding test, a large number of the independent bits contained in the test cube are randomly filled, which causes too high switching activity when they are shifted into the scan chain, and thus too high test power consumption. Excessive power consumption can bring about sudden changes of the internal temperature of the device, damage of the device is caused, reliability is reduced, yield loss of the chip and test throughput are reduced, and accordingly working performance of the chip is reduced. Therefore, the invention provides a test scheme of a low-power consumption LFSR reseeding test compression technology oriented to scan design, aiming at the problem of higher test power consumption in the LFSR reseeding process and how to reduce the LFSR stage number and improve the coding efficiency. The overall idea of the method is to improve the compression efficiency of LFSR reseeding and reduce the test power consumption as the targets, firstly, a test cube is divided into data blocks with different types and equal lengths, then optimized coding is carried out according to the types of the data blocks, the test cube after optimized coding is solved into seed vectors, and the seed vectors are automatically loaded into an LFSR decompression circuit during chip test to generate a test mode compatible with the original test cube. According to the scheme, on the premise that the fault coverage rate is not influenced, the shift power consumption can be reduced, the determination position in the test cube can be greatly reduced, the test compression efficiency is improved, and the hardware overhead of the LFSR can be reduced.

Disclosure of Invention

The invention aims to solve the problem of high test power consumption caused by excessive frequent switching activities generated in the scanning process of a test mode generated in the LFSR seeding process, and provides a low-power consumption LFSR reseeding test compression method oriented to scanning design. The encoding technology can be combined with any LFSR reseeding scheme, and the test data capacity and the test power consumption are effectively reduced.

The invention specifically comprises the following contents:

1. optimized coding technique based on test cube

1.1 in order to reduce the number of definite bits in the test cube and to improve the logic consistency between adjacent bits of the test cube, the invention uses an optimized coding technique to perform block processing on the test cube. Before encoding, the test cube is divided into data blocks with equal length, and the four data block types of a compatible block 0, a compatible block 1, an incompatible block and an irrelevant block are respectively marked by using a 0, a 1 and an X holding mark bit.

1.2 to further reduce the number of definite bits in the test cube, the invention classifies the test cube blocks by using the marker bits, reorders the test cubes compatible with the marker bits, and classifies the test cubes into a keep-isolated group.

1.3 the flag bits of the different keep-isolated groups are updated, with an update bit of 1/0 indicating that the flag bits in the keep-isolated group need/need not be loaded once into the scan chain.

2. Solving LFSR seed vector

2.1 for the optimally coded test cube, the maximum bit S is determined_maxAnd setting the LFSR order L, and selecting a local polynomial as an LFSR characteristic polynomial to obtain a state transition matrix.

And 2.2, listing a state transition equation according to the LFSR state transition matrix, and solving by adopting a Gaussian Jordan elimination method. When the equation has a solution, calculating whether the LFSR under the order successfully encodes each test cube, and if so, obtaining the shortest LFSR seed under the block; if not, the order is L + 1. And when the equation is not solved, the order L +1 is made, the state transition equation is listed again for solving, and the calculation is stopped until one LFSR order is found, all the test cubes can be successfully coded, so that the LFSR seed under the block is obtained.

And 2.3, comparing the LFSR seeds obtained under each data block, and selecting the shortest LFSR seed to obtain the best block of the test cube.

LFSR reseeding technique

The idea of the low-power-consumption LFSR reseeding technology is that optimized encoding is carried out on a test cube with the purposes of reducing power consumption and improving LFSR encoding efficiency, a test cube set subjected to optimized encoding processing is encoded into smaller seed storage, the seed set is expanded into a determined test mode by using the LFSR during testing, test data compatible with the original test cube are obtained, and high fault coverage rate and high test compression rate are obtained while VLSI scanning test is carried out.

In order to achieve the purpose, the invention adopts the following technical scheme:

a low-power consumption LFSR reseeding test compression method for a scanning design structure comprises the following steps:

(1) obtaining a test set: aiming at the circuit faults which are still not testable after 10000 times of pseudo-random test modes are used, an ATPG tool provided by Atalanta is used for generating a deterministic test set of the faults difficult to test, and an LFSR reseeding test is carried out in an experiment;

(2) testing cubic partitioning treatment: dividing the test cube in the deterministic test set into data blocks equally, wherein the data block types comprise 0 compatible block, 1 compatible block, incompatible block and irrelevant block;

(3) test cube coding: carrying out block marking processing on different data block types;

(4) grouping into keep-isolated groups: extracting the marking bit of each testing cube, and dividing the testing cubes with compatible marking bits into groups;

(5) and 4, obtaining a test cube group with compatible mark bits according to the step 4, and adding the updated mark bits. When the update mark bit is 1, loading the mark bit and continuously loading the test cube into the scan chain; when the updating mark bit is 0, the mark bit is not loaded, and only the test cube is continuously loaded into the scan chain;

(6) solving the LFSR seed vector: selecting a proper LFSR characteristic polynomial for the test cube subjected to the optimized coding treatment according to the principle of the primitive polynomial, listing a state transition equation, and solving the shortest LFSR seed vector by using a Gaussian jordan elimination method;

(7) generating a test pattern: and loading the obtained seeds into an LFSR reseeding circuit, and obtaining a test pattern compatible with the original test set through a decoding circuit.

The testing of cubic blocks in step (2) aims to improve the logical consistency between adjacent bits. The test cube is divided into 0 compatible block, 1 compatible block, incompatible block and irrelevant block data types.

And (4) the test cube optimization coding in the step (3) aims to reduce the number of the determined bits and the number of the state equations and simplify the seed vector solving process. Block marker encoding is performed on the data block type.

The grouping of the encoded test cubes in steps (4) - (5) is intended to reduce the number of times test data is loaded into the scan chain. And grouping the test cubes compatible with the mark bits, and reducing the times of loading the compatible mark bits and the test cube groups thereof to the scan chain by updating the mark bits.

Solving the LFSR seed set in the steps (6) - (7) aims to reduce the number of equations and reduce the solution space. According to the primitive polynomial, listing a state transition equation by a characteristic polynomial, solving a shortest LFSR seed set, and storing the shortest LFSR seed set in a ROM; at the beginning of the scan test, a seed vector is loaded onto the reseeding circuit and expanded into a test pattern compatible with the original test data.

The invention has the following advantages:

firstly, the number of determined bits in a test cube is reduced by adopting an optimized coding algorithm, the number of state transition equations is reduced, the solution space of the equations is effectively released, the LFSR seed vector is easier to solve, and the test compression efficiency is improved.

Secondly, the problem of overhigh switch activity caused by the generation of the test mode by the LFSR reseeding technology is solved, the test power consumption is greatly reduced, and the method has practical significance for the design of a low-power-consumption test structure.

Drawings

FIG. 1 is a schematic diagram of a low power consumption test compression scheme based on LFSR reseeding in an embodiment of the present invention;

FIG. 1(a) is a schematic table of optimized coding based on test cubes in an embodiment of the present invention;

FIG. 1(b) is a schematic table of compression ratio and power consumption tests in an embodiment of the present invention;

FIG. 2 is a schematic diagram of the data format generated by an LFSR reseeding method in an embodiment of the present invention;

FIG. 3 is a schematic diagram of an LFSR reseed decoding circuit according to an embodiment of the present invention;

FIG. 4 is a diagram illustrating simulation results of a decoding circuit according to an embodiment of the present invention.

Detailed Description

The method of the present invention is further described with reference to the accompanying drawings and the following detailed description, wherein the specific steps of the present invention are as follows:

step 1: referring to FIG. 1, a test set of test circuits is obtained. The circuit is first test-covered by 10000 pseudorandom test patterns and then LFSR reseed for those hard-to-test faults, which determines that the test set was generated by the ATPG tool provided by Atalanta.

Step 2: with reference to fig. 1 and fig. 1(a), a test cube is subjected to block preprocessing, and different flag bits are added to data blocks according to different data types.

And step 3: according to fig. 1, the test cubes are sorted in groups according to the compatibility of the flag bits, and the update flag bits are added, so that whether the corresponding flag bits are loaded on the scan chain is determined, and the number of determination bits in the test cubes is reduced.

And 4, step 4: according to the attached figure 1, aiming at the test cube after optimized coding, a proper primitive polynomial is selected as an LFSR characteristic polynomial, a state transition equation is listed, and the shortest LFSR seed vector is solved by utilizing a Gaussian jordan elimination method.

And 5: with reference to fig. 1(a) and fig. 2, the test sequence (update bit + flag bit + data bit) after the seed is reseeded is generated by LFSR characteristic polynomial. And decoding to obtain a test mode compatible with the original test cube. The specific decoding process is as follows: assuming each scan chain length is M, the test cube is equally divided into B blocks. In the first clock cycle, the LFSR generates a bit update flag bit, and if the update flag bit is 1, in the next B clock cycles, the LFSR generates a flag bit for each scan chain. If the update flag bit is 0, no flag bit is generated. In the next M clock cycles, the LFSR generates test data for the circuit under test. And in each M/B clock cycles, if the corresponding mark bit is 1, directly loading the data generated by the LFSR into the scan chain, and if the corresponding mark bit is 0, repeatedly shifting the first bit of data generated by the LFSR into the scan chain by M/B cycles.

The effects of the present invention can be further illustrated by the following circuit experiment and simulation results.

1. Experiments and simulations

The experiment of the invention is carried out on part of ISCS-89 reference circuits, and the test set adopted by the experiment is generated by an Atalanta ATPG tool. The simulation experiment of the invention is carried out on Modalism of the Mentor company. The purpose of simulation and experiment is to analyze whether the optimized coding algorithm based on the test cube can improve the test compression and reduce the test power consumption.

Computer environment of simulation experiment of the invention: the operating system is windows 7; the software platform is as follows: modalism, Python.

2. Simulation content and results

Experiment 1, the present invention performed compression ratio and power consumption experiments at the ISCAS-89 reference circuit, and the obtained experimental results were used to verify the validity of the present invention, as shown in fig. 1 (b).

Simulation 1, the invention is used for carrying out simulation experiments on part of data in the interception test set to obtain a simulation graph based on an optimized coding algorithm, as shown in figure 4.

Claims

1. A low-power consumption LFSR reseed test compression method facing a scanning design structure is characterized by comprising the following steps:

(5) according to the step 4, a testing cube group with compatible mark bits is obtained, and the update mark bits are added to the testing cube group; when the update mark bit is 1, loading the mark bit and continuously loading the test cube into the scan chain; when the updating mark bit is 0, the mark bit is not loaded, and only the test cube is continuously loaded into the scan chain;

2. The low-power consumption LFSR reseeding test compression method for scan-oriented design structure as recited in claim 1, wherein the reseeded test sequence of the seed, i.e. update bit + marker bit + data bit, is generated by LFSR characteristic polynomial; decoding to obtain a test mode compatible with the original test cube; the specific decoding process is as follows: assuming each scan chain length is M, the test cube is equally divided into B blocks; in the first clock cycle, LFSR generates a bit of updating mark bit, if the updating mark bit is 1, in the next B clock cycles, LFSR will generate mark bit for each scan chain; if the update flag bit is 0, no flag bit is generated; in the next M clock cycles, the LFSR generates test data for the circuit to be tested; and in each M/B clock cycles, if the corresponding mark bit is 1, directly loading the data generated by the LFSR into the scan chain, and if the corresponding mark bit is 0, repeatedly shifting the first bit of data generated by the LFSR into the scan chain by M/B cycles.