CN109545672A - Wafer bonding method and bonded wafer - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000000227 grinding Methods 0.000 claims abstract description 31
- 238000009966 trimming Methods 0.000 claims abstract description 30
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 229910003460 diamond Inorganic materials 0.000 claims description 5
- 239000010432 diamond Substances 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims 2
- 235000012431 wafers Nutrition 0.000 abstract description 215
- 239000000377 silicon dioxide Substances 0.000 description 8
- 238000003801 milling Methods 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- 239000013078 crystal Substances 0.000 description 5
- 229910002808 Si–O–Si Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 125000002887 hydroxy group Chemical group [H]O* 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
- H10F39/026—Wafer-level processing
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/10—Integrated devices
- H10F39/12—Image sensors
- H10F39/199—Back-illuminated image sensors
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
一种晶圆键合方法以及键合晶圆，所述方法包括：提供第一晶圆，所述第一晶圆内形成有半导体器件，所述第一晶圆包括中心区域以及环绕所述中心区域的边缘区域；在所述第一晶圆的表面形成介质层；对所述第一晶圆进行边缘研磨修剪，以去除所述边缘区域表面的介质层，以及所述介质层覆盖的所述第一晶圆的一部分；提供第二晶圆；将所述第一晶圆与所述第二晶圆键合，其中，所述介质层朝向所述第二晶圆。本发明方案可以有效地避免在晶圆键合后斜坡平面与第二晶圆之间的夹缝容易产生空洞和灰边的问题，提高键合晶圆的品质。
A wafer bonding method and bonding wafer, the method comprising: providing a first wafer in which a semiconductor device is formed, the first wafer including a center area and a surrounding area of the center The edge area of the area; forming a dielectric layer on the surface of the first wafer; performing edge grinding and trimming on the first wafer to remove the dielectric layer on the surface of the edge area, and the dielectric layer covered by the dielectric layer. a portion of a first wafer; providing a second wafer; bonding the first wafer to the second wafer, wherein the dielectric layer faces the second wafer. The solution of the present invention can effectively avoid the problem of easy generation of voids and gray edges in the gap between the slope plane and the second wafer after wafer bonding, and improve the quality of the bonded wafers.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of wafer bonding methods and bonded wafer.
Background technique
Imaging sensor is the core component of picture pick-up device, realizes image taking function by converting optical signals into electric signal
Energy.By taking cmos image sensor (CMOS Image Sensors, CIS) device as an example, due to its tool
There is the advantages of low-power consumption and high s/n ratio, therefore is widely applied in various fields.
By taking back-illuminated type (Back-side Illumination, BSI) CIS as an example, in existing manufacturing process, first in device
Logical device, pixel device and metal interconnection structure are formed in part wafer, then by the front for carrying wafer and the device
The front bonding of wafer, and then the back of semiconductor substrate carried out thinned, and then CIS is formed at the back side of semiconductor substrate
Subsequent technique, such as latticed grid (Grid) is formed at the semiconductor substrate back side of the pixel device, in the grid
Between grid in form optical filtering (Filter) matrix etc..
Currently, in the technique that the front that will carry wafer is bonded with the front of the device wafers, in order to reduce wafer
The cavity at edge and grey side, it will usually deposit very thick oxidation film, crystal round fringes are then optimized by chemical mechanical grinding
Situation, but still there is cavity and grey side, a kind of wafer bonding method is needed, crystal round fringes are optimized.
Summary of the invention
The technical problem to be solved by the present invention is to provide a kind of wafer bonding method and bonded wafers, can be effectively avoided
The problem of the crack that wafer bonding retreads between slope plane and the second wafer is easy to produce cavity and grey side, bonded wafer is improved
Quality.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of wafer bonding method, comprising: it is brilliant to provide first
Justify, semiconductor devices is formed in first wafer, first wafer includes central area and the circular center
The fringe region in domain；Dielectric layer is formed on the surface of first wafer；Edge grinding trimming is carried out to first wafer, with
Remove a part of the dielectric layer on the fringe region surface and first wafer of dielectric layer covering；There is provided the
Two wafers；By first wafer and second wafer bonding, wherein the dielectric layer is towards second wafer.
Optionally, the material of the dielectric layer is selected from silica and silicon nitride.
Optionally, after forming the dielectric layer, the wafer bonding method further include: the dielectric layer is carried out
Planarization.
Optionally, the dielectric layer with a thickness of 500nm to 3000nm.
Optionally, edge grinding trimming is carried out to first wafer using milling apparatus；Wherein, the milling apparatus is
Cylindric diamond blade.
Optionally, in the fringe region, first wafer includes the first surface around the central area, and
Around the second surface of the first surface, wherein the first surface is plane, and the second surface is curved surface.
Optionally, first wafer is device wafers, and second wafer is carrying wafer.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of bonded wafer, comprising: the first wafer, described
It is formed with semiconductor devices in one wafer, first wafer includes central area and fringe region, the fringe region
A part of first wafer is removed to form groove；Dielectric layer covers the surface of the central area of first wafer, and not
Cover the groove；Second wafer, with first wafer bonding, wherein the dielectric layer is towards second wafer.
Optionally, the material of the dielectric layer is selected from silica and silicon nitride.
Optionally, first wafer is device wafers, and second wafer is carrying wafer.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that
In embodiments of the present invention, the first wafer is provided, is formed with semiconductor devices in first wafer, described first
Wafer includes central area and the fringe region around the central area；Medium is formed on the surface of first wafer
Layer；Edge grinding trimming is carried out to first wafer, to remove the dielectric layer and the medium on the fringe region surface
A part of first wafer of layer covering；Second wafer is provided；By first wafer and second wafer bonding,
In, the dielectric layer is towards second wafer.Using the above scheme, medium is formed on the surface of first wafer by elder generation
Then layer carries out edge grinding trimming to first wafer again, Jie on fringe region surface can be removed when grinding trimming
Matter layer also just eliminates the slope of dielectric layer edge region, compared with the prior art in first to the first wafer carry out edge grind
Mill trimming, re-forms dielectric layer, and then lead to dielectric layer edge region there are slopes, and then retreads slope plane in wafer bonding
Crack between the second wafer is easy to produce cavity and grey side, described due to eliminating using the scheme of the embodiment of the present invention
The crack to retread between slope plane and the second wafer in wafer bonding can be effectively avoided in the slope of dielectric layer edge region
The problem of being easy to produce cavity and grey side, improves the quality of bonded wafer.
Further, after forming the dielectric layer, further includes: the dielectric layer is planarized, compared to
In the prior art, the first wafer again planarize dielectric layer after edge grinding trimming, be easy to aggravate dielectric layer
Edge region the case where there are slopes, is carrying out edge grinding trimming to the first wafer using the scheme of the embodiment of the present invention
The dielectric layer is planarized before, further can effectively avoid retreading slope plane and the second wafer in wafer bonding
Between crack the problem of being easy to produce cavity and grey side, to further increase the quality of bonded wafer.
Further, in embodiments of the present invention, first wafer is device wafers, and second wafer is that carrying is brilliant
Circle helps to improve device wafers when being bonded device wafers with carrying wafer and carry the bonding quality of wafer, from
And improve the device quality of BSI CIS.
Detailed description of the invention
Fig. 1 to Fig. 5 is the corresponding device profile structural schematic diagram of each step in a kind of wafer bonding method in the prior art；
Fig. 6 is a kind of flow chart of wafer bonding method in the embodiment of the present invention；
Fig. 7 to Figure 11 is that the corresponding device profile structure of each step is shown in a kind of wafer bonding method in the embodiment of the present invention
It is intended to.
Specific embodiment
In existing BSI CIS technique, the front for needing to carry wafer is bonded with the front of the device wafers, in order to
Reduce the cavity and grey side of crystal round fringes, it will usually deposit very thick oxidation film, crystalline substance is then optimized by chemical mechanical grinding
The situation of the edge of the circle.However in the prior art, it is easy the presence of cavity and grey side, the device quality of CIS is caused to decline.
Fig. 1 to Fig. 5 is the corresponding device profile structural schematic diagram of each step in a kind of wafer bonding method in the prior art.
Referring to Fig.1, device wafers 100 are provided, could be formed with semiconductor devices in the device wafers 100, described half
Conductor device for example may include logical device, pixel device and metal interconnection structure etc..
Wherein, the device wafers 100 may include central area A and fringe region B, the fringe region B circular
The central area A.
Referring to Fig. 2, edge grinding trimming is carried out to the device wafers 100, to remove the device of the fringe region B surface
A part of part wafer 100.
In specific implementation, by carrying out edge grinding trimming to device wafers 100, not advising for crystal round fringes can be removed
Then region prevents edge from problem of Cracking occurs, and reduces the stress of device wafers 100, improves the semiconductor devices of formation
Quality.
Referring to Fig. 3, dielectric layer 101 is formed on the surface of the device wafers 100.
Wherein, the dielectric layer 101 is formed in the one side that device wafers 100 are ground after trimming, therefore dielectric layer 101 is in
It is step-like.
Referring to Fig. 4, the dielectric layer 101 is planarized.
It in specific implementation, can be using chemically mechanical polishing (Chemical Mechanical Polishing, CMP)
Technique planarizes the dielectric layer 101, to improve dielectric layer 101 in the consistency of the surface thickness of device wafers 100.
Referring to Fig. 5, carrying wafer 110 is provided, the device wafers 100 are bonded with the carrying wafer 110, wherein
The dielectric layer 101 is towards the carrying wafer 110.
Wherein, the material of the dielectric layer 101 can be silica.
Specifically, the dielectric layer 101 helps to promote to generate silicone hydroxyl key (Si-O-H) in carrying 110 interface of wafer
Structure Si-O-Si key is formed between two wafers, and be fixed on one by Si-O-Si key and then in subsequent annealing process
It rises.
The present inventor has found after study, in the prior art, first carries out edge grinding to device wafers 100 and repairs
It cuts, re-forms dielectric layer 101, be easy to cause dielectric layer 101 in marginal zone during planarizing dielectric layer 101
There is slope (Slope) in domain, such as the part irised out in Fig. 4 and Fig. 5.
Further, after being bonded the device wafers 100 with the carrying wafer 110, slope plane and second
It is easy to produce crack (Seam) between wafer, and then is easy to cause cavity and grey side.Wherein, difficult in the region where the cavity
To realize bonding, the ash side will lead to the problem of bond strength deficiency.
In embodiments of the present invention, the first wafer is provided, is formed with semiconductor devices in first wafer, described first
Wafer includes central area and the fringe region around the central area；Medium is formed on the surface of first wafer
Layer；Edge grinding trimming is carried out to first wafer, to remove the dielectric layer and the medium on the fringe region surface
A part of first wafer of layer covering；Second wafer is provided；By first wafer and second wafer bonding,
In, the dielectric layer is towards second wafer.Using the above scheme, medium is formed on the surface of first wafer by elder generation
Then layer carries out edge grinding trimming to first wafer again, Jie on fringe region surface can be removed when grinding trimming
Matter layer also just eliminates the slope of dielectric layer edge region, compared with the prior art in first to the first wafer carry out edge grind
Mill trimming, re-forms dielectric layer, and then lead to dielectric layer edge region there are slopes, and then retreads slope plane in wafer bonding
Crack between the second wafer is easy to produce cavity and grey side, described due to eliminating using the scheme of the embodiment of the present invention
The crack to retread between slope plane and the second wafer in wafer bonding can be effectively avoided in the slope of dielectric layer edge region
The problem of being easy to produce cavity and grey side, improves the quality of bonded wafer.
It is understandable to enable above-mentioned purpose of the invention, feature and beneficial effect to become apparent, with reference to the accompanying drawing to this
The specific embodiment of invention is described in detail.
Referring to Fig. 6, Fig. 6 is a kind of flow chart of wafer bonding method in the embodiment of the present invention.The wafer bonding method
May include step S21 to step S25:
Step S21: the first wafer is provided, is formed with semiconductor devices in first wafer, first wafer includes
Central area and the fringe region for surrounding the central area；
Step S22: dielectric layer is formed on the surface of first wafer；
Step S23: edge grinding trimming is carried out to first wafer, to remove the medium on the fringe region surface
A part of layer and first wafer of dielectric layer covering；
Step S24: the second wafer is provided；
Step S25: by first wafer and second wafer bonding, wherein the dielectric layer is towards described second
Wafer.
Above-mentioned each step is illustrated below with reference to Fig. 7 to Figure 11.
Fig. 7 to Figure 11 is that the corresponding device profile structure of each step is shown in a kind of wafer bonding method in the embodiment of the present invention
It is intended to.
Referring to Fig. 7, the first wafer 200 is provided, first wafer 200 may include central area A and surround described
The fringe region B of central area.
Wherein, it could be formed with semiconductor devices in first wafer 200.
In a kind of specific embodiment of the embodiment of the present invention, first wafer 200 can be device wafers
(Device Wafer), the second wafer can be carrying wafer (Carrier Wafer), then the semiconductor devices for example can be with
Including logical device, pixel device and metal interconnection structure etc..
The logical device may include the device of the transistors such as gate structure and source and drain doping area.It may be noted that
Be, in embodiments of the present invention, for specific logical device composition with no restriction.
The pixel device may include photodiode (Photo Diode, PD) and pixel circuit, wherein described
Pixel circuit may include forming selection transistor (Select Transistor), reset transistor (Reset
Transistor) and source with the various transistors appropriate such as transistor (Source Follower Transistor) device
Part, for example, may include transmission grid (Transfer Gate, TG) and floating diffusion region (Floating Diffusion,
FD).It should be pointed out that in embodiments of the present invention, for specific pixel circuit composition with no restriction.
In another specific embodiment of the embodiment of the present invention, first wafer 200 can be logic wafer
(Logic Wafer), the second wafer can be pixel wafer (Pixel Wafer), then may include in first wafer 200
Logical device may include pixel device in second wafer.
Referring to Fig. 8, dielectric layer 201 is formed on the surface of first wafer 200.
Wherein, the material of the dielectric layer 201 can be selected from silica and silicon nitride.
Further, the silica for example can be SiO2, the silicon nitride for example can be Si3N4。
Preferably, the silica can be prepared using ethyl orthosilicate (TEOS), to improve the dielectric layer 201
Quality and compactness.
Further, the thickness of the dielectric layer 201 can be 500nm to 3000nm.
It should be pointed out that the thickness of the dielectric layer 201 should not be blocked up, otherwise will increase flatening process when
It is long；The thickness of the dielectric layer 201 should not be excessively thin, otherwise can reduce bonding effect.
It in embodiments of the present invention, can be flat by the setting dielectric layer 201 with a thickness of 500nm to 3000nm
After smooth chemical industry skill, obtain dielectric layer 201 with a thickness of 300nm to 1200nm, to meet bonding demand.
Further, in the fringe region B, first wafer 200 may include around the of the central area A
One surface B1, and the second surface B2 around the first surface B1, wherein the first surface B1 is plane, described the
Two surface B2 are curved surface.
In embodiments of the present invention, plane is showed by the way that first surface B1 is arranged, and the first wafer 200 is ground
The region of trimming includes first surface B1, it can be ensured that it is brilliant to be located at first in the edges of regions trimmed to the first wafer 200
In the plane of circle 200, to improve the bonding effect of the first wafer 200 and the second wafer after subsequent bonding technology.
Referring to Fig. 9, edge grinding trimming is carried out to first wafer 200, to remove Jie of the fringe region B surface
The a part for first wafer 200 that matter layer 201 and the dielectric layer 201 cover.
In specific implementation, by carrying out edge grinding trimming to the first wafer 200, not advising for crystal round fringes can be removed
Then region prevents edge from problem of Cracking occurs, and reduces the stress of device wafers 200, improves the semiconductor devices of formation
Quality.
In embodiments of the present invention, due to being initially formed dielectric layer 201, then edge grinding trimming is carried out to the first wafer 200,
A part of dielectric layer 201 can be removed when removing a part at edge of the first wafer 200.
It is possible to further carry out edge grinding trimming to first wafer using milling apparatus；Wherein, the grinding
Equipment is cylindric diamond blade.
In specific implementation, the milling apparatus can be cylindric diamond blade.It specifically, can be to the first crystalline substance
Circle 200 carries out center rotation, and carries out edge to first wafer 200 using the cylindric diamond blade of rotation and grind
Mill trimming, to reduce the thickness of the fringe region B of the first wafer 200.Wherein, described can be one or more.
It should be pointed out that can also be trimmed using other milling apparatus appropriate, it is in embodiments of the present invention, right
In milling apparatus specific structure and implementation with no restriction.
Referring to Fig.1 0, after forming the dielectric layer 201, the dielectric layer 201 can also be planarized.
In specific implementation, the dielectric layer 201 can be planarized using CMP process, to improve dielectric layer 201
In the consistency of the surface thickness of the first wafer 200.
In embodiments of the present invention, by being initially formed institute before carrying out edge grinding trimming to first wafer 200
It states dielectric layer 201 and the dielectric layer 201 is planarized, compared in the prior art, edge is carried out to the first wafer
Dielectric layer is planarized again after grinding trimming, is easy to aggravate dielectric layer edge region the case where there are slopes, use
The scheme of the embodiment of the present invention further can effectively avoid the crack to retread between slope plane and the second wafer in wafer bonding
The problem of being easy to produce cavity and grey side, to further increase the quality of bonded wafer.
Referring to Fig.1 1, the second wafer 210 is provided, first wafer 201 is bonded with second wafer 210, wherein
The dielectric layer 201 is towards second wafer 210.
In specific implementation, when being bonded to the first wafer 201 with second wafer 210, by the first wafer
201 with the bonding face metallization medium layer 201 of second wafer 210, then by being activated to dielectric layer 201, at interface
The structure that place generates silicone hydroxyl key (Si-O-H) forms Si-O-Si between two wafers during subsequent annealed
Key, and be fixed together by Si-O-Si key.
In embodiments of the present invention, dielectric layer is formed on the surface of first wafer 200 by elder generation, then again to described
First wafer 200 carries out edge grinding trimming, the dielectric layer 201 on fringe region surface can be removed when grinding trimming, also
Eliminate the slope of 201 edge region of dielectric layer, compared with the prior art in first to the first wafer carry out edge grinding trimming,
Dielectric layer is re-formed, and then leads to dielectric layer edge region there are slope, and then is retreaded slope plane and second in wafer bonding
Crack between wafer is easy to produce cavity and grey side, using the scheme of the embodiment of the present invention, due to eliminating the dielectric layer
The crack to retread between slope plane and the second wafer 210 in wafer bonding can be effectively avoided in the slope of 201 edge regions
The problem of being easy to produce cavity and grey side, improves the quality of bonded wafer.
In embodiments of the present invention, a kind of bonded wafer can also be provided, may include: the first wafer as shown in figure 11
200, semiconductor devices is formed in first wafer 200, first wafer 200 includes central area and marginal zone
The a part in domain, the first wafer of the fringe region is removed to form groove；Dielectric layer 201 covers first wafer
The surface of 200 central area, and the groove is not covered；Second wafer 210 is bonded with first wafer 201, wherein
The dielectric layer 201 is towards second wafer 210.
Further, the material of the dielectric layer 201 can be selected from silica and silicon nitride.
Further, first wafer 200 can be device wafers, and second wafer 210 can be carrying wafer.
The pass above and shown in Fig. 6 to Figure 10 is please referred to about the principle of the bonded wafer, specific implementation and beneficial effect
In the associated description of the forming method of bonded wafer, details are not described herein again.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (10)
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110534423A (en) * | 2019-09-19 | 2019-12-03 | 武汉新芯集成电路制造有限公司 | Semiconductor devices and preparation method thereof |
| CN112289694A (en) * | 2020-10-30 | 2021-01-29 | 长江存储科技有限责任公司 | Wafer bonding method |
| CN114420549A (en) * | 2022-03-31 | 2022-04-29 | 深圳新声半导体有限公司 | Method for bonding silicon dioxide surface and silicon surface at low temperature |
| CN119137707A (en) * | 2022-05-18 | 2024-12-13 | 原子能与替代能源委员会 | Method for transferring layers from a source matrix to a target matrix |
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| CN114420549A (en) * | 2022-03-31 | 2022-04-29 | 深圳新声半导体有限公司 | Method for bonding silicon dioxide surface and silicon surface at low temperature |
| CN119137707A (en) * | 2022-05-18 | 2024-12-13 | 原子能与替代能源委员会 | Method for transferring layers from a source matrix to a target matrix |
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