CN109613331B - Load detection method and method for alternating current charging pile based on double-load array - Google Patents
Load detection method and method for alternating current charging pile based on double-load array Download PDFInfo
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Abstract
The application provides an alternating current charging pile detection load and a method based on a double-load array, wherein the load comprises: the device comprises a first resistor array, a second resistor array, a current transformer, a voltage transformer, a first A/D converter, a second A/D converter, a DSP processing unit, a relay driving chip and a silicon controlled rectifier driving circuit. This application can realize the current-voltage detection to load circuit through DSP processing unit to can adjust first resistance array and second resistance array's resistance through DSP processing unit, cooperate appropriate detection method or appropriate digital processing logic circuit, can realize filling quick detection of electric pile and quick adjustment resistance load tracking power grid power change, realize filling electric pile active power or the rapid detection of active power to single-phase alternating current.
Description
Technical Field
The application relates to the technical field of power grids, in particular to a load detection method and a load detection device for an alternating current charging pile based on a double-load array.
Background
Along with the development of electric automobile, alternating-current charging stake is more and more, and alternating-current charging stake's detection and maintenance are more and more important. It is common practice in the industry to use an ac charging post to sense a load to simulate charging of an electric vehicle.
The AC charging pile load box in the current market has two types of adjustable load and fixed load, and the load accuracy is generally +/-5%.
However, at present, the charging pile measures the accuracy of active electric energy by using an electric energy comparison method, the measuring speed is very slow, and the time difference for detecting one point is almost 30 minutes under the minimum working current, so that the method for quickly detecting the active electric energy of the single-phase alternating-current charging pile is needed to meet the future millions of charging pile detection requirements.
Moreover, the traditional load accuracy is low, and due to the influence of voltage fluctuation of a power grid, the fluctuation of active power for testing a charging pile is large, the active power cannot be directly detected, the active power can only be detected by using a pulse method or an electric energy comparison method, the speed is low, and the efficiency is low.
Disclosure of Invention
The application provides a load detection method and a load detection method for an alternating current charging pile based on a double-load array, rapid detection of the charging pile is achieved, the essence of the method is that alternating current constant power capable of rapidly tracking voltage of a power grid and temperature change of the load is provided, rapid detection of active power (direct measurement method) or active power of a single-phase alternating current charging pile is achieved, and the method can also be used for providing stable alternating current loads for other tests.
In view of this, the present application provides in a first aspect an ac charging pile detecting load based on a dual-load array, including: the device comprises a first resistor array, a second resistor array, a current transformer, a voltage transformer, a first A/D converter, a second A/D converter, a DSP processing unit, a relay driving chip and a silicon controlled rectifier driving circuit;
the resistors of the first resistor array are connected in series with a relay and are controlled by the relay to be switched; the resistors of the second resistor array are connected in series with a bidirectional thyristor and are controlled to be switched by the bidirectional thyristor;
the first resistor array and the second resistor array are connected in parallel and then connected to an alternating current charging pile to be detected to form a load circuit;
the DSP processing unit is connected with the load circuit through the first A/D converter and the current transformer and is used for detecting the current of the load circuit;
the DSP processing unit is connected with the load circuit through the second A/D converter and the voltage transformer and is used for detecting the voltage of the load circuit;
the DSP processing unit is connected with the relay through the relay driving chip and is used for controlling the first resistor array to be switched into the resistor of the load circuit;
the DSP processing unit is connected with the bidirectional controllable silicon through the controllable silicon driving circuit and used for controlling the resistance of the second resistance array to be input into the load circuit.
Preferably, an IV feedback resistor and a first operational amplifier are further connected between the first a/D converter and the current transformer.
Preferably, a second operational amplifier is further connected between the second a/D converter and the voltage transformer.
Preferably, the system further comprises a human-computer interaction unit, wherein the human-computer interaction unit is connected with the DSP processing unit and is used for inputting a control signal to the DSP processing unit.
Preferably, the resistance value of the first resistor array is smaller than the resistance value of the second resistor array.
Preferably, the resistance values of the first resistor array and the second resistor array are sequentially increased by an exponential multiple of a preset value.
Preferably, the resistance value of the resistor with the largest resistance value in the first resistor array is the same as that of the resistor with the smallest resistance value in the second resistor array, so that switching of the relay switch of the first resistor array can be avoided or reduced.
The second aspect of the present application provides a method for detecting an ac charging pile based on a dual-load array, which is based on the first aspect, and includes:
s1, acquiring a preset set output power value Pset;
s2, calculating and outputting corresponding IO values of the first resistor array and the second resistor array according to the set output power value Pset and the voltage value U detected by the voltage sensor;
s3, calculating the current active power Pm according to the current value I detected by the current sensor and the voltage value U detected by the voltage sensor;
s4, calculating a difference value between the set output power value Pset and the current active power Pm, controlling the switching of the first resistor array and the second resistor array through the IO port, and increasing or decreasing the input resistance;
wherein, the steps S3 and S4 are repeatedly performed at preset time intervals.
Preferably, the step S2 specifically includes:
calculating the actual set current according to the current actual voltage as follows: iset is Pset/U;
calculating the IO value of the first resistor array as: MSB ═ floor ((Iset-0.5 × I1b)/I1 b);
calculating the IO value of the second resistor array as follows: LSB round (Iyu/I2b), Iyu Iset-MSB × I1 b;
the MSB is an output value of the IO port corresponding to the DSP processing unit and the first resistor array, floor () is rounded down, I1b is a minimum current provided by the first resistor array, LSB is an output value of the IO port corresponding to the DSP processing unit and the second resistor array, round () is rounded up, I2b is a minimum current provided by the second resistor array, and Iyu is a remainder current value.
Preferably, the step S4 includes:
calculating a difference value between the set output power value Pset and the current active power Pm: perr ═ (Pset-Pm);
the error in power translates into an error in resistance: rerr ═ 220 × 220)/Perr;
calculating the total resistance of the resistor array input in the calculation: r (n) ═ R (n-1) + K × Rerr;
wherein, R (n) is the total resistance of the resistor array which is added in the current calculation, R (n-1) is the total resistance of the resistor array which is added in the last calculation, K is-1, and n is the number of the sampling point.
Preferably, the step S3 includes:
calculating the numerical value N: n ═ round (fs/Freq);
calculate the average power of 2 cycles before sample point n:
taking the average power Pm (n) of 2 periods before the sampling point n as the current active power Pm calculated in the step S3;
wherein fs is the sampling rate of AD, Freq is the frequency of charging pile voltage, uiAnd iiThe voltage and current corresponding to the sampling point in the two cycles before the nth point.
According to the technical scheme, the method has the following advantages:
the application provides an alternating current charging pile detection load and a method based on a double-load array, wherein the load comprises: the device comprises a first resistor array, a second resistor array, a current transformer, a voltage transformer, a first A/D converter, a second A/D converter, a DSP processing unit, a relay driving chip and a silicon controlled rectifier driving circuit; the resistors of the first resistor array are connected in series with a relay and are controlled by the relay to be switched; the resistors of the second resistor array are connected in series with a bidirectional thyristor and are controlled to be switched by the bidirectional thyristor; the first resistor array and the second resistor array are connected in parallel and then connected to an alternating current charging pile to be detected to form a load circuit; the DSP processing unit is connected with the load circuit through the first A/D converter and the current transformer and is used for detecting the current of the load circuit; the DSP processing unit is connected with the load circuit through the second A/D converter and the voltage transformer and is used for detecting the voltage of the load circuit; the DSP processing unit is connected with the relay through the relay driving chip and is used for controlling the first resistor array to be switched into the resistor of the load circuit; the DSP processing unit is connected with the bidirectional controllable silicon through the controllable silicon driving circuit and used for controlling the resistance of the second resistance array to be input into the load circuit. This application can realize the current-voltage detection to load circuit through DSP processing unit to can adjust first resistance array and second resistance array's resistance through DSP processing unit, cooperate appropriate detection method or appropriate digital processing logic circuit, can realize filling quick detection of electric pile and quick adjustment resistance load tracking power grid power change, realize filling electric pile active power or the rapid detection of active power to single-phase alternating current.
Drawings
In order to illustrate the embodiments of the present application more clearly, the drawings that are needed for describing the embodiments or prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained by those skilled in the art without inventive exercise.
Fig. 1 is a circuit diagram of an embodiment of a dual-load array based ac charging post for detecting a load according to the present application;
fig. 2 is a circuit diagram of a relay driving chip in an embodiment of detecting a load by an ac charging pile based on a dual-load array according to the present application;
fig. 3 is a circuit diagram of a thyristor driving circuit in an embodiment of the present application for detecting a load by an ac charging pile based on a dual-load array;
fig. 4 is a circuit diagram of a DSP processing unit in an embodiment of a dual-load array based ac charging post for detecting a load according to the present application;
fig. 5 is a flowchart of an embodiment of a method for detecting an ac charging pile based on a dual load array according to the present application;
fig. 6 is another flowchart of an embodiment of a method for detecting an ac charging pile based on a dual load array according to the present application;
fig. 7 is a flowchart of calculating a resistance change in an embodiment of a method for detecting an ac charging pile based on a dual load array according to the present application;
wherein the reference numerals are:
the device comprises a first resistor array 1, a second resistor array 2, an alternating current charging pile 3, a current transformer 4, a voltage transformer 5, a first operational amplifier 6, a second operational amplifier 7, an IV feedback resistor 8, a first A/D converter 9, a second A/D converter 10, a DSP processing unit 11, a human-computer interaction unit 14, a relay driving chip 12, a silicon controlled rectifier driving circuit 13, a human-computer interaction unit 14 and a switching power supply 15.
Detailed Description
The application provides a load detection method and a load detection method for an alternating current charging pile based on a double-load array, rapid detection of the charging pile is achieved, the essence of the method is that alternating current constant power capable of rapidly tracking voltage of a power grid and temperature change of the load is provided, rapid detection of active power (direct measurement method) or active power of a single-phase alternating current charging pile is achieved, and the method can also be used for providing stable alternating current loads for other tests.
In order to make the objects, features and advantages of the present invention more apparent and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the embodiments described below are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, an embodiment of a dual-load array-based ac charging post for detecting a load according to the present application includes: the system comprises a first resistor array 1, a second resistor array 2, a current transformer 4, a voltage transformer 5, a first A/D converter 6, a second A/D converter 7, a DSP processing unit 11, a relay driving chip 12 and a silicon controlled rectifier driving circuit 13;
the resistors of the first resistor array 1 are all connected in series with a relay and are controlled by the relay to be switched; the resistors of the second resistor array 2 are all connected in series with a bidirectional thyristor and are controlled to be switched by the bidirectional thyristor;
it should be noted that the switching in this application means that, because the resistance is connected in series with the relay, when the relay is disconnected, the resistance is not connected to the circuit, which is equivalent to "cut off", and when the relay is connected, the resistance is connected to the circuit, that is, "put in", and the situation of the silicon controlled rectifier is the same.
The first resistor array 1 and the second resistor array 2 are connected in parallel and then connected to an alternating current charging pile 3 to be detected to form a load circuit; specifically, the load circuit is a circuit composed of a first resistor array 1, a second resistor array 2, an alternating current charging pile 3 and a conducting wire.
The DSP processing unit 11 is connected with a load circuit through a first A/D converter 9 and a current transformer 4 and is used for detecting the current of the load circuit;
the DSP processing unit 11 is connected with a load circuit through a second A/D converter 10 and a voltage transformer 5 and is used for detecting the voltage of the load circuit;
the DSP processing unit 11 is connected with a relay through a relay driving chip 12 and is used for controlling the resistance of the first resistance array 1 which is put into a load circuit;
the DSP processing unit 11 is connected with a bidirectional thyristor through a thyristor driving circuit 13 and is used for controlling the resistance of the second resistor array 2 which is put into a load circuit.
This application can realize the current-voltage detection to load circuit through DSP processing unit 11 to can adjust first resistance array 1 and second resistance array 2's resistance through DSP processing unit 11, cooperate appropriate detection method or appropriate digital processing logic circuit, can realize filling quick detection and the quick adjustment resistance load of electric pile 3 and track the power grid power change, realize filling 3 active power or the rapid detection of active power of electric pile to single-phase alternating current.
Further, an IV feedback resistor 8 and a first operational amplifier 6 are connected between the first a/D converter 9 and the current transformer 4. Specifically, the circuit connection is made in a manner to amplify the signal, as shown in fig. 1.
Further, a second operational amplifier 7 is connected between the second a/D converter 10 and the voltage transformer 5. Specifically, the circuit connection is made in a manner to amplify the signal, as shown in fig. 1.
Further, the system also comprises a human-computer interaction unit 14, wherein the human-computer interaction unit 14 is connected with the DSP processing unit 11 and is used for inputting a control signal to the DSP processing unit 11. The human-computer interaction unit 14 can receive a set output power value Pset signal, a set parameter signal or a start signal, an exit load signal and the like input by a worker. May be a device having a display screen, and the operator performs signal input by clicking the display screen or pressing a physical button.
Further, the resistance value of the first resistor array 1 is smaller than that of the second resistor array 2, so that the resistance value adjustment of the first resistor array 1 can be distinguished from the resistance value adjustment of the second resistor array 2, namely, one small resistor is adjusted, and the other large resistor is adjusted to perform coarse adjustment and fine adjustment.
Further, the resistance values of the first resistor array 1 and the second resistor array 2 are sequentially increased by an exponential multiple of a preset value. The exponential increase can make the regulation more sensitive, and the resistance setting is more suitable. An exponential multiplication length of a predetermined value means, for example, an exponential multiplication length of 2 (predetermined value of 2), and then the first resistor is R, the second is 2R, and the third is 22R, fourth is 23R, n is 2(n-1)And R is shown in the specification. That is, all resistors of the first resistor array 1 and the second resistor array 2 are arranged together, the resistor of the first resistor array 1 is arranged in front of the resistor, and the resistor of the second resistor array 2 is arranged behind the resistor, and then the resistors are sequentially increased by exponential times of a preset value. R is the minimum resistance of the load array and may be 10 ohms.
Further, the resistance value of the resistor with the largest resistance value in the first resistor array 1 is the same as the resistance value of the resistor with the smallest resistance value in the second resistor array 2. The resistance value of the resistor with the largest resistance value in the first resistor array 1 is the same as that of the resistor with the smallest resistance value in the second resistor array 2, so that switching of the relay switch of the first resistor array 1 can be avoided or reduced.
According to an embodiment of the present application, the present application provides the following use case:
in the application example of the present application, the first resistor array 1 is a high-power resistor array, and the second resistor array 2 is a low-power resistor array.
As shown in fig. 1, the single-phase ac charging pile detection load (hereinafter referred to as detection load) that performs adjustment based on a dual-load array and constant power is composed of a first resistor array 1, a second resistor array 2, a current transformer 4, a voltage transformer 5, an operational amplifier 6, an operational amplifier 7, an IV feedback resistor 8, an a/D converter 9, an a/D converter 10, a DSP processing unit 11, a human-computer interaction unit 14, a relay driving chip 12, and a thyristor driving circuit 13.
Wherein, the first resistor array 1 comprises 5 resistors with numbers of R1-R5 and resistance values of { R,21R,...24R, and 5 control relays { S0, S1.., S4 };
the method is used for controlling main loads, and is characterized in that the control current is large, the relay control is used, and the relay control has the characteristics of large power but long switching time (5-100 ms), so that the method mainly uses slow speed and infrequent control.
The second resistor array 2 comprises 20 resistors with the numbers of R5 'to R24' and the resistance value of {24R,25R,26R,...223R, and 20 triacs G5, G6., G24, which allow for fast turn-off and zero-crossing timesThe high-power switch-on circuit is quickly started (10 microseconds), stable power switching and frequent switching can be realized by matching with AD (analog-to-digital) circuits, wherein the resistance value of R5' is the same as that of the resistor R5 of the high-power array 1, the purpose is to ensure that the first resistor array 1 is switched according to an underload rule, namely the active power value of the first resistor array 1 which is switched in advance is smaller than an actual set value, and the rest part is compensated by the second resistor array 2 in real time through an algorithm, so that switching of a relay switch of the first resistor array 1 can be avoided or reduced. Therefore, the resistance value of the resistor with the largest resistance value in the first resistor array 1 is the same as the resistance value of the resistor with the smallest resistance value in the second resistor array 2, so that switching of the relay switch of the first resistor array 1 can be avoided or reduced.
The current transformer 4 adopts a 0.01-level zero-flux current transformer, so that the measuring accuracy is ensured.
The voltage transformer 5 adopts a 0.01-level bipolar voltage transformer, so that the measuring accuracy is ensured.
The switching power supply 15 will provide +/-5V operating power for chip operation through L and N.
The operational amplifier 6 and the operational amplifier 7 adopt OPA343, the harmonic distortion and noise are less than 0.0007%, and the accuracy of measurement is guaranteed.
The IV feedback resistor 8 uses a precision resistor with a temperature drift of 1ppm (parts per million) and an initial accuracy of 0.01%, ensuring the accuracy of the measurement.
The a/ D converters 9 and 10 use a 24-Bit SAR type a/D converters AD7767, guaranteeing high accuracy and resolution up to 24 bits (1/224 ═ 5.6 × 10 "8), while the sampling rate is set to 5KHz (integrated cost/performance ratio).
The human-computer interaction unit 14 can implement performance display and keyboard input.
As shown in fig. 2, the relay driver chip 12 is a relay driver integrated chip ULN2003, and is directly driven and controlled by the high-order 5 bits (MSB) of the IO port of the DSP processing unit 11, i.e., IO1 to IO5, and the output is an open-drain output connected to the negative terminals of the five relay coils of the first resistor array 1. The right 5 circles in FIG. 2 represent the five relay coils from S0 to S4.
The thyristor drive circuit 13 is composed of a 5V to 5V isolation power supply 135, a drive resistor Rin 131, an optical isolator 132, an output pull-up resistor Rout 133 and a tracking drive amplifier 134 as shown in fig. 3, wherein the 5V to 5V isolation power supply 135 realizes 5V to 5V isolation output and outputs current 1A, meanwhile, the output ground is connected with a live wire L1, the Rin 131 drive resistor Rin and a patch resistor with the output pull-up resistor Rout 133 being 1K, the optical isolator 132 uses 6N137 of 10MHz, and the tracking drive amplifier 134 is a track-to-track budget amplifier with a power of more than 50 mA. The purpose of the tracking driver amplifier 134 is to increase the driving current and control the thyristors reliably, while there are 20 general control circuits to distribute the 20 thyristors that control the second resistor array 1.
The DSP processing unit 11 is shown in fig. 4, the DSP processing unit 11 samples an ADSP BF609 chip, the ADSP BF609 chip has very rich on-chip resources, only part of the resources are used in the design, the SPI 2112 is used for communication of the a/D converter 10, the SPI 1111 is used for communication of the a/D converter 9, the high-order MSB of the IO is used for controlling 5 relays of the first resistor array 1, the high-order LSB of the IO is used for controlling 20 triacs of the second resistor array 2, the intermediate module (processor or digital signal logic operation circuit) realizes real-time calculation of active power and control of the IO output adjustment amount, and the control management 110 is responsible for communication with the human-computer interaction unit 14.
As shown in fig. 1, a primary a end of a voltage transformer 5 is connected to a live wire input L1, a primary X end is connected to a neutral wire input N, a secondary output a, X of the voltage transformer 5 is connected to an input of an operational amplifier 7, a primary access neutral wire N of a current transformer 4, a secondary output S1, S2 is connected to an input of the operational amplifier 6, an output of the operational amplifier 6 is connected to an input of an a/D converter 9, an output of the operational amplifier 7 is connected to an input of an a/D converter 10, an output of the a/D converter 9 is connected to an SPI1 of a DSP processing unit 11, an output of the a/D converter 10 is connected to the SPI2 of the DSP processing unit 11, the DSP processing unit 11 is connected to a human-computer interaction unit 14 through a control management module, a high MSB of an IO output of the DSP processing unit 11 is connected to an input of a relay driving chip 12 of a control relay of a first resistor array, a low LSB of the IO output of the DSP processing unit 11 is connected to a thyristor driving, the input of the switch power supply is connected with a live wire L and a zero line N, a first resistor array (comprising a relay) is connected between the live wire L and the zero line N, and a second resistor array (comprising a bidirectional thyristor) is connected between the live wire L and the zero line N.
The operation method of the circuit can realize the current and voltage detection of the load circuit through the DSP processing unit 11, and can adjust the resistance values of the first resistor array 1 and the second resistor array 2 through the DSP processing unit 11, and by matching with an appropriate detection method or an appropriate digital processing logic circuit, the quick detection of the charging pile 3 can be realized, the resistance load can be quickly adjusted to track the power change of a power grid, and the quick detection of the active power or the active power of the single-phase alternating-current charging pile 3 can be realized.
The load of the present application can be adapted to a proper detection method or a proper digital processing logic circuit, and also can adopt an ac charging pile detection method based on a dual-load array provided by the following embodiments. When the method for detecting the alternating current charging pile based on the double-load array is adapted, the method can be carried out by the DSP processing unit.
The above is a detailed description of an embodiment of the method for detecting a load by using an ac charging pile based on a dual-load array, and the following is a detailed description of an embodiment of the method for detecting an ac charging pile based on a dual-load array.
Referring to fig. 5 and fig. 6, an embodiment of a method for detecting an ac charging pile based on a dual-load array according to the present application is provided, where the method for detecting a load based on an ac charging pile based on a dual-load array according to the above embodiment includes:
101. acquiring a preset set output power value Pset;
the set output power value Pset can be sent to the DSP processing unit by an upper computer or a man-machine interaction unit;
102. calculating and outputting corresponding IO values of the first resistor array and the second resistor array according to the set output power value Pset and the voltage value U detected by the voltage sensor;
the voltage value U detected by the voltage sensor can be converted into a digital signal through the second A/D converter and then sent to the DSP processing unit; similarly, the current value I detected by the current sensor can be converted into a digital signal through the first A/D converter and sent to the DSP processing unit;
the corresponding IO values of the first resistor array and the second resistor array refer to control signals, such as MSB and LSB, of an IO output port on the DSP processing unit.
103. Calculating the current active power Pm according to the current value I detected by the current sensor and the voltage value U detected by the voltage sensor;
the current active power Pm may be obtained by direct multiplication, or an average power over a period of time may be obtained as the current active power Pm, please refer to the following further scheme;
104. calculating a difference value between a set output power value Pset and the current active power Pm, controlling the switching of the first resistor array and the second resistor array through an IO port, and increasing or decreasing the input resistance;
wherein, step 103 and step 104 are repeatedly executed at preset time intervals.
Fig. 6 is also used to illustrate an embodiment of a method for detecting an ac charging pile based on a dual load array according to the present application:
the first step,
The human-computer interaction unit 14 inputs the set output power value Pset.
Step two,
The DSP processing unit 11 calculates the resistive loads S0 and S4 to be applied according to the power value (Pset) and the voltage value U value collected by the DSP processing unit and an under load calculation method, and outputs IO values of S0 and S4.
Step three,
The DSP processing unit 11 calculates the current active power Pm every other half cycle according to the power (Pset) and the voltage value U and the current I acquired by the DSP processing unit.
Step four,
The DSP processing unit 11 controls the switches of G4 and G24 and the switches of S0 and S4 through the IO port according to the difference value between the power (Pset) and the current active average power Pm, and increases or decreases the power load array step five,
When the load does not receive an exit command sent by the human-computer interaction unit 14, the third step and the fourth step are repeated every half cycle (about 10ms), so that the active power is ensured to be in a constant state.
Further, step 102 specifically includes:
calculating the actual set current according to the current actual voltage as follows: iset is Pset/U;
calculating the IO value of the first resistor array as: MSB ═ floor ((Iset-0.5 × I1b)/I1 b);
calculating the IO value of the second resistor array as follows: LSB round (Iyu/I2b), Iyu Iset-MSB × I1 b;
the MSB is an output value of the IO port corresponding to the DSP processing unit and the first resistor array, floor () is rounded down, I1b is a minimum current provided by the first resistor array, LSB is an output value of the IO port corresponding to the DSP processing unit and the second resistor array, round () is rounded up, I2b is a minimum current provided by the second resistor array, and Iyu is a remainder current value.
The principle is as follows: the load is divided into a high-power load controlled by a low-speed switch and a low-power load controlled by a high-speed bidirectional thyristor, an under-load pre-input mode is used for the high-power load, the low-power load part controlled by the subsequent load high-speed bidirectional thyristor is ensured, in order to ensure the continuity of the load, an R5' is added in a low-power load array and is the same as the resistance value of R5 of the high-power load array, and thus the continuity of the low-power load array can be ensured at any boundary of the input of the high-power load.
The under-load pre-investment mode is sampled by the following calculation formula:
calculating the actual set current according to the current actual voltage:
Iset＝Pset/U；
and/U is the current actually measured voltage, and Pset is the power value set by the human-computer interaction interface. The values of the switches S0-S4 (high-order to low-order) are MSBs.
The current I1b ═ U/24R can be provided at minimum due to a high-power load array
MSB ═ floor ((Iset-0.5 × I1b)/I1 b);
load current of load R5 (U/24R)// I1b
// floor (for rounding down) R is the resistance of the small resistor array 101R1
The purpose of-0.5 xi 1b is to ensure that the remaining load current portion is supplied in any case by the low power load increase input, while adding an R5' to the small resistor array, ensuring that in the case of MSB calculation minus the load current of-0.5 xi 1b, the small resistor array has enough resistive load current to ensure the adjustment of the remainder portion, whose LSB resolution is 220, to fully meet the design requirement of 0.05%.
The remainder part LSB is calculated as follows (for the G4 to G24 switches, G4 high, G24 low):
iyu Iset-MSB I1b// Iyu is remainder partial current value
I2b＝U/224×R；
LSB round (Iyu/I2b)// round (round to round)
U/(224 × R)/I2 b is the minimum current that can be provided by a small power.
Further, step 104 includes:
calculating a difference value between the set output power value Pset and the current active power Pm: perr ═ (Pset-Pm);
the error in power translates into an error in resistance: rerr ═ 220 × 220)/Perr;
calculating the total resistance of the resistor array input in the calculation: r (n) ═ R (n-1) + K × Rerr;
wherein, R (n) is the total resistance of the resistor array which is added in the current calculation, R (n-1) is the total resistance of the resistor array which is added in the last calculation, K is-1, and n is the number of the sampling point.
The principle is shown in fig. 7, the difference value Perr of Pset and Pm is compared by each half cycle, and the double-resistance load array (the first resistance array and the second resistance array) is controlled by a proportional-integral algorithm to achieve the purpose of automatic constant power control.
Perr＝(Pset-Pm)；
The error in power is converted to an error in resistance calculated from the line voltage 220V (220V does not require very accurate amplification of the error).
Rerr＝(220×220)/Perr；
Therefore, the proportional integral of resistance is calculated as R (n) ═ R (n-1) + K × Rerr; where/n is that the current point K takes-1, i.e., K ═ 1; the power and resistance changes are inversely proportional.
v/R (n) the total resistance of the resistor array is calculated;
the last time/R (n-1) the total resistance of the resistor array was calculated.
Further, step 103 may be to directly multiply to obtain the current active power Pm, or to obtain an average power over a period of time as the current active power Pm. The step of obtaining the average power over a period of time as the current active power Pm includes:
calculating the numerical value N: n ═ round (fs/Freq);
calculate the average power of 2 cycles before sample point n:
taking the average power Pm (n) of 2 periods before the sampling point n as the current active power Pm calculated in the step S3;
wherein fs is the sampling rate of AD, Freq is the frequency of charging pile voltage, uiAnd iiThe voltage and current corresponding to the sampling point in the two cycles before the nth point.
The principle is that the method for obtaining the current average power uses an innovative averaging method, namely, the dot product of voltage and current and the average power are obtained, and the double average and frequency self-adjusting period averaging method is used
The calculation method is N ═ round (fs ×/Freq); // fs: the sampling rate fs of AD is 5000Hz Freq, and the frequency of the voltage of the charging pile is
When sampling point n points in AD (n)// Pm (n), average power of 2 periods is deduced previously
And/ui and ii are the sampling points of the voltage and current in two cycles before the nth point.
// N: for the sampling rate fs and the current voltage frequency rounded to integers
Remarking:
the algorithm needs to push 2 cycles forward from the current sampling point
The algorithm can ensure that stable active power accuracy is obtained when the power grid frequency fluctuates between 45Hz and 55Hz
Its accuracy is about 1/Nx 1/N-1/N2,
If the grid frequency is 50 Hz; accuracy of 1/(100) is 5000/50 ═ 100 ═ N ═ 100-2＝0.01％
If the grid frequency is 55 Hz; accuracy is 1/(91) when N is 5000/55 and 912＝0.012％
If the grid frequency is 45 Hz; the accuracy is 1/(111) when N is 5000/55 and 1112＝0.008％
The principle of the algorithm is explained as follows
First, the active power of 2 cycles is averaged, and since the power P is Um × Im × cos (Φ) + Um × Im × cos (2 × w × t- Φ),
the load in the present invention is a pure resistor so
Pt is a significant value of Um × Im + Um × Im × cos (2 × w × t) Um and Im.
It can be seen that the active power can be obtained by averaging Pt according to the period, when the frequency and sampling rate are not divided, the maximum difference of the remainder part is 1 point, the invention adopts the rounding method to obtain the average sampling point N of the periodic function, all the maximum difference is half point, the power sampling points are averaged according to the period of N once, the power measuring accuracy of 1/N can be obtained, the invention is characterized in that the N sampling points are averaged to the former N points of the N sampling points, a new data sequence only Pt ═ Um × Im + Um × Im × cos (2 × w × t)/N is obtained,
and averaging the new data sequence again, the active power measurement accuracy (indicated average active power) can be increased again by a factor of 1/N.
The MSB is the control IO of { S0, S1.. S4} in the order from high to low;
control IO with LSB { G4, G5.. G25} in high order to low order;
the A/D is an A/D conversion chip and an additional circuit thereof, and AD7767 is used in the patent;
DSP, digital signal processor, BF609 is used in the patent;
r is the minimum resistance value of the load array, and the invention can be 10 ohms;
round: rounding off as round (3.51) ═ 4;
floor: rounding down as floor (3.9999) ═ 3.
The above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.
Claims (10)
1. The utility model provides an alternating current charging stake detects load based on two load arrays which characterized in that includes: the device comprises a first resistor array, a second resistor array, a current transformer, a voltage transformer, a first A/D converter, a second A/D converter, a DSP processing unit, a relay driving chip and a silicon controlled rectifier driving circuit;
the resistors of the first resistor array are connected in series with a relay and are controlled by the relay to be switched; the resistors of the second resistor array are connected in series with a bidirectional thyristor and are controlled to be switched by the bidirectional thyristor; the resistance value of the first resistor array is smaller than that of the second resistor array;
the first resistor array and the second resistor array are connected in parallel and then connected to an alternating current charging pile to be detected to form a load circuit;
the DSP processing unit is connected with the load circuit through the first A/D converter and the current transformer and is used for detecting the current of the load circuit;
the DSP processing unit is connected with the load circuit through the second A/D converter and the voltage transformer and is used for detecting the voltage of the load circuit;
the DSP processing unit is connected with the relay through the relay driving chip and is used for controlling the first resistor array to be switched into the resistor of the load circuit;
the DSP processing unit is connected with the bidirectional controllable silicon through the controllable silicon driving circuit and used for controlling the resistance of the second resistance array to be input into the load circuit.
2. The AC charging pile detection load based on the double-load array as recited in claim 1, wherein an IV feedback resistor and a first operational amplifier are further connected between the first A/D converter and the current transformer.
3. The AC charging pile load detection system based on the dual-load array as claimed in claim 1, wherein a second operational amplifier is further connected between the second A/D converter and the voltage transformer.
4. The AC charging pile detecting load based on the double-load array as recited in claim 1, further comprising a human-computer interaction unit, wherein the human-computer interaction unit is connected with the DSP processing unit and is used for inputting a control signal to the DSP processing unit.
5. The AC charging pile detection load based on the double-load array as recited in claim 1, wherein the resistance values of the first resistance array and the second resistance array sequentially increase exponentially with a preset value.
6. The AC charging pile detection load based on the double-load array as recited in claim 5, wherein the resistance of the resistor with the largest resistance in the first resistor array is the same as the resistance of the resistor with the smallest resistance in the second resistor array.
7. A method for detecting an ac charging pile based on a dual-load array, based on the method for detecting a load of an ac charging pile based on a dual-load array as claimed in any one of claims 1 to 6, comprising:
s1, acquiring a preset set output power value Pset;
s2, calculating and outputting corresponding IO values of the first resistor array and the second resistor array according to the set output power value Pset and the voltage value U detected by the voltage sensor;
s3, calculating the current active power Pm according to the current value I detected by the current sensor and the voltage value U detected by the voltage sensor;
s4, calculating a difference value between the set output power value Pset and the current active power Pm, controlling the switching of the first resistor array and the second resistor array through the IO port, and increasing or decreasing the input resistance;
wherein, the steps S3 and S4 are repeatedly performed at preset time intervals.
8. The method according to claim 7, wherein the step S2 specifically includes:
calculating the actual set current according to the current actual voltage as follows: iset is Pset/U;
calculating the IO value of the first resistor array as: MSB ═ floor ((Iset-0.5 × I1b)/I1 b);
calculating the IO value of the second resistor array as follows: LSB round (Iyu/I2b), Iyu Iset-MSB × I1 b;
the MSB is an output value of the IO port corresponding to the DSP processing unit and the first resistor array, floor () is rounded down, I1b is a minimum current provided by the first resistor array, LSB is an output value of the IO port corresponding to the DSP processing unit and the second resistor array, round () is rounded up, I2b is a minimum current provided by the second resistor array, and Iyu is a remainder current value.
9. The method for detecting the ac charging post based on the dual load array as claimed in claim 7, wherein the step S4 includes:
calculating a difference value between the set output power value Pset and the current active power Pm: perr ═ (Pset-Pm);
the error in power translates into an error in resistance: rerr ═ 220 × 220)/Perr;
calculating the total resistance of the resistor array input in the calculation: r (n) ═ R (n-1) + K × Rerr;
wherein, R (n) is the total resistance of the resistor array which is added in the current calculation, R (n-1) is the total resistance of the resistor array which is added in the last calculation, K is-1, and n is the number of the sampling point.
10. The method for detecting the ac charging post based on the dual load array as claimed in claim 7, wherein the step S3 includes:
calculating the numerical value N: n ═ round (fs/Freq);
calculate the average power of 2 cycles before sample point n:
taking the average power Pm (n) of 2 periods before the sampling point n as the current active power Pm calculated in the step S3;
wherein fs is the sampling rate of AD, Freq is the frequency of charging pile voltage, uiAnd iiThe voltage and current corresponding to the sampling point in the two cycles before the nth point.
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| CN110221646A (en) * | 2019-07-08 | 2019-09-10 | 上海文顺电器有限公司 | A kind of output power and the constant method and device of electric current of holding load |
| CN110865253A (en) * | 2019-11-14 | 2020-03-06 | 许继电源有限公司 | Fill electric pile test load device |
| CN110989752B (en) * | 2019-11-21 | 2022-05-13 | 思瑞浦微电子科技（苏州）股份有限公司 | Resistance absolute value calibration circuit applied to floating high voltage |
| CN112285476A (en) * | 2020-11-14 | 2021-01-29 | 国网江苏省电力有限公司营销服务中心 | A kind of short circuit protection test circuit and method of AC charging pile based on quantitative analysis |
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