CN109637971B - Semiconductor device with improved performance - Google Patents
Semiconductor device with improved performance Download PDFInfo
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- CN109637971B CN109637971B CN201811495425.9A CN201811495425A CN109637971B CN 109637971 B CN109637971 B CN 109637971B CN 201811495425 A CN201811495425 A CN 201811495425A CN 109637971 B CN109637971 B CN 109637971B
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- silicon substrate
- well region
- dielectric layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 46
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 46
- 239000010703 silicon Substances 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 230000004888 barrier function Effects 0.000 claims abstract description 26
- 150000004767 nitrides Chemical class 0.000 claims abstract description 14
- 238000009489 vacuum treatment Methods 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 230000000994 depressogenic effect Effects 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- WGLPBDUCMAPZCE-UHFFFAOYSA-N Trioxochromium Chemical compound O=[Cr](=O)=O WGLPBDUCMAPZCE-UHFFFAOYSA-N 0.000 claims description 5
- 229910000423 chromium oxide Inorganic materials 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical group Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 abstract description 6
- 239000000969 carrier Substances 0.000 abstract description 5
- 230000003647 oxidation Effects 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000011900 installation process Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005381 potential energy Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Element Separation (AREA)
Abstract
The invention relates to the technical field of semiconductor devices, in particular to a semiconductor device with improved performance, which comprises a silicon substrate, wherein the silicon substrate is provided with a first surface and a second surface, a dielectric layer, a first oxidation layer, a silicon top layer and a first mask layer are sequentially arranged on the first surface, a second oxidation layer, a barrier layer and a second mask layer are sequentially arranged on the second surface, a well region penetrating through the dielectric layer is arranged on the dielectric layer, nitride is filled in the well region, a sunken region penetrating through the barrier layer is arranged on the barrier layer, and vacuum treatment is carried out inside the sunken region. The well region is arranged on the dielectric layer and filled with the nitride, so that the dielectric layer reduces the influence on the forming process of the semiconductor device, and meanwhile, the well region is arranged to avoid the influence of inherent junction capacitance formed between the silicon substrate and the silicon top layer on current carriers in the silicon substrate, so that the efficiency of signals passing through the semiconductor device is improved, and the distortion rate of the signals is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a semiconductor device with improved performance.
Background
The volume requirement for semiconductor components is higher and higher nowadays, the semiconductor with large volume occupies a large installation space in the installation process, the development of the chip towards the characteristics of lightness, smallness and the like is not facilitated, meanwhile, the anti-interference capacity of the chip to signals is also to be improved, because the silicon substrate of the SOI silicon chip is isolated from the top silicon by the buried oxide layer, inherent junction capacitance can exist between the silicon substrate and the top silicon, and under some conditions, passing radio-frequency signals can interfere with current carriers of the silicon substrate in the semiconductor device, so that the junction capacitance between the silicon substrate and a region above the silicon substrate where the device is formed can generate irregular and nonlinear changes along with the radio-frequency signals, and further the waveform distortion of the signals passing through the semiconductor device is caused.
Disclosure of Invention
It is an object of the present invention to overcome the problems of the prior art and to provide a semiconductor device with improved performance which can achieve a reduction in cost and a reduction in distortion rate.
In order to achieve the technical purpose and achieve the technical effect, the invention is realized by the following technical scheme:
the utility model provides a semiconductor device with improve performance, includes a silicon substrate, the silicon substrate has first surface, second surface, is equipped with dielectric layer, first oxide layer, silicon top layer, first mask layer on its first surface in proper order, is equipped with second oxide layer, barrier layer, second mask layer on its second surface in proper order, be equipped with the well region that runs through it on the dielectric layer, and the well region only runs through the dielectric layer, well region intussuseption is filled with the nitride, be equipped with the depressed area that runs through it on the barrier layer, and the depressed area only runs through the barrier layer, vacuum treatment carries out in the depressed area.
Further, the nitride is aluminum nitride.
Further, the first oxide layer and the second oxide layer are made of any one of silicon dioxide and chromium oxide.
Further, the number of the concave regions is 8-10.
Further, the manufacturing method comprises the following steps:
s1, providing a silicon substrate;
s2, forming a dielectric layer on the first surface of the silicon substrate through dry etching;
s3, etching a well region on the dielectric layer;
s4, filling nitride in the well region;
s5, forming a first oxide layer on the dielectric layer;
s6, forming a silicon top layer on the first oxide layer;
s7, depositing a first mask layer on the top silicon layer;
s8, sequentially forming a second oxide layer and a barrier layer on the second surface of the silicon substrate;
s9, etching a concave area on the barrier layer;
and S10, depositing a second mask layer on the barrier layer.
The invention has the beneficial effects that: the well region is arranged on the dielectric layer and filled with nitride, so that the dielectric layer reduces the influence on the forming process of the semiconductor device, the well region is arranged to avoid the influence of inherent junction capacitance formed between the silicon substrate and the silicon top layer on current carriers in the silicon substrate, further improve the efficiency of signals passing through the semiconductor device and reduce the distortion rate of the signals, the concave region is arranged and the interior of the concave region is subjected to vacuum treatment, so that when the semiconductor device is in a working state, the speed of the current carriers on the semiconductor device is increased when the current carriers pass through the concave region, thereby improving the signal transmission efficiency of the semiconductor device, simultaneously reducing the signal distortion rate, arranging the barrier layer to increase the potential energy of electrons in the semiconductor device, further ensuring the transmission efficiency, in the manufacturing method, the dielectric layer is etched by the dry method, and the directionality is stronger, so that the interatomic bonding structure after the dielectric layer is etched is not easy to damage, therefore, the influence on the transmission process of the current carrier is reduced, and the distortion rate is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural view of a semiconductor device with improved performance in embodiment 1 of the present invention;
fig. 2 is a schematic structural view of a semiconductor device with improved performance in embodiment 2 of the present invention;
FIG. 3 is a flow chart illustrating a method of fabricating a semiconductor device with improved performance in accordance with the present invention;
in the drawings, the reference numerals denote the following components:
the method comprises the following steps of 1-a silicon substrate, 2-a dielectric layer, 3-a well region, 4-a first oxide layer, 5-a silicon top layer, 6-a first mask layer, 7-a second oxide layer, 8-a barrier layer, 9-a sunken region, 10-a second mask layer and 11-a partial pressure groove.
Detailed Description
In order to make the technical means, the creation characteristics, the achievement purposes and the effects of the invention easy to understand, the technical solutions in the embodiments of the invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the invention, not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
A semiconductor device with improved performance as shown in fig. 1 comprises a silicon substrate 1, wherein the silicon substrate 1 has a first surface and a second surface, the first surface is sequentially provided with a dielectric layer 2, a first oxide layer 4, a silicon top layer 5 and a first mask layer 6, the second surface is sequentially provided with a second oxide layer 7, a barrier layer 8 and a second mask layer 10, the dielectric layer 2 is provided with a well region 3 penetrating through the dielectric layer, the well region 3 only penetrates through the dielectric layer 2, the well region 3 is filled with nitride, the barrier layer 8 is provided with a recessed region 9 penetrating through the barrier layer 8, the recessed region 9 is internally subjected to vacuum treatment, and the interior of the recessed region 9 is subjected to vacuum treatment.
The nitride is aluminum nitride.
The first oxide layer 4 and the second oxide layer 7 are made of any one of silicon dioxide and chromium oxide, and silicon dioxide is used in this embodiment.
The number of the concave regions 9 is 8-10.
As shown in fig. 3, the manufacturing method includes the following steps:
s1, providing a silicon substrate 1;
s2, forming the dielectric layer 2 on the first surface of the silicon substrate 1 by dry etching;
s3, etching the well region 3 on the dielectric layer 2;
s4, filling nitride in the well region 3;
s5, forming a first oxide layer 4 on the dielectric layer 2;
s6, forming a silicon top layer 5 on the first oxidation layer 4;
s7, depositing a first mask layer 6 on the top silicon layer 5;
s8, sequentially forming a second oxide layer 7 and a barrier layer 8 on the second surface of the silicon substrate 1;
s9, etching a concave region 9 on the barrier layer 8;
s10, a second mask layer 10 is deposited on the barrier layer 8.
Example 2
A semiconductor device with improved performance as shown in fig. 2 comprises a silicon substrate 1, wherein the silicon substrate 1 has a first surface and a second surface, the first surface is sequentially provided with a dielectric layer 2, a first oxide layer 4, a silicon top layer 5 and a first mask layer 6, the second surface is sequentially provided with a second oxide layer 7, a barrier layer 8 and a second mask layer 10, the dielectric layer 2 is provided with a well region 3 penetrating through the dielectric layer, the well region 3 is filled with nitride, the barrier layer 8 is provided with a recessed region 9 penetrating through the barrier layer, and the recessed region 9 is subjected to vacuum treatment.
The nitride is aluminum nitride.
The first oxide layer 4 and the second oxide layer 7 are made of any one of silicon dioxide and chromium oxide, and in this embodiment, chromium oxide is used.
The number of the concave regions 9 is 8-10.
And voltage division grooves 11 are arranged on two sides of the well region 3, so that the dielectric layer 2 can perform voltage division when a semiconductor device bears pressure.
The manufacturing method was the same as in example 1.
The preferred embodiments of the invention disclosed above are intended to be illustrative only. The preferred embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention. The invention is limited only by the claims and their full scope and equivalents.
Claims (5)
1. The utility model provides a semiconductor device with improve performance, its characterized in that includes a silicon substrate (1), silicon substrate (1) has first surface, second surface, is equipped with dielectric layer (2), first oxide layer (4), silicon top layer (5), first mask layer (6) on its first surface in proper order, is equipped with second oxide layer (7), barrier layer (8), second mask layer (10) on its second surface in proper order, be equipped with well region (3) that runs through it on dielectric layer (2), and well region (3) only runs through dielectric layer (2), well region (3) intussuseption is filled with the nitride, be equipped with on barrier layer (8) and run through its depressed area (9), and depressed area (9) only run through barrier layer (8), vacuum treatment is carried out in depressed area (9) inside.
2. A semiconductor device with improved performance according to claim 1, characterized in that the nitride is aluminum nitride.
3. A semiconductor device with improved performance according to claim 1, characterized in that the first oxide layer (4) and the second oxide layer (7) are made of any one of silicon dioxide and chromium oxide.
4. A semiconductor device with improved performance according to claim 1, characterized in that the number of recessed regions (9) is 8-10.
5. A semiconductor device with improved performance according to claim 1, characterized in that its fabrication method comprises the following steps:
s1, providing a silicon substrate (1);
s2, forming a dielectric layer (2) on the first surface of the silicon substrate (1) through dry etching;
s3, etching the well region (3) on the dielectric layer (2);
s4, filling nitride in the well region (3);
s5, forming a first oxide layer (4) on the dielectric layer (2);
s6, forming a silicon top layer (5) on the first oxide layer (4);
s7, depositing a first mask layer (6) on the top silicon layer (5);
s8, forming a second oxide layer (7) and a barrier layer (8) on the second surface of the silicon substrate (1) in sequence;
s9, etching a concave area (9) on the barrier layer (8);
s10, depositing a second mask layer (10) on the barrier layer (8).
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811495425.9A CN109637971B (en) | 2018-12-07 | 2018-12-07 | Semiconductor device with improved performance |
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| CN201811495425.9A CN109637971B (en) | 2018-12-07 | 2018-12-07 | Semiconductor device with improved performance |
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| CN109637971B true CN109637971B (en) | 2021-08-10 |
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| JP4540146B2 (en) * | 1998-12-24 | 2010-09-08 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
| CN103022054B (en) * | 2012-12-21 | 2016-12-28 | 上海华虹宏力半导体制造有限公司 | Silicon radio frequency device on insulator and silicon-on-insulator substrate |
| CN103824837B (en) * | 2014-03-10 | 2016-08-17 | 上海华虹宏力半导体制造有限公司 | Semiconductor device structure and preparation method thereof |
| WO2016149113A1 (en) * | 2015-03-17 | 2016-09-22 | Sunedison Semiconductor Limited | Thermally stable charge trapping layer for use in manufacture of semiconductor-on-insulator structures |
| CN105633002A (en) * | 2015-12-29 | 2016-06-01 | 中国科学院上海微系统与信息技术研究所 | Graphic silicon-on-insulator material and preparation method thereof |
| CN107170750B (en) * | 2017-05-08 | 2019-08-02 | 合肥市华达半导体有限公司 | A kind of semiconductor components and devices structure and preparation method thereof |
| US10276371B2 (en) * | 2017-05-19 | 2019-04-30 | Psemi Corporation | Managed substrate effects for stabilized SOI FETs |
| CN108682656B (en) * | 2018-05-30 | 2024-10-25 | 深圳市科创数字显示技术有限公司 | Composite silicon substrate, preparation method thereof, chip and electronic device |
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Address after: 230000, No. 66 Tiantangzhai Road, High tech Zone, Hefei City, Anhui Province Patentee after: Hefei Huayu Semiconductor Co.,Ltd. Country or region after: China Address before: 230000 Room 301 and 302, building 4, phase I, mechanical and Electrical Industrial Park, No. 767, Yulan Avenue, high tech Zone, Hefei City, Anhui Province Patentee before: Hefei Huayu Semiconductor Co.,Ltd. Country or region before: China |
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