CN109660263B - An LDPC code decoding method suitable for MLC NAND flash memory - Google Patents

Abstract

The invention discloses an LDPC code decoding method suitable for MLC NAND flash memory, comprising: (1) determining the type of the page to which the data to be decoded belongs, if it is a low page, then go to step (2); otherwise, go to step (2) Step (3); (2) carry out LDPC code decoding on the data to be decoded, and save the decoding result; the decoding ends; (3) obtain the low page data after decoding in the same unit, according to the obtained low page data Determine the threshold voltage range of the storage unit with the data to be decoded; calculate the log-likelihood ratio according to the determined threshold voltage range; take the calculated log-likelihood ratio as the decoding input, and perform LDPC code decoding on the data to be decoded ; Decoding ends. The invention can improve the decoding success rate and reduce the number of decoding iterations, so as to achieve the purpose of reducing the decoding delay and improving the read performance of the flash memory.

Description

An LDPC code decoding method suitable for MLC NAND flash memory

technical field

The invention belongs to the technical field of computer storage error correction, and more particularly, relates to an LDPC code decoding method suitable for MLC NAND flash memory.

Background technique

NAND flash memory is a non-volatile storage medium. Based on its advantages of high storage density, low unit cost, and fast read and write speed, NAND flash memory has become the mainstream application in the storage field. However, with the shrinking of flash memory process size and the increase of storage density, the bit error rate of NAND flash memory is also increasing. Compared with traditional BCH codes, LDPC codes still have strong error correction ability under high noise. More and more widely used in NAND flash memory. However, LDPC codes will bring additional read and write delays in the process of data read and write, thereby reducing the performance of NAND flash memory.

In MLCNAND flash memory, a memory cell stores two bits of data, and these two bits belong to different data pages, namely high page and low page. According to the threshold voltage of the memory cell, the memory cell is divided into four states, and these four The states are encoded as corresponding data "11", "10", "00", and "01" on the left is the low page data and on the right is the high page data. The peripheral circuit needs to determine the data stored in the memory cell by means of a series of read reference voltages, and the data in the memory cell can be determined by comparing the storage threshold voltage with the read reference voltage. After the memory cells in the flash memory are disturbed by noise, the threshold voltage will change, and the threshold voltage distributions of two adjacent states will overlap, causing errors in the read data.

The threshold voltage model of MLCNAND flash memory after interference is shown in Figure 1. The voltage values VERF1, VREF2, and VREF3 represented by solid lines are the default read reference voltages, and the voltage values represented by dotted lines are variable read reference voltages. The existing LDPC code decoding method is shown in FIG. 2 , the threshold voltage range can be obtained by using the default three read reference voltages, and LDPC hard-decision decoding can be used after reading the data. If the threshold voltage distributions of adjacent states overlap, erroneous data will be read out. If the LDPC hard-decision decoding fails, the read reference voltage should be changed to obtain a more accurate threshold voltage range, and soft-decision decoding is used to obtain correct data. After the soft-decision decoding fails, the read reference voltage can be further changed, and the next round of soft-decision decoding can be performed until all the available read reference voltages are used, and the read reference voltage cannot be changed any more.

In the decoding process of the LDPC code, it is necessary to first determine the corresponding threshold voltage range according to the read data, and then calculate the Log-Likelihood Ratio (LLR) according to the determined threshold voltage range as the decoding input. The smaller the determined threshold voltage range, the more accurate the obtained decoding input, and the higher the decoding efficiency of the LDPC code. However, to obtain a smaller threshold voltage range, the read reference voltage needs to be changed many times, which leads to an increase in the read delay in the decoding process of the LDPC code.

SUMMARY OF THE INVENTION

In view of the defects and improvement requirements of the prior art, the present invention provides an LDPC code decoding method suitable for MLC NAND flash memory, the purpose of which is to reduce the decoding delay of the LDPC code in the MLC NAND flash memory, thereby improving the performance of the flash memory.

In order to achieve the above object, the present invention provides an LDPC code decoding method suitable for MLC NAND flash memory, comprising the following steps:

(1) determine the type of the page to which the data to be decoded belongs, if it is a low page, then go to step (2); otherwise, go to step (3);

(2) LDPC code decoding is performed on the data to be decoded, and the decoding result is saved; the decoding ends;

(3) Obtain the decoded lower page data in the same unit, and perform LDPC code decoding on the to-be-decoded data according to the lower page data; the decoding ends.

Although the two bits of data belonging to the same storage unit belong to different pages, the errors that occur after being interfered by noise have a certain correlation, and due to the characteristics of encoding, the original bit error rate of the low page is lower than that of the high page. Therefore, the decoding success rate of the low page is higher than that of the high page, and the decoding of the low page precedes the decoding of the high page in the decoding process. In the present invention, when decoding the high page data, the low page decoding information of the same unit is used to assist the decoding of the high page data, and the threshold voltage range can be narrowed according to the correlation between the high page data and the low page data, A more accurate decoding input is obtained, thereby improving the decoding success rate, reducing the number of decoding iterations, and achieving the purpose of reducing the decoding delay and improving the read performance of the flash memory.

Further, step (3) includes:

Determine the threshold voltage range of the memory cell according to the low page data and the data to be decoded;

Calculate the log-likelihood ratio based on the threshold voltage range;

Taking the log-likelihood ratio as the decoding input, the data to be decoded is decoded by LDPC code.

Further, if the low page data is "1" and is not flipped before and after decoding, and the data to be decoded is "1", the threshold voltage range is (-∞, VREF1], and the log-likelihood ratio is:

If the low page data is "1" and is not flipped before and after decoding, and the data to be decoded is "0", the threshold voltage range is (VREF1, VREF2], and the log-likelihood ratio is:

If the low page data is "0" and is not flipped before and after decoding, and the data to be decoded is "1", the threshold voltage range is (VREF3,∞], and the log-likelihood ratio is:

If the low page data is "0" and is not flipped before and after decoding, and the data to be decoded is "0", the threshold voltage range is (VREF2, VREF3], and the log-likelihood ratio is:

If the low page data is flipped before and after decoding, the log-likelihood ratio is:

LLR(MSB)=LLRMAX;

Among them, ER, P1, P2 and P3 are the corresponding memory cell states when the memory cells store data "11", "10", "00" and "01" respectively, VREF1, VREF2 and VREF3 are the default read reference voltages, and VREF1<VREF2<VREF3, p ^(S) (x) represents the probability that the memory cell state is S before the data to be decoded is in error when the threshold voltage is x, S∈{ER,P1,P2,P3}, LLRMAX means greater than 50 constant.

For the high page data in the memory cell, if the read data is 1, the threshold voltage range can be determined to be (-∞, VREF1]∪(VREF3,+∞], and if the read data is 0, the threshold voltage range can be determined to be ( VREF1, VREF3], the threshold voltage range determined only according to the high page data is large; according to the value of the low page data in the same cell, the threshold voltage range can be further determined as (-∞, VREF1], (VREF1, VREF2], (VREF2 , VREF3] and (VREF3, +∞) in a certain range, thus narrowing the threshold voltage range, you can get more accurate decoding input.

For a codeword, if a bit is flipped before and after decoding, it indicates that the threshold voltage state of the memory cell where this bit is located has shifted, resulting in an error in reading data. Since the threshold voltage state is shifted to adjacent states, and the coding of the adjacent states of the threshold voltage is a Gray code that differs by only one bit, if the threshold voltage state is shifted to the adjacent state, a certain bit of the memory cell will be flipped , the other data of the same unit is unchanged. Since the low page data error occurs in the overlapping area of P1 and P2, if the memory cell low page data is inverted before and after decoding, it indicates that the low page data is read incorrectly, and the threshold voltage is in the P1 or P2 state. The high page data of the P1 and P2 states are both 0, so the high page data of the same unit has a high probability of being 0, and the LLR can be set to a large value LLRMAX.

In general, through the above technical solutions conceived in the present invention, compared with the prior art, when decoding the high page data, the threshold voltage of the memory cell is determined in combination with the decoded low page data in the same unit. Therefore, the determined threshold voltage range can be effectively narrowed and a more accurate decoding input can be provided, thereby improving the decoding success rate, reducing the number of decoding iterations, reducing the decoding delay and improving the flash memory read performance.

Description of drawings

FIG. 1 is a schematic diagram of a memory cell threshold voltage distribution of an existing MLC NAND flash memory;

2 is a schematic diagram of an existing LDPC code decoding method;

3 is a flowchart of a method for decoding an LDPC code used in an MLC NAND flash memory provided by an embodiment of the present invention;

4 is a schematic diagram of a decoding input calculation area provided by an embodiment of the present invention;

FIG. 5 is a test result of performing a decoding test using the traditional decoding method and the decoding method provided by the present invention.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

Before introducing the technical solutions of the present invention in detail, a brief description of the calculation of the log-likelihood ratio (LLR) as the decoding input is made. The log-likelihood ratio is the ratio of the probability that the corresponding data is 0 to the probability that the corresponding data is 1, and then the logarithm is taken. Assuming that the threshold voltage range of the memory cell is in (VREF1, V 1, ₂ ], then the pair of low page data The calculation formulas of the log-likelihood ratio LLR (LSB) and the log-likelihood ratio LLR (MSB) of the high page data are:

The calculation of the LLR is based on the threshold voltage range of the memory cell. The smaller the read threshold voltage range, the more accurate the obtained decoding input information LLR, and the higher the decoding efficiency of the LDPC code. However, to obtain a smaller threshold voltage range, the read reference voltage needs to be changed many times, which leads to an increase in the read delay in the decoding process of the LDPC code.

The present invention provides an LDPC code decoding method suitable for MLC NAND flash memory. The characteristic of the original bit error rate of the high page data is that when decoding the high page data, the threshold voltage range of the memory cell is determined in combination with the low page data in the same memory cell to narrow the threshold voltage range and provide more accurate decoding. code input, thereby improving the decoding success rate, reducing the number of decoding iterations, reducing the decoding delay and improving the flash memory read performance.

The LDPC code decoding method suitable for MLC NAND flash memory provided by the present invention, as shown in Figure 3, includes the following steps:

(1) determine the type of the page to which the data to be decoded belongs, if it is a low page, then go to step (2); otherwise, go to step (3);

(2) LDPC code decoding is performed on the data to be decoded, and the decoding result is saved; the decoding ends;

(3) obtain the low page data after decoding in the same unit, and carry out LDPC code decoding to the data to be decoded according to the low page data; the decoding ends;

In an optional embodiment, step (3) specifically includes:

Determine the threshold voltage range of the memory cell according to the low page data and the data to be decoded;

Calculate the log-likelihood ratio based on the threshold voltage range;

Taking the log-likelihood ratio as the decoding input, the data to be decoded is decoded by LDPC code;

According to the specific values of the high page data (that is, the data to be decoded) and the low page data, the method for determining the threshold voltage range and calculating the log-likelihood ratio is:

If the low page data is "1" and is not flipped before and after decoding, and the data to be decoded is "1", the threshold voltage range is (-∞, VREF1], and the log-likelihood ratio is:

If the low page data is "1" and is not flipped before and after decoding, and the data to be decoded is "0", the threshold voltage range is (VREF1, VREF2], and the log-likelihood ratio is:

If the low page data is "0" and is not flipped before and after decoding, and the data to be decoded is "1", the threshold voltage range is (VREF3,∞], and the log-likelihood ratio is:

If the low page data is "0" and is not flipped before and after decoding, and the data to be decoded is "0", the threshold voltage range is (VREF2, VREF3], and the log-likelihood ratio is:

If the low page data is flipped before and after decoding, the log-likelihood ratio is:

LLR(MSB)=LLRMAX;

Among them, ER, P1, P2 and P3 are the corresponding memory cell states when the memory cells store data "11", "10", "00" and "01" respectively, VREF1, VREF2 and VREF3 are the default read reference voltages, and VREF1<VREF2<VREF3, p ^(S) (x) represents the probability that the memory cell state is S before the data to be decoded is in error when the threshold voltage is x, S∈{ER,P1,P2,P3}, LLRMAX means greater than 50 constant.

As shown in Figure 4, for the high page data in the memory cell, if the read data is 1, the threshold voltage range can be determined to be (-∞, VREF1]∪(VREF3,+∞], if the read data is 0, it can be It is determined that the threshold voltage range is (VREF1, VREF3], and the threshold voltage range determined only according to the high page data is larger; according to the value of the low page data in the same cell, the threshold voltage range can be further determined to be (-∞, VREF1], (VREF1 , VREF2], (VREF2, VREF3] and (VREF3, +∞) in a certain range, thus narrowing the threshold voltage range, can get more accurate decoding input;

For a codeword, if a bit flips before and after decoding, it indicates that the threshold voltage state of the memory cell where this bit is located has shifted, resulting in an error in reading data; because the threshold voltage state shifts more Offset to the adjacent state, and the coding of the adjacent state of the threshold voltage is a Gray code that differs by only one bit, so if the threshold voltage state is shifted to the adjacent state and a bit of the memory cell is flipped, the other of the same cell will be reversed. Bit data is unchanged; since the low page data error occurs in the overlapping area of P1 and P2, if the memory cell low page data is flipped before and after decoding, it indicates that the low page data is read incorrectly, and the threshold voltage is in the P1 or P2 state; However, the high page data of P1 and P2 states are both 0, so the high page data of the same unit has a high probability of being 0, and LLR can be set to a large value LLRMAX. In the above embodiment, the value range of LLRMAX is greater than 50.

In the present invention, when decoding the high page data, the low page decoding information of the same unit is used to assist the decoding of the high page data, and the threshold voltage range can be narrowed according to the correlation between the high page data and the low page data, A more accurate decoding input is obtained, thereby improving the decoding success rate, reducing the number of decoding iterations, and achieving the purpose of reducing the decoding delay and improving the read performance of the flash memory.

Based on the flash memory error model and parameters in "Exploiting Memory Device Wear-Out Dynamics to Improve NAND FlashMemory System Performance", the traditional LDPC code decoding method (ie decoding without auxiliary information) and the MLC code provided by the present invention are respectively adopted. The LDPC code decoding method of NAND flash memory (that is, decoding with auxiliary information) is tested for decoding, and the code length of the LDPC code is set to 9216, the information length is 8192, the code rate is 88.9%, and the maximum number of decoding iterations is 50. The test sample erase and write cycle (PE) is 2000-5000 times, the number of programming disturbances is 0-3 times, the retention time is 1 month to 10 years, and the flash bit error rate is 10 ^-3 to 10 ^-2 level. The specific test samples are shown in Table 1. The decoding success rate of the test samples shown in Table 1 using two decoding methods and the high page error rate of the decoding method using auxiliary information are shown in Figure 5. Show.

Table 1 Test Example

Numbering PE CCI Interference Times keep time High page data error rate 1 2000 1 6 years 8.55E-03 2 5000 1 January 8.74E-03 3 2000 1 7 years 9.26E-03 4 2000 1 8 years 9.74E-03 5 3000 2 2 years 9.75E-03 6 3000 3 3 years 9.97E-03 7 2000 0 3 years 1.02E-02 8 3000 1 1 year 1.04E-02 9 2000 1 9 years 1.05E-02 10 2000 1 10 years 1.09E-02 11 4000 3 1 year 1.16E-02 12 2000 0 4 years 1.20E-02 13 3000 2 3 years 1.20E-02 14 3000 3 5 years 1.21E-02 15 3000 3 6 years 1.28E-02 16 2000 0 5 years 1.34E-02 17 3000 3 7 years 1.36E-02 18 4000 2 1 year 1.40E-02 19 5000 0 January 1.41E-02

According to the test results shown in FIG. 5 , compared with the traditional LDPC code decoding method, the LDPC code decoding method suitable for MLC NAND flash memory provided by the present invention improves the decoding success rate by up to 49%, and reduces the 40% of the decoding iteration times can effectively reduce the decoding delay.

Those skilled in the art can easily understand that the above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention, etc., All should be included within the protection scope of the present invention.

Claims (2)

1. An LDPC code decoding method suitable for MLC NAND flash memory is characterized by comprising the following steps:

(1) determining the type of the page to which the data to be decoded belongs, and if the type of the page is a low page, turning to the step (2); otherwise, turning to the step (3);

(2) decoding the data to be decoded by using the LDPC code, and storing a decoding result; ending the decoding;

(3) obtaining low-page data after decoding in the same unit, and performing LDPC code decoding on the data to be decoded according to the low-page data; ending the decoding;

the step (3) comprises the following steps:

if the low page data is turned over before and after decoding, calculating a log-likelihood ratio as follows: llr (msb) LLRMAX; otherwise, determining a threshold voltage range of a storage unit according to the low-page data and the data to be decoded, and calculating a log-likelihood ratio according to the threshold voltage range;

performing LDPC code decoding on the data to be decoded by taking the log-likelihood ratio as decoding input;

determining a threshold voltage range of a memory cell according to the low page data and the data to be decoded, comprising:

if the low page data is "1" and there is no inversion before and after decoding, and the data to be decoded is "1", the threshold voltage range is (— ∞, VREF1 ];

if the low page data is "1" and is not flipped before and after decoding, and the data to be decoded is "0", the threshold voltage range is (VREF1, VREF2 ];

if the lower page data is "0" and is not flipped before and after decoding, and the data to be decoded is "1", the threshold voltage range is (VREF3, ∞ ];

if the low page data is '0' and is not flipped before and after decoding, and the data to be decoded is '0', the threshold voltage range is (VREF2, VREF3 ];

where LLRMAX denotes a constant greater than 50, and the corresponding threshold voltages rise in sequence when the memory cells store data "11", "10", "00", and "01"; VREF1, VREF2 and VREF3 are all default read reference voltages, and VREF1 < VREF2 < VREF 3.

2. The LDPC code decoding method for MLC NAND flash memory according to claim 1,

when the threshold voltage range is (— ∞, VREF1], the log-likelihood ratio is:

when the threshold voltage range is (VREF1, VREF 2), the log-likelihood ratio is:

when the threshold voltage range is (VREF3, ∞), the log-likelihood ratio is:

when the threshold voltage range is (VREF2, VREF 3), the log-likelihood ratio is:

wherein, ER, P1, P2 and P3 are the corresponding memory cell states when the memory cell stores data "11", "10", "00" and "01", respectively, P^(S)(x) And the probability that the state of the memory cell is S before the error occurs to the data to be decoded when the threshold voltage is x is represented, and the S belongs to { ER, P1, P2 and P3 }.

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