CN109672516A - A kind of lotus control memristor chaos circuit - Google Patents
A kind of lotus control memristor chaos circuit Download PDFInfo
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- CN109672516A CN109672516A CN201710952209.1A CN201710952209A CN109672516A CN 109672516 A CN109672516 A CN 109672516A CN 201710952209 A CN201710952209 A CN 201710952209A CN 109672516 A CN109672516 A CN 109672516A
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Abstract
本发明公开了一种荷控忆阻器混沌电路，由放大器U1、放大器U2、放大器U3、放大器U4、放大器U5、放大器U6、电流反馈型放大器U7、电流反馈型放大器U8、乘法器U9、电流反馈型放大器U10、放大器U11、放大器U12、电容C1、电容C2、电容Cw1、电容Cw2、电容Cw3以及其外围电阻构成。本发明公开的一种荷控忆阻器混沌电路，忆阻器属于荷控型，具有独特的动力学行为，丰富了忆阻器混沌电路库。
The invention discloses a load-controlled memristor chaotic circuit, which consists of an amplifier U1, an amplifier U2, an amplifier U3, an amplifier U4, an amplifier U5, an amplifier U6, a current feedback amplifier U7, a current feedback amplifier U8, a multiplier U9, a current The feedback amplifier U10, the amplifier U11, the amplifier U12, the capacitor C1, the capacitor C2, the capacitor Cw1, the capacitor Cw2, the capacitor Cw3 and its peripheral resistances are formed. The invention discloses a load-controlled memristor chaotic circuit. The memristor belongs to the load-controlled type, has unique dynamic behavior, and enriches the memristor chaotic circuit library.
Description
Technical field
The invention patent relates to field of electronic circuitry, more particularly to a kind of lotus control memristor chaos circuit.
Background technique
Memristor chaos circuit has unique kinetic characteristics, is the hot spot of current chaos circuit research, at present memristor
The quantity of device chaos circuit is extremely limited, and enriching memristor chaos circuit library has very big realistic meaning.But for routine
Memristor chaos circuit, memristor one end need to be connected to the ground, the building of new memristor chaos circuit of this restrict.
Summary of the invention
To solve the problems in the background art, the invention proposes a kind of lotus control memristor chaos circuit, features
It is, the invention discloses a kind of lotus control memristor chaos circuits, by amplifier U1, amplifier U2, amplifier U3, amplifier
U4, amplifier U5, amplifier U6, current feedback amplifier U7, current feedback amplifier U8, multiplier U9, current feedback
Type amplifier U10, amplifier U11, amplifier U12, capacitor C1, capacitor C2, capacitor Cw1, capacitor Cw2, capacitor Cw3 and its outside
Enclose resistance composition；
Wherein, resistance Rw7 is connected to the non-inverting input terminal of amplifier U11 and the output end of amplifier U11；Resistance Rw6 is connected to
The inverting input terminal of amplifier U11 and the output end of amplifier U11；The inverting input terminal of amplifier U11 is connect by resistance Rw8
Ground；Resistance Rw2 mono- terminates the non-inverting input terminal of amplifier U11, other end ground connection；The same phase of the termination of capacitor Cw2 mono- amplifier U11
Input terminal, other end ground connection；
The non-inverting input terminal of the homophase input termination amplifier U1 of U11；The inverting input terminal of amplifier U1 is defeated with amplifier U1's
Outlet is connected；The output end of amplifier U1 is connected by resistance R1 with the non-inverting input terminal of amplifier U3；The same phase of amplifier U3
Input terminal is grounded by resistance R2；
The non-inverting input terminal of the homophase input termination amplifier U2 of U12；The inverting input terminal of amplifier U2 is defeated with amplifier U2's
Outlet is connected；The output end of amplifier U2 is connected by resistance R3 with the inverting input terminal of amplifier U3；The reverse phase of amplifier U3
Input terminal is connected with the output end of amplifier U3；
The output end of amplifier U3 is connected with the non-inverting input terminal of amplifier U4；Resistance R5 is connected to the anti-phase input of amplifier U4
Between end and the output end of amplifier U4；
The output end of amplifier U4 is connected by resistance R6 with the inverting input terminal of amplifier U5；The inverting input terminal of amplifier U4
It is connected by resistance R7 with the non-inverting input terminal of amplifier U5；Resistance R8 is connected to the non-inverting input terminal and amplifier of amplifier U5
Between the in-phase end of U1；Resistance R9 is connected between the inverting input terminal of amplifier U5 and the output end of amplifier U5；Resistance R10
It is connected between the output end of amplifier U5 and the in-phase end of amplifier U1；
The output end of amplifier U4 is connected by resistance R11 with the inverting input terminal of amplifier U6；The anti-phase input of amplifier U4
End is connected by resistance R12 with the non-inverting input terminal of amplifier U6；Resistance R13 is connected to the non-inverting input terminal of amplifier U6 and puts
Between the output end of big device U3；Resistance R14 be connected to amplifier U6 inverting input terminal and amplifier U2 non-inverting input terminal it
Between；Resistance R15 is connected between the output end of amplifier U6 and the in-phase end of amplifier U2；
The inverting input terminal of amplifier U4 is connected by resistance R16 with the inverting input terminal of current feedback amplifier U7；Electric current
The feedback C-terminal of feedback-type amplifier U7 is grounded by capacitor C1；The output of current feedback amplifier U7 terminates current feedback
The non-inverting input terminal of amplifier U8；The inverting input terminal of current feedback amplifier U8 is grounded by capacitor C2；Current feedback
The feedback C-terminal of amplifier U8 is grounded by resistance R17；
The non-inverting input terminal of current feedback amplifier U8 is connected with the port y of multiplier U9；Current feedback amplifier U8's
Output end is connected with the port x of multiplier U9；The port w of multiplier U9 and the non-inverting input terminal of current feedback amplifier U10
It is connected；The inverting input terminal of current feedback amplifier U10 is grounded by resistance R18；The feedback of current feedback amplifier U10
C-terminal is grounded by resistance R19；The homophase input of the output termination current feedback amplifier U7 of current feedback amplifier U10
End；
Resistance Rw7 connect with capacitor Cw3 series connection after be connected to the non-inverting input terminal of amplifier U12 and the output end of amplifier U12
Between；Resistance Rw4 is connected to the inverting input terminal of amplifier U12 and the output end of amplifier U12；The reverse phase of amplifier U12 is defeated
Enter end to be grounded by resistance Rw5；Resistance Rw1 mono- terminates the non-inverting input terminal of amplifier U12, other end ground connection；The one end capacitor Cw1
Connect the non-inverting input terminal of amplifier U12, other end ground connection.
The method have the benefit that: a kind of lotus control memristor chaos circuit disclosed by the invention, memristor belong to
Lotus control type gets rid of the constraint of one end ground connection, has unique dynamic behavior, enriches memristor chaos circuit library.
Detailed description of the invention
A kind of lotus control memristor chaos circuit figure of Fig. 1.
Fig. 2 VW1-VW2Phasor.
Specific embodiment
The specific embodiment of circuit of the present invention is described further with reference to the accompanying drawing.
As shown in Figure 1, a kind of lotus control memristor chaos circuit, which is characterized in that by amplifier U1, amplifier U2, amplification
Device U3, amplifier U4, amplifier U5, amplifier U6, current feedback amplifier U7, current feedback amplifier U8, multiplier
U9, current feedback amplifier U10, amplifier U11, amplifier U12, capacitor C1, capacitor C2, capacitor Cw1, capacitor Cw2, capacitor
Cw3 and its peripheral resistance are constituted；
Wherein, resistance Rw7 is connected to the non-inverting input terminal of amplifier U11 and the output end of amplifier U11；Resistance Rw6 is connected to
The inverting input terminal of amplifier U11 and the output end of amplifier U11；The inverting input terminal of amplifier U11 is connect by resistance Rw8
Ground；Resistance Rw2 mono- terminates the non-inverting input terminal of amplifier U11, other end ground connection；The same phase of the termination of capacitor Cw2 mono- amplifier U11
Input terminal, other end ground connection；
The non-inverting input terminal of the homophase input termination amplifier U1 of U11；The inverting input terminal of amplifier U1 is defeated with amplifier U1's
Outlet is connected；The output end of amplifier U1 is connected by resistance R1 with the non-inverting input terminal of amplifier U3；The same phase of amplifier U3
Input terminal is grounded by resistance R2；
The non-inverting input terminal of the homophase input termination amplifier U2 of U12；The inverting input terminal of amplifier U2 is defeated with amplifier U2's
Outlet is connected；The output end of amplifier U2 is connected by resistance R3 with the inverting input terminal of amplifier U3；The reverse phase of amplifier U3
Input terminal is connected with the output end of amplifier U3；
The output end of amplifier U3 is connected with the non-inverting input terminal of amplifier U4；Resistance R5 is connected to the anti-phase input of amplifier U4
Between end and the output end of amplifier U4；
The output end of amplifier U4 is connected by resistance R6 with the inverting input terminal of amplifier U5；The inverting input terminal of amplifier U4
It is connected by resistance R7 with the non-inverting input terminal of amplifier U5；Resistance R8 is connected to the non-inverting input terminal and amplifier of amplifier U5
Between the in-phase end of U1；Resistance R9 is connected between the inverting input terminal of amplifier U5 and the output end of amplifier U5；Resistance R10
It is connected between the output end of amplifier U5 and the in-phase end of amplifier U1；
The output end of amplifier U4 is connected by resistance R11 with the inverting input terminal of amplifier U6；The anti-phase input of amplifier U4
End is connected by resistance R12 with the non-inverting input terminal of amplifier U6；Resistance R13 is connected to the non-inverting input terminal of amplifier U6 and puts
Between the output end of big device U3；Resistance R14 be connected to amplifier U6 inverting input terminal and amplifier U2 non-inverting input terminal it
Between；Resistance R15 is connected between the output end of amplifier U6 and the in-phase end of amplifier U2；
The inverting input terminal of amplifier U4 is connected by resistance R16 with the inverting input terminal of current feedback amplifier U7；Electric current
The feedback C-terminal of feedback-type amplifier U7 is grounded by capacitor C1；The output of current feedback amplifier U7 terminates current feedback
The non-inverting input terminal of amplifier U8；The inverting input terminal of current feedback amplifier U8 is grounded by capacitor C2；Current feedback
The feedback C-terminal of amplifier U8 is grounded by resistance R17；
The non-inverting input terminal of current feedback amplifier U8 is connected with the port y of multiplier U9；Current feedback amplifier U8's
Output end is connected with the port x of multiplier U9；The port w of multiplier U9 and the non-inverting input terminal of current feedback amplifier U10
It is connected；The inverting input terminal of current feedback amplifier U10 is grounded by resistance R18；The feedback of current feedback amplifier U10
C-terminal is grounded by resistance R19；The homophase input of the output termination current feedback amplifier U7 of current feedback amplifier U10
End；
Resistance Rw7 connect with capacitor Cw3 series connection after be connected to the non-inverting input terminal of amplifier U12 and the output end of amplifier U12
Between；Resistance Rw4 is connected to the inverting input terminal of amplifier U12 and the output end of amplifier U12；The reverse phase of amplifier U12 is defeated
Enter end to be grounded by resistance Rw5；Resistance Rw1 mono- terminates the non-inverting input terminal of amplifier U12, other end ground connection；The one end capacitor Cw1
Connect the non-inverting input terminal of amplifier U12, other end ground connection.
The present embodiment, amplifier U1, amplifier U2, amplifier U3, amplifier U4, amplifier U5, amplifier U6, amplifier
That U11 and amplifier U12 is selected is amplifier LM324；
The present embodiment, current feedback amplifier U7, current feedback amplifier U8 and current feedback amplifier U10 select high
Fast single-chip operational amplifier AD844；
The present embodiment, multiplier U9 select four-quadrant multiplier AD633；
The present embodiment, capacitor C1=100nF, capacitor C2=10nF, Cw1=47nF, capacitor Cw2=10nF, capacitor CW3=10nF；
The present embodiment, peripheral circuit resistance R1=10k Ω, resistance R2=12k Ω, resistance R3=10k Ω, resistance R4=14k Ω, resistance
R5=6.8k Ω, resistance R6=10k Ω, resistance R7=100k Ω, resistance R8=100k Ω, resistance R9=10k Ω, resistance R10=100k
Ω, resistance R11=100k Ω, resistance R12=10k Ω, resistance R13=30k Ω, resistance R14=10k Ω, resistance R15=100k Ω, electricity
Resistance R16=18k Ω, resistance R17=3.3k Ω, resistance R18=22k Ω, resistance R19=5k Ω, resistance Rw1=100k Ω, resistance Rw2=
2k Ω, resistance Rw3=3.3k Ω, resistance Rw4=22k Ω, resistance Rw5=5k Ω, resistance Rw6=68k Ω, resistance Rw7=2k Ω, electricity
Hinder Rw8=33k Ω.
The present embodiment, Fig. 2 show VW1-VW2A kind of phasor, it can be seen that lotus control memristor chaos circuit tool of the present invention
There is unique dynamic behavior.
What has been described above is only a preferred embodiment of the present invention, and present invention is not limited to the above embodiments.It is appreciated that this
The other improvements and change that field technical staff directly exports or associates without departing from the spirit and concept in the present invention
Change, is considered as being included within protection scope of the present invention.
Claims (1)
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710952209.1A CN109672516A (en) | 2017-10-13 | 2017-10-13 | A kind of lotus control memristor chaos circuit |
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| CN201710952209.1A CN109672516A (en) | 2017-10-13 | 2017-10-13 | A kind of lotus control memristor chaos circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111079365A (en) * | 2019-12-12 | 2020-04-28 | 杭州电子科技大学 | Arc tangent trigonometric function memristor circuit model |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111079365A (en) * | 2019-12-12 | 2020-04-28 | 杭州电子科技大学 | Arc tangent trigonometric function memristor circuit model |
| CN111079365B (en) * | 2019-12-12 | 2023-11-10 | 杭州电子科技大学 | A simulator for arctangent trigonometric memristor |
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Application publication date: 20190423 |