CN109767986A - Semiconductor devices and its manufacturing method - Google Patents
Semiconductor devices and its manufacturing method Download PDFInfo
- Publication number
- CN109767986A CN109767986A CN201910069243.3A CN201910069243A CN109767986A CN 109767986 A CN109767986 A CN 109767986A CN 201910069243 A CN201910069243 A CN 201910069243A CN 109767986 A CN109767986 A CN 109767986A
- Authority
- CN
- China
- Prior art keywords
- electrode
- layer
- semiconductor layer
- separation layer
- field plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 170
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 63
- 238000000926 separation method Methods 0.000 claims abstract description 135
- 239000007772 electrode material Substances 0.000 claims abstract description 85
- 239000000463 material Substances 0.000 claims description 33
- 239000000758 substrate Substances 0.000 claims description 32
- 239000003989 dielectric material Substances 0.000 claims description 16
- 230000000717 retained effect Effects 0.000 claims description 15
- 238000002955 isolation Methods 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 17
- 229920005591 polysilicon Polymers 0.000 description 12
- 238000000034 method Methods 0.000 description 10
- 230000005669 field effect Effects 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 108090000723 Insulin-Like Growth Factor I Proteins 0.000 description 1
- 102000013275 Somatomedins Human genes 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Element Separation (AREA)
Abstract
The present invention provides a kind of semiconductor devices and its manufacturing methods, are related to technical field of semiconductors.By first removing a part of electrode material during making grid, make to form isolated groove between the electrode material and the first separation layer that retain in slot electrode, while the second separation layer can be made in isolated groove again.So, the sum of thickness of first separation layer and the second separation layer can be significantly greater than the thickness of the first oxide layer, so that the overall quality of the separation layer between first electrode and field plate is improved, it so that the limiting value of the grid source maximum voltage of semiconductor devices is higher, while can solve the IGSS/HTGB Problem of Failure of device, interelectrode robustness can be improved, improve the reliability of device, the production process of device is simple, and the thickness of separation layer is controllable, and cost of manufacture is lower.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and its manufacturing method.
Background technique
In certain application scenarios, certain performances of device can have some impact on actual use semiconductor devices.Example
Such as, for certain field effect transistors, need the limiting value of the grid source maximum voltage of device higher in certain application scenarios, but existing
In some field effect transistors, there are many factor of the performance of constraint device, so that certain devices can not adapt to application scenes.
For example, in existing device, if in grid oxic horizon growth period, isolating oxide layer is formed simultaneously.Although isolating oxide layer
It is more slightly thicker than gate oxide (oxidation rate of polysilicon is faster than monocrystalline silicon, the thickness of the first oxide layer probably 200A~
Between 900A, its thickness is limited by the threshold voltage designed), but the isolating oxide layer ratio being formed by polysilicon is by monocrystalline
The quality of gate oxide that silicon is formed is poor.In general, grid polycrystalline silicon is weak compared with the layer of isolation oxide between field plate polysilicon.
Device VGSSLimiting value be restricted, IGSS/ HTGB failure will cause many puzzlements.
It, as shown in Figure 1a, can if forming isolating oxide layer 36 using method described in United States Patent (USP) 7098500B2
Groove is filled to form oxide using high-density plasma chemical vapor deposition (HDPCVD), then is chemically-mechanicapolish polished into crossing
Technique, then carry out the technique that oxide time is carved and made.Although it is thick that isolating oxide layer 36 can be made comparison, technique is very
Complicated and cost of manufacture is very high, and the thickness of isolating oxide layer 36 is difficult to control in manufacturing process, and thickness depends on polysilicon
The terminating point of 38 remaining thickness and isolating oxide layer 36 etching itself.Meanwhile the manufacture craft is difficult to control grid polycrystalline silicon
The position of 34 bottoms, influence factor are similar to above.If the bottom of grid polycrystalline silicon 34 is than the bottom shallow of p-well 16, device
Part will be hardly turned on.If the bottom of grid polycrystalline silicon 34 is too deep, undesirable larger miller capacitance (Miller will be formed
Capacitance)。
Summary of the invention
In view of this, the present invention provides a kind of semiconductor devices and its manufacturing methods.
Technical solution provided by the invention is as follows:
A kind of manufacturing method of semiconductor devices, comprising:
There is provided a substrate, the substrate includes the first semiconductor layer and positioned at the second the half of first semiconductor layer side
Conductor layer, first semiconductor layer have the first conduction type, and second semiconductor layer has the second conduction type, described
First conduction type and the second conduction type are identical or different；
Groove is formed in second semiconductor layer；
It forms field oxide in the groove and field plate, the field oxide covers bottom and the side wall of the groove
A part, formed between the field plate and the part of second semiconductor layer far from first semiconductor layer side empty
Gap；
On side wall, the field plate surface and second semiconductor far from first semiconductor layer in the gap
Layer makes dielectric material far from the surface of first semiconductor layer, with the shape between the field plate and second semiconductor layer
At the slot electrode for deposition of electrode material；
Deposition of electrode material makes first electrode in the slot electrode, forms the field plate surface production of the slot electrode
Dielectric material forms the first separation layer, and the dielectric material for forming the second semiconductor layer surface production of the slot electrode forms first
Oxide layer；
Remove close to first separation layer some electrode materials so that the slot electrode in retain electrode material with
Isolated groove is formed between first separation layer, the isolated groove is for making the second separation layer；
Production forms second separation layer in the isolated groove；
The first conductivity regions and the second conductivity regions are made in the substrate；
In the substrate side, production covers the dielectric layer of the first electrode；And
Second electrode and third electrode are made in the substrate two sides.
Further, the slot electrode includes two slot electrodes positioned at the field plate two sides, the electrode material filling
In in each slot electrode, and the electrode material covers second semiconductor layer far from first semiconductor layer surface
Dielectric material；Wherein, it removes and includes: close to the step of some electrode materials of first separation layer
Remove some electrode materials in each slot electrode close to first separation layer；
Removal is located at a part of electrode material of second semiconductor layer far from first semiconductor layer side, protects
Stay the portion covered in the electrode material of second semiconductor layer far from first semiconductor layer side close to the slot electrode
Divide material；
The gap between electrode material and first separation layer retained in the slot electrode forms the isolating trenches
Slot.
Further, the slot electrode includes two slot electrodes positioned at the field plate two sides, the electrode material filling
In in each slot electrode；Wherein, it removes and includes: close to the step of some electrode materials of first separation layer
The some electrode materials in each slot electrode close to first separation layer are removed, are retained in the slot electrode
Gap between electrode material and first separation layer forms the isolated groove.
Further, the isolated groove includes two isolated grooves positioned at the field plate two sides；In the isolating trenches
The step of formation second separation layer, includes: in slot
Fill isolated material in each isolated groove, the electrode material retained in the slot electrode and described the
Isolated material between one separation layer forms second separation layer；
The isolated material also covers the electrode material retained in the slot electrode and is located at second semiconductor
Layer is far from the dielectric material in first semiconductor layer surface.
Further, the isolated groove includes two isolated grooves positioned at the field plate two sides；In the isolating trenches
The step of formation second separation layer, includes: in slot
In thermal oxide growth condition, the electrode material retained in the slot electrode grows to form thermal growth oxide layer, institute
It states thermal growth oxide layer and fills the isolated groove, form second separation layer.
Further, first conduction type is N or p-type, and second conduction type is N-type or p-type.
The present invention also provides a kind of semiconductor devices, comprising:
Substrate, the substrate include the first semiconductor layer and the second semiconductor layer, and first semiconductor layer has first
Conduction type, second semiconductor layer have the second conduction type, and first conduction type is identical as the second conduction type
Or it is different；
Field oxide and field plate in second semiconductor layer, the field oxide be located at the field plate with it is described
Between second semiconductor layer；
First electrode, the first electrode are located at the field plate two sides, make between the first electrode and the field plate
There are the first separation layer and the second separation layer, production has the first oxide layer between the first electrode and second semiconductor layer,
Thickness of the sum of first separation layer and the second separation layer thickness greater than first oxide layer；Wherein, second isolation
Layer is to grow to obtain under hot oxide growth environment with first electrode growth basis, alternatively, second separation layer is by institute
After a part removal for stating first electrode, make to form isolated groove between the electrode material and first separation layer that retain, institute
The second separation layer is stated to be made in the isolated groove；
Cover the dielectric layer of the first electrode；
It is made in the first conductivity regions and the second conductivity regions in the substrate；And
It is made in the second electrode and third electrode of the substrate two sides.
Further, the first electrode is arranged between the field plate and second semiconductor layer.
Further, the first electrode includes first part and second part, and the first part is arranged in the field
Between plate and the second semiconductor layer, the second part is arranged in second semiconductor layer far from first semiconductor layer one
Side.
Further, first conduction type is N or p-type, and second conduction type is N-type or p-type.
By first removing a part of electrode material, making slot electrode during making grid in the embodiment of the present application
Isolated groove is formed between the electrode material of interior reservation and the first separation layer, while can make the second isolation in isolated groove again
Layer.In this way, the sum of thickness of the first separation layer and the second separation layer can be significantly greater than the thickness of the first oxide layer, so that the
The overall quality of separation layer between one electrode and field plate is improved.The limiting value of the grid source maximum voltage of semiconductor devices is more
Height, meanwhile, it can solve the IGSS/HTGB Problem of Failure of device, the device with higher grid source maximum voltage can be produced,
Interelectrode robustness can be improved simultaneously, improve the reliability of device.The production process of device is simple, and the thickness of separation layer can
Control, cost of manufacture are lower.
To enable the above objects, features and advantages of the present invention to be clearer and more comprehensible, preferred embodiment is cited below particularly, and cooperate
Appended attached drawing, is described in detail below.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below will be to needed in the embodiment attached
Figure is briefly described, it should be understood that the following drawings illustrates only certain embodiments of the present invention, therefore is not construed as pair
The restriction of range for those of ordinary skill in the art without creative efforts, can also be according to this
A little attached drawings obtain other relevant attached drawings.
Fig. 1 a is the device schematic diagram for making isolating oxide layer and grid oxic horizon in the prior art.
Fig. 1 b is a kind of flow diagram of the manufacturing method of semiconductor devices provided by the embodiments of the present application.
Fig. 1 c is the corresponding structure of step S101 in a kind of manufacturing method of semiconductor devices provided by the embodiments of the present application
Schematic diagram.
Fig. 2 is that the corresponding structure of step S102 is shown in a kind of manufacturing method of semiconductor devices provided by the embodiments of the present application
It is intended to.
Fig. 3 to Fig. 5 is that step S103 is corresponding in a kind of manufacturing method of semiconductor devices provided by the embodiments of the present application
Structural schematic diagram.
Fig. 6 is that the corresponding structure of step S104 is shown in a kind of manufacturing method of semiconductor devices provided by the embodiments of the present application
It is intended to.
Fig. 7 is that the corresponding structure of step S105 is shown in a kind of manufacturing method of semiconductor devices provided by the embodiments of the present application
It is intended to.
Fig. 8 is to form the first separation layer and first in a kind of manufacturing method of semiconductor devices provided by the embodiments of the present application
Structural schematic diagram after oxide layer.
Fig. 9 is the partial enlargement diagram of the part I in Fig. 8.
Figure 10 is a kind of signal of gate structure in a kind of manufacturing method of semiconductor devices provided by the embodiments of the present application
Figure.
Figure 11 is that another gate structure shows in a kind of manufacturing method of semiconductor devices provided by the embodiments of the present application
It is intended to.
Figure 12 is the corresponding knot of sub-step S161 in a kind of manufacturing method of semiconductor devices provided by the embodiments of the present application
Structure schematic diagram.
Figure 13 is after removing some electrode materials in a kind of manufacturing method of semiconductor devices provided by the embodiments of the present application
Structural schematic diagram.
Figure 14 is sub-step S162 and sub-step in a kind of manufacturing method of semiconductor devices provided by the embodiments of the present application
The corresponding structural schematic diagram of S163.
Figure 15 is after removing some electrode materials in a kind of manufacturing method of semiconductor devices provided by the embodiments of the present application
Another structural schematic diagram.
Figure 16 and Figure 17 is S171 pairs of sub-step in a kind of manufacturing method of semiconductor devices provided by the embodiments of the present application
The structural schematic diagram answered.
Figure 18 is the knot that the second separation layer is formed in a kind of manufacturing method of semiconductor devices provided by the embodiments of the present application
Structure schematic diagram.
Figure 19 is the partial enlargement diagram of the part II in Figure 18.
Figure 20 is to form the another of the second separation layer in a kind of manufacturing method of semiconductor devices provided by the embodiments of the present application
One structural schematic diagram.
Figure 21 is the partial enlargement diagram of the part III in Figure 20.
Figure 22 to Figure 25 is that production first is conductive in a kind of manufacturing method of semiconductor devices provided by the embodiments of the present application
Class area, the second conductivity regions, dielectric layer, the corresponding structural schematic diagram of second electrode.
Figure 26, Figure 27 and Figure 28 are a kind of structural schematic diagram of semiconductor devices provided by the embodiments of the present application.
Icon: 10- semiconductor devices；101- substrate；The first semiconductor layer of 111-；The second semiconductor layer of 112-；113- ditch
Slot；The first conductivity regions 114-；The second conductivity regions 115-；116- contact hole ion implanted region；102- field oxide；
103- field plate；The gap 131-；104- dielectric material；141- slot electrode；The first separation layer of 142-；The first oxide layer of 143-；105-
Electrode material；151- first electrode；106- photoresist；107- isolated groove；The second separation layer of 108-；181- isolated material；
109- dielectric layer；110- second electrode；120- third electrode.
Specific embodiment
Below in conjunction with attached drawing in the embodiment of the present invention, technical solution in the embodiment of the present invention carries out clear, complete
Ground description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.Usually exist
The component of the embodiment of the present invention described and illustrated in attached drawing can be arranged and be designed with a variety of different configurations herein.Cause
This, is not intended to limit claimed invention to the detailed description of the embodiment of the present invention provided in the accompanying drawings below
Range, but it is merely representative of selected embodiment of the invention.Based on the embodiment of the present invention, those skilled in the art are not doing
Every other embodiment obtained under the premise of creative work out, shall fall within the protection scope of the present invention.
It should also be noted that similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined in a attached drawing, does not then need that it is further defined and explained in subsequent attached drawing.Meanwhile of the invention
In description, term " first ", " second " etc. are only used for distinguishing description, are not understood to indicate or imply relative importance.
The embodiment of the present application provides a kind of manufacturing method of semiconductor devices, as shown in Figure 1 b, includes the following steps.
Step S101 provides a substrate 101 as illustrated in figure 1 c, and the substrate 101 includes the first semiconductor layer 111 and position
The second semiconductor layer 112 in 111 side of the first semiconductor layer, first semiconductor layer 111 have the first conductive-type
Type, second semiconductor layer 112 have the second conduction type, and first conduction type is identical as the second conduction type or not
Together.First semiconductor layer 111 and the second semiconductor layer 112 can be carried out n-type doping, specifically, the first semiconductor layer 111 can
To carry out N-type heavy doping, the second semiconductor layer 112 carries out N-type and is lightly doped, so that the first semiconductor layer 111 and the second half
The conduction type having the same of conductor layer 112.It is understood that first conduction type is N or p-type, described second is led
Electric type is N-type or p-type.Forming p-type doping in the first semiconductor layer 111 can when second semiconductor layer 112 forms n-type doping
Insulated gate bipolar transistor IGBT is formed with production, the embodiment of the present application is to the first semiconductor layer 111 and the second semiconductor layer
112 conduction type does not make limitation.
Step S102, as shown in Fig. 2, forming groove 113 in second semiconductor layer 112.
The depth of groove 113 in second semiconductor layer 112 can determines according to actual conditions, and the embodiment of the present application is not
Limit the specific depth of groove 113.It is understood that may be used also after etching forms groove 113 in the second semiconductor layer 112
To carry out the growth and removal of sacrificial oxide layer.
Step S103, forms field oxide 102 and field plate 103 in the groove 113, and the field oxide 102 covers
The bottom of the groove 113 and a part of side wall are formed empty between the field plate 103 and second semiconductor layer 112
Gap 131.
After the production for completing groove 113, it can continue to make field oxide 102 and field plate 103 in groove 113.In detail
Thin, field oxide 102 is formed as shown in figure 3, can first grow in groove 113, then as shown in figure 4, in field oxide 102
Interior production forms field plate 103.Returning for field oxide 102 is carried out again to carve, and forms structure as shown in Figure 5.It is understood that field
Plate 103 can be made of polycrystalline silicon material.In the Hui Kehou for completing field oxide 102, field plate 103 and the second semiconductor
Gap 131 is formd between layer 112.
Step S104, as shown in fig. 6, in the side wall in the gap 131 and bottom, the field plate 103 far from described first
The surface somatomedin of the surface of semiconductor layer 111 and second semiconductor layer 112 far from first semiconductor layer 111
Material 104, to form the electrode for being used for deposition of electrode material 105 between the field plate 103 and second semiconductor layer 112
Slot 141.
Step S105, as shown in fig. 7, depositing the electrode material 105 in the slot electrode 141.
Electrode material 105 can not only fill slot electrode 141, can also cover the surface of the second semiconductor layer 112.
For the convenience of description, as shown in figure 8, the dielectric material 104 between electrode material 105 and field plate 103 is used as first
Separation layer 142, the oxidation material between electrode material 105 and the second semiconductor layer 112 is as the first oxide layer 143.First every
Absciss layer 142 and the first oxide layer 143 are formed by the dielectric material 104 of aforementioned growth.
In the embodiment of the present application, the first separation layer 142 is to carry out oxidation growth based on field plate 103 to obtain, the
One oxide layer 143 is obtained with the basic oxidation growth of the second semiconductor layer 112.Field plate 103 is using polycrystalline silicon material, and
When substrate 101 is using single crystal silicon material, under same growing environment, the growth rate for obtaining the first separation layer 142 is compared
To the first oxide layer 143 growth rate faster so that the thickness D2 of the first separation layer 142 is greater than the first oxide layer
143 thickness D1, as shown in Figure 9.It is understood that when the specific thickness of the first oxide layer 143 can be according to design device
Threshold voltage determine that the embodiment of the present application is not intended to limit the specific thickness of the first oxide layer 143.Optionally, the first oxidation
The thickness of layer 143 can be in 200A between 900A.
Semiconductor devices in the embodiment of the present application can be used as field-effect tube, and first electrode 151 therein can be used as
Grid in field-effect tube.Although inventor has found that the first separation layer between field plate 103 and first electrode 151
142 thickness is thicker than the first oxide layer 143, but the first separation layer 142 directly grown based on field plate 103 is still
That comparison is weak, the first weaker separation layer 142 will the limiting value of grid source maximum voltage VGSS to device cause
Limitation, meanwhile, can also there are problems that IGSS/HTGB failure.
Step S106 removes some electrode materials 105 close to first separation layer 142, so that the slot electrode 141
Isolated groove 107 is formed between the electrode material 105 of interior reservation and first separation layer 142, the isolated groove 107 is used for
Make the second separation layer 108.
In order to improve the gate source voltage of device and solve puzzlement caused by IGSS/HTGB failure, in the embodiment of the present application
In, after filling electrode material 105 in slot electrode 141, does not continue to make other structures, but first remove in slot electrode 141
A part of electrode material 105.Detailed, some electrode materials 105 that can will be close to the first separation layer 142 remove, so that
New isolated groove 107 is formed between the electrode material 105 and the first separation layer 142 retained in slot electrode 141.
In the embodiment of the present application, the quantity of slot electrode 141 be two, be located at 103 two sides of field plate, so as to so that
The first electrode 151 that must be made also is two first electrodes 151, to form grid dividing structure.In the system for carrying out isolated groove 107
When making, equally some electrode materials 105 in each slot electrode 141 close to the first separation layer 142 are removed, thus in field plate
103 two sides form two isolated grooves 107.
Detailed, the structure of first electrode 151 can form two kinds of situations, and one is as shown in Figure 10, first electrodes 151
It is only located between field plate 103 and the second semiconductor layer 112；Another kind is that as shown in figure 11, first electrode 151 is not only comprising being located at
Part between field plate 103 and the second semiconductor layer 112 further includes being located at the second semiconductor layer 112 far from the first semiconductor layer
The another part on 111 surfaces.
With the difference of 151 structure of first electrode, the step of forming isolated groove 107, is also different.Specifically, in a kind of reality
It applies in mode, the slot electrode 141 can also include two slot electrodes 141 positioned at 103 two sides of field plate, the electrode material
Material 105 is filled in each slot electrode 141.Wherein, some electrode materials close to first separation layer 142 are removed
105 the step of includes following sub-step.
Sub-step S161 removes some electrode materials 105 in each slot electrode 141 close to first separation layer 142,
The gap between electrode material 105 and first separation layer 142 retained in the slot electrode 141 forms the isolating trenches
Slot 107.
When being removed to electrode material 105 as shown in Figure 10, photoresist 106 can be coated in the side of device,
As shown in figure 12, photoresist 106 exposes some electrode materials 105 in slot electrode 141 close to the first separation layer 142, from
And some electrode materials 105 that can will be close to the first separation layer 142 in the next steps remove, and are tied as shown in fig. 13 that
Structure, the electrode material 105 retained in slot electrode 141 form first electrode 151.
In another embodiment, the slot electrode 141 includes two slot electrodes positioned at 103 two sides of field plate
141, the electrode material 105 is filled in each slot electrode 141, and the electrode material 105 covers described the second half
Dielectric material 104 of the conductor layer 112 far from 111 surface of the first semiconductor layer.It removes close to first separation layer 142
The step of some electrode materials 105 includes following sub-step.
Sub-step S162 removes some electrode materials 105 in each slot electrode 141 close to first separation layer 142.
Sub-step S163, removal are located at electricity of second semiconductor layer 112 far from 111 side of the first semiconductor layer
A part of pole material 105 retains and covers the electricity of the second semiconductor layer 112 far from 111 side of the first semiconductor layer
Close to some materials of the slot electrode 141 in pole material 105；The electrode material 105 retained in the slot electrode 141 and institute
It states the gap between the first separation layer 142 and forms the isolated groove 107.
, can be as shown in figure 14 when carrying out part removal to 151 structure of first electrode as shown in figure 11, in part electricity
Photoresist 106 is coated on pole material 105, then electrode material 105 is performed etching, and is removed some electrode materials 105, is made to retain
Electrode material 105 and field plate 103 between form isolated groove 107, structure as shown in figure 15 is obtained, in the embodiment of the present application
Isolated groove 107 be two.In the etching removal process of electrode material 105, in order to avoid etching into slot electrode 141 as far as possible
The dielectric material 104 of interior 105 lower section of electrode material, can use the lithographic method of high selectivity ratio.It is gone to electrode material 105
Except after the completion, photoresist 106 can be removed.
Step S107, production forms second separation layer 108 in the isolated groove 107.
The method that the second separation layer 108 is made in isolated groove 107 may include two kinds, and one is in isolated groove
Isolated material 181 is filled in 107, another kind is under thermal oxidizing conditions, with 151 polycrystalline of 103 polysilicon of field plate and first electrode
Growth obtains based on silicon.
It is detailed, it can make to form the second separation layer 108 by following sub-step.
Sub-step S171 fills isolated material 181 in each isolated groove 107, retains in the slot electrode 141
Under electrode material 105 and first separation layer 142 between isolated material 181 form second separation layer 108.
As shown in Figure 16 and Figure 17, for isolated material 181 while filling isolated groove 107, the isolated material 181 is also
Cover the surface of the electrode material 105 retained in the slot electrode 141, while isolated material 181 also covers and is located at described the
Two semiconductor layers 112 are far from the dielectric material 104 on 111 surface of the first semiconductor layer.The isolated material 181 can lead to
Overpopulation plasma chemical vapor deposition technique forms second separation layer 108 in the isolated groove 107.
In another embodiment, it can make to form the second separation layer 108 by following sub-step.
Sub-step S172, in thermal oxide growth condition, the electrode material 105 that retains in the slot electrode 141 and described
The growth of first separation layer 142 forms thermal growth oxide layer, and the thermal growth oxide layer fills the isolated groove 107, forms institute
State the second separation layer 108.
Second separation layer 108 can be on the basis of 151 polysilicon of first electrode and 103 polysilicon of field plate, in thermal oxide
Growth obtains under growth conditions.Optionally, the second separation layer 108 can be during the second 115 knot of conductivity regions of p-type
151 polysilicon of first electrode and 103 polysilicon oxidation of field plate are obtained.
Isolated material 181 between first electrode 151 and the first separation layer 142 forms second separation layer 108,
Convenient for signal, Figure 18 and Figure 20 just show the second separation layer 108, and the isolated material 181 of other parts does not carry out figure
Show.As shown in Figure 19 and Figure 21, the dielectric material between first electrode 151 and field plate 103 includes the first separation layer 142 and second
Separation layer 108, the sum of thickness of the two are D3, and the first oxide layer 143 is obviously greater than D1, Ke Yili with a thickness of D1, D3
Solution, in identical device specification, D3 is also greater than above-mentioned D2.
Step S108 makes the first conductivity regions 114 and the second conductivity regions 115 in the substrate 101.
Step S109, in 101 side of substrate, production covers the dielectric layer 109 of the first electrode 151.
Step S110 makes second electrode 110 and third electrode 120 in 101 two sides of substrate.
Complete the second separation layer 108 production after, can making devices other structures.It, can be with such as Figure 22 to Figure 25
Ion implanting is first carried out in the second semiconductor layer 112, forms the first conductivity regions 114 and the second conductivity regions of p-type
115, and carry out the knot of the second conductivity regions of p-type 115.When production forms MOS structure, the first conductivity regions 114 can
To form the source region of device, the second conductivity regions 115 can form the well region of device.It makes to form covering first electrode again
The surface of 151 dielectric layer 109, the second semiconductor layer 112 that then can be not covered with to dielectric layer 109 carries out photoetching, shape
The contact hole contacted at second electrode 110 with the second semiconductor layer 112.Further, ion can be carried out at contact hole position
Injection forms contact hole ion implanted region 116.The deposition of metal material is carried out again, forms second electrode 110 and third electrode
120.In addition, can also carry out operation, the application such as the photoetching of metal material, thinned in the production process does not make limitation.
Semiconductor devices in the embodiment of the present application is when as field-effect tube, as previously mentioned, first electrode 151 can be used as field-effect
The grid of pipe can serve as source electrode and the leakage of field-effect tube positioned at the second electrode 110 and third electrode 120 of device two sides
Pole.
It by the above manufacturing method, can make to form the field effect transistor with grid dividing structure, partly be led such
In body device, there is two layers of separation layer, i.e. the first separation layer 142 and the second separation layer between first electrode 151 and field plate 103
108, the second separation layer 108 can be formed by filling isolated material 181, can also be in 151 polysilicon of first electrode and field plate
Thermal oxide growth obtains on the basis of 103 polysilicons.In this way, the thickness of the isolated material 181 between first electrode 151 and field plate 103
Degree will be significantly greater than the thickness of the first oxide layer 143 between first electrode 151 and the second semiconductor layer 112, also, pass through
In addition the second separation layer 108 is made, so that the overall quality of the separation layer between first electrode 151 and field plate 103 is improved.
So that the limiting value of the grid source maximum voltage of semiconductor devices is higher, meanwhile, the IGSS/HTGB failure that can solve device is asked
Topic.
In conclusion by first removing electrode material during making first electrode 151 in the embodiment of the present application
105 a part makes to form isolated groove 107 between the electrode material 105 and the first separation layer 142 that retain in slot electrode 141,
The second separation layer 108 can be made again in isolated groove 107 simultaneously.In this way, the first separation layer 142 and the second separation layer 108
The sum of thickness can be significantly greater than the thickness of the first oxide layer 143, so that the isolation between first electrode 151 and field plate 103
The overall quality of layer is improved.The limiting value of the grid source maximum voltage of semiconductor devices is higher, meanwhile, it can solve device
IGSS/HTGB Problem of Failure can produce the device with higher grid source maximum voltage, while interelectrode heavily fortified point can be improved
Solidity improves the reliability of device.The production process of device is simple, and the thickness of separation layer is controllable, and cost of manufacture is lower.
The embodiment of the present application also provides a kind of semiconductor devices 10, including substrate 101, field oxide 102, field plate 103,
First separation layer 142, the second separation layer 108, first electrode 151, the first oxide layer 143, dielectric layer 109,110 and of second electrode
Third electrode 120.
As previously mentioned, the substrate 101 includes the first semiconductor layer 111 and the second semiconductor layer 112, described the second half are led
The conduction type of body layer 112 is identical as the conduction type of first semiconductor layer 111.Optionally, first semiconductor layer
111 be N-type heavily doped layer, and second semiconductor layer 112 is N-type lightly-doped layer.
Field oxide 102 and field plate 103 are located in second semiconductor layer 112, and the field oxide 102 is located at described
Between field plate 103 and second semiconductor layer 112.
The first electrode 151 is located at 103 two sides of field plate, makes between the first electrode 151 and the field plate 103
Work has the first separation layer 142 and the second separation layer 108, makes between the first electrode 151 and second semiconductor layer 112
Have the first oxide layer 143,108 thickness of first separation layer 142 and the second separation layer and be greater than first oxide layer 143
Thickness.Wherein, it is growth basis in heat that second separation layer 108, which is with first separation layer 142 and first electrode 151,
Growth obtains under oxide growth environment, alternatively, second separation layer 108 is by a part removal of the first electrode 151
Afterwards, make to form isolated groove 107, second separation layer between the electrode material 105 and first separation layer 142 that retain
108 are made in the isolated groove 107.
In the embodiment of the present application, the second separation layer 108 and the first separation layer 142 do not make simultaneously, the second isolation
Layer 108 is to complete in the first separation layer 142, and electrode material 105 is filled in slot electrode 141, then remove electrode material
Formation is made again after a part of material 105.First separation layer 142 and the first oxide layer 143 are to make formation simultaneously, first
Separation layer 142 is formed on the surface of field plate 103, and the first oxide layer 143 is formed in 112 surface of the second semiconductor layer.Such as preceding institute
It states, field plate 103 can be made of polysilicon, in this way, the thickness meeting of the first separation layer 142 formed based on field plate 103
Slightly larger than the thickness of the first oxide layer 143, but it is not sufficient to be greatly improved the limiting value of the grid source maximum voltage of device.
In the embodiment of the present application, the second separation layer has also been fabricated separately between first electrode 151 and the first separation layer 142
108, so that the feelings of the first separation layer 142 are more only arranged in the thickness of the isolated material 181 between first electrode 151 and field plate 103
Condition is thicker, that is, the thickness of the isolated material 181 between first electrode 151 and field plate 103 is significantly greater than the first oxide layer
143 thickness.In this way, the limiting value of the grid source maximum voltage VGSS of device can be significantly improved, meanwhile, it can solve
The problem of IGSS/HTGB fails.
Dielectric layer 109 can cover the first electrode 151 or dielectric layer 109 and can cover to form the second separation layer
108 isolated material 181, also production has the second conductivity regions 115 and the first conductivity regions 114, institute in the substrate 101
Stating 101 two sides of substrate and also making has second electrode 110 and third electrode 120.
In the embodiment of the present application, the structure of first electrode 151 may include two kinds, in as shown in figure 26, institute
First electrode 151 is stated to be arranged between the field plate 103 and second semiconductor layer 112.In another embodiment, such as scheme
Shown in 27, the first electrode 151 includes first part and second part, and the first part is arranged in 103 He of field plate
Between second semiconductor layer 112, the second part is arranged in second semiconductor layer 112 far from first semiconductor layer
111 sides.
For different 151 structures of first electrode when forming isolated groove 107, the covering position of photoresist 106 is different,
The embodiment of the present application is not intended to limit the actual fabrication method of different 151 structures of first electrode.
In another embodiment, as shown in figure 28, the substrate in semiconductor devices 10 can also be using through overdoping
Substrate material, substrate do not form the first semiconductor layer and the second semiconductor layer.
In semiconductor devices 10 in the embodiment of the present application, there is two layers of separation layer, the first isolation between grid and field plate
The sum of thickness of layer 142 and the second separation layer 108 is significantly greater than the thickness of the first oxide layer 143, and the second separation layer is only
Vertical production, so that the overall quality of the separation layer between first electrode 151 and field plate 103 is improved.So that partly leading
The limiting value of the grid source maximum voltage of body device is higher, meanwhile, it can solve the IGSS/HTGB Problem of Failure of device, while electricity
The robustness of interpolar is more preferable, is able to bear bigger peak voltage, and the reliability of device is higher.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.It should also be noted that similar label and letter exist
Similar terms are indicated in following attached drawing, therefore, once being defined in a certain Xiang Yi attached drawing, are then not required in subsequent attached drawing
It is further defined and explained.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
Lid is within protection scope of the present invention.Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. a kind of manufacturing method of semiconductor devices characterized by comprising
A substrate is provided, the substrate includes the first semiconductor layer and the second semiconductor positioned at first semiconductor layer side
Layer, first semiconductor layer have the first conduction type, second semiconductor layer have the second conduction type, described first
Conduction type and the second conduction type are identical or different；
Groove is formed in second semiconductor layer；
Form field oxide and field plate in the groove, the field oxide cover the groove bottom and side wall one
Part forms gap between the field plate and the part of second semiconductor layer far from first semiconductor layer side；
Side wall, the field plate surface and second semiconductor layer far from first semiconductor layer in the gap is remote
Surface from first semiconductor layer makes dielectric material, is used with being formed between the field plate and second semiconductor layer
In the slot electrode of deposition of electrode material；
Deposition of electrode material makes first electrode in the slot electrode, forms the medium of the field plate surface production of the slot electrode
Material forms the first separation layer, and the dielectric material for forming the second semiconductor layer surface production of the slot electrode forms the first oxidation
Layer；
Remove close to first separation layer some electrode materials so that the slot electrode in retain electrode material with it is described
Isolated groove is formed between first separation layer, the isolated groove is for making the second separation layer；
Production forms second separation layer in the isolated groove；
The first conductivity regions and the second conductivity regions are made in the substrate；
In the substrate side, production covers the dielectric layer of the first electrode；And
Second electrode and third electrode are made in the substrate two sides.
2. the manufacturing method of semiconductor devices according to claim 1, which is characterized in that the slot electrode includes being located at institute
Two slot electrodes of field plate two sides are stated, the electrode material is filled in each slot electrode, and the electrode material covers
Dielectric material of second semiconductor layer far from first semiconductor layer surface；Wherein, removal is close to first isolation
Layer some electrode materials the step of include:
Remove some electrode materials in each slot electrode close to first separation layer；
Removal is located at a part of electrode material of second semiconductor layer far from first semiconductor layer side, and reservation is covered
Cover the part material in the electrode material of second semiconductor layer far from first semiconductor layer side close to the slot electrode
Material；
The gap between electrode material and first separation layer retained in the slot electrode forms the isolated groove.
3. the manufacturing method of semiconductor devices according to claim 1, which is characterized in that the slot electrode includes being located at institute
Two slot electrodes of field plate two sides are stated, the electrode material is filled in each slot electrode；Wherein, removal is close to described the
The step of some electrode materials of one separation layer includes:
Remove some electrode materials in each slot electrode close to first separation layer, the electrode retained in the slot electrode
Gap between material and first separation layer forms the isolated groove.
4. the manufacturing method of semiconductor devices according to claim 2 or 3, which is characterized in that the isolated groove includes
Two isolated grooves positioned at the field plate two sides；The step of forming second separation layer in the isolated groove include:
Fill isolated material in each isolated groove, the electrode material retained in the slot electrode with described first every
Isolated material between absciss layer forms second separation layer；
The isolated material also cover the electrode material retained in the slot electrode and be located at second semiconductor layer it is remote
From the dielectric material in first semiconductor layer surface.
5. the manufacturing method of semiconductor devices according to claim 2 or 3, which is characterized in that the isolated groove includes
Two isolated grooves positioned at the field plate two sides；The step of forming second separation layer in the isolated groove include:
In thermal oxide growth condition, the electrode material retained in the slot electrode grows to form thermal growth oxide layer, the heat
It grows oxide layer and fills the isolated groove, form second separation layer.
6. the manufacturing method of semiconductor devices according to claim 1, which is characterized in that first conduction type is N
Or p-type, second conduction type are N-type or p-type.
7. a kind of semiconductor devices characterized by comprising
Substrate, the substrate include the first semiconductor layer and the second semiconductor layer, and first semiconductor layer has the first conduction
Type, second semiconductor layer have the second conduction type, and first conduction type is identical as the second conduction type or not
Together；
Field oxide and field plate in second semiconductor layer, the field oxide are located at the field plate and described second
Between semiconductor layer；
First electrode, the first electrode are located at the field plate two sides, and production has the between the first electrode and the field plate
One separation layer and the second separation layer, production has the first oxide layer between the first electrode and second semiconductor layer, described
Thickness of the sum of first separation layer and the second separation layer thickness greater than first oxide layer；Wherein, second separation layer is
It grows and obtains under hot oxide growth environment with first electrode growth basis, alternatively, second separation layer is by described the
After a part removal of one electrode, make to form isolated groove between the electrode material and first separation layer that retain, described the
Two separation layers are made in the isolated groove；
Cover the dielectric layer of the first electrode；
It is made in the first conductivity regions and the second conductivity regions in the substrate；And
It is made in the second electrode and third electrode of the substrate two sides.
8. semiconductor devices according to claim 7, which is characterized in that the first electrode is arranged in the field plate and institute
It states between the second semiconductor layer.
9. semiconductor devices according to claim 7, which is characterized in that the first electrode includes first part and second
Part, the first part are arranged between the field plate and the second semiconductor layer, and the second part is arranged described second
Semiconductor layer is far from first semiconductor layer side.
10. according to semiconductor devices described in claim 7 to 9 any one, which is characterized in that first conduction type is
N or p-type, second conduction type are N-type or p-type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910069243.3A CN109767986B (en) | 2019-01-24 | 2019-01-24 | Semiconductor device and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910069243.3A CN109767986B (en) | 2019-01-24 | 2019-01-24 | Semiconductor device and method for manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109767986A true CN109767986A (en) | 2019-05-17 |
| CN109767986B CN109767986B (en) | 2021-09-28 |
Family
ID=66455391
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910069243.3A Active CN109767986B (en) | 2019-01-24 | 2019-01-24 | Semiconductor device and method for manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109767986B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112435928A (en) * | 2019-08-26 | 2021-03-02 | 无锡先瞳半导体科技有限公司 | Shielding gate power device and preparation method thereof |
| CN115117171A (en) * | 2021-03-19 | 2022-09-27 | 株式会社东芝 | semiconductor device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7977742B1 (en) * | 2010-08-20 | 2011-07-12 | Monolithic Power Systems, Inc. | Trench-gate MOSFET with capacitively depleted drift region |
| US20130168760A1 (en) * | 2011-12-30 | 2013-07-04 | Force Mos Technology Co. Ltd. | Trench mosfet with resurf stepped oxide and diffused drift region |
| CN103367144A (en) * | 2012-03-26 | 2013-10-23 | 马克斯半导体股份有限公司 | Trench-type structure of junction electric-field shielding power MOSFET and manufacturing method |
| EP2466629B1 (en) * | 2010-12-14 | 2017-10-11 | STMicroelectronics Srl | A method and a structure for enhancing electrical insulation and dynamic performance of MIS structures comprising vertical field plates |
| CN108767004A (en) * | 2018-08-03 | 2018-11-06 | 江苏捷捷微电子股份有限公司 | A kind of separation grid MOSFET component structure and its manufacturing method |
| CN109065542A (en) * | 2018-08-10 | 2018-12-21 | 无锡新洁能股份有限公司 | A kind of shielding gate power MOSFET device and its manufacturing method |
-
2019
- 2019-01-24 CN CN201910069243.3A patent/CN109767986B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7977742B1 (en) * | 2010-08-20 | 2011-07-12 | Monolithic Power Systems, Inc. | Trench-gate MOSFET with capacitively depleted drift region |
| EP2466629B1 (en) * | 2010-12-14 | 2017-10-11 | STMicroelectronics Srl | A method and a structure for enhancing electrical insulation and dynamic performance of MIS structures comprising vertical field plates |
| US20130168760A1 (en) * | 2011-12-30 | 2013-07-04 | Force Mos Technology Co. Ltd. | Trench mosfet with resurf stepped oxide and diffused drift region |
| CN103367144A (en) * | 2012-03-26 | 2013-10-23 | 马克斯半导体股份有限公司 | Trench-type structure of junction electric-field shielding power MOSFET and manufacturing method |
| CN108767004A (en) * | 2018-08-03 | 2018-11-06 | 江苏捷捷微电子股份有限公司 | A kind of separation grid MOSFET component structure and its manufacturing method |
| CN109065542A (en) * | 2018-08-10 | 2018-12-21 | 无锡新洁能股份有限公司 | A kind of shielding gate power MOSFET device and its manufacturing method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112435928A (en) * | 2019-08-26 | 2021-03-02 | 无锡先瞳半导体科技有限公司 | Shielding gate power device and preparation method thereof |
| CN112435928B (en) * | 2019-08-26 | 2023-12-29 | 无锡先瞳半导体科技有限公司 | Shielding grid power device and preparation method thereof |
| CN115117171A (en) * | 2021-03-19 | 2022-09-27 | 株式会社东芝 | semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109767986B (en) | 2021-09-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI482236B (en) | Semiconductor trench structure and method with sealed plug | |
| EP1842236B1 (en) | Manufacturing process for high voltage semiconductor device | |
| JP4880199B2 (en) | High voltage power MOSFET with voltage sustaining region including a doped column formed by trench etching and diffusion from a region of oppositely doped polysilicon | |
| JP4928947B2 (en) | Manufacturing method of super junction device | |
| TWI696242B (en) | Method for forming a thin semiconductor-on-insulator (soi) substrate | |
| US10580775B2 (en) | Dual deep trenches for high voltage isolation | |
| EP1702358A2 (en) | A method for forming thick dielectric regions using etched trenches | |
| CN101138077A (en) | Fabrication of Lateral Semiconductor Devices | |
| US10672901B2 (en) | Power transistor with terminal trenches in terminal resurf regions | |
| CN101258588A (en) | Method for manufacturing semiconductor power devices | |
| US9929259B2 (en) | Semiconductor device and manufacturing method for semiconductor device | |
| US7192872B2 (en) | Method of manufacturing semiconductor device having composite buffer layer | |
| US7220661B1 (en) | Method of manufacturing a Schottky barrier rectifier | |
| US7435628B1 (en) | Method of forming a vertical MOS transistor | |
| CN109830526A (en) | A kind of power semiconductor and preparation method thereof | |
| US9431286B1 (en) | Deep trench with self-aligned sinker | |
| JP2020129597A (en) | Semiconductor device and method of manufacturing semiconductor device | |
| CN109767986A (en) | Semiconductor devices and its manufacturing method | |
| US6249025B1 (en) | Using epitaxially grown wells for reducing junction capacitances | |
| US20180053766A1 (en) | High Density Vertical Thyristor Memory Cell Array with Improved Isolation | |
| CN109860302A (en) | A kind of power metal-oxide-semiconductor field effect transistor and its manufacture of new model | |
| TWI460823B (en) | Method for manufacturing trench type metal oxide semiconductor field effect transistor | |
| JP7607120B2 (en) | Semiconductor device having split gate structure and manufacturing method thereof | |
| CN101924104A (en) | Structure of metal oxide semiconductor and manufacturing method thereof | |
| CN114156183A (en) | Split gate power MOS device and method of making the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |