CN109785889B - An adaptive charging and discharging circuit, method and device - Google Patents
An adaptive charging and discharging circuit, method and device Download PDFInfo
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Abstract
本发明实施例公开了一种自适应的充放电电路，所述电路包括：检测单元和充放电控制单元，其中：所述检测单元的输入端与存储阵列的每一闪存单元对应的电容的输出端连接，所述检测单元的输出端与所述充放电控制单元的输入端连接；所述充放电控制单元的输出端与每一所述闪存单元对应的电容的输入端连接；所述检测单元，用于对每一所述闪存单元对应的电容进行充放电时，对每一所述闪存单元对应的电容的电压进行监测，并将监测结果发送至所述充放电控制单元；所述充放电控制单元，用于接收所述检测单元发送的监测结果，并基于所述监测结果控制每一所述闪存单元对应的电容的充放电操作。本发明的实施例同时还公开了一种自适应的充放电方法和设备。
An embodiment of the present invention discloses an adaptive charging and discharging circuit, the circuit includes: a detection unit and a charging and discharging control unit, wherein: an input end of the detection unit is an output of a capacitor corresponding to each flash memory unit of a storage array The output end of the detection unit is connected to the input end of the charge and discharge control unit; the output end of the charge and discharge control unit is connected to the input end of the capacitor corresponding to each flash memory unit; the detection unit is used to monitor the voltage of the capacitor corresponding to each flash memory cell when charging and discharging the capacitor corresponding to each flash memory cell, and send the monitoring result to the charging and discharging control unit; the charging and discharging The control unit is configured to receive the monitoring result sent by the detection unit, and control the charging and discharging operation of the capacitor corresponding to each flash memory unit based on the monitoring result. The embodiments of the present invention also disclose an adaptive charging and discharging method and device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a self-adaptive charge and discharge circuit, a method and equipment.
Background
In the NAND flash memory, generally, the capacitance of a bit line corresponding to a NAND flash memory cell needs to be controlled to be charged and discharged; in the related art, the charging operation of the capacitor of the bit line corresponding to the NAND flash memory cell is generally controlled by a fixed precharge time, and the discharging operation of the capacitor of the bit line corresponding to the NAND flash memory cell is generally controlled by a fixed discharge start time.
However, the process, power supply, temperature, etc. of the bit line corresponding to the NAND flash memory cell may have variations; therefore, the charging and discharging method of the capacitor of the bit line in the related art has the defect of outputting error data due to insufficient charging or excessive discharging under the influence of the process, the supplied power supply, the temperature and the like.
Disclosure of Invention
In view of this, embodiments of the present invention are expected to provide a self-adaptive charging and discharging circuit, method, and device, so as to solve the problem that the charging and discharging method of the capacitor of the bit line in the relative art may have insufficient charging or excessive discharging, avoid outputting incorrect data, and improve the accuracy and working efficiency of the output data.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
an adaptive charge-discharge circuit, the circuit comprising: a detection unit and a charge and discharge control unit; wherein:
the input end of the detection unit is connected with the output end of a capacitor corresponding to each flash memory unit of the storage array, and the output end of the detection unit is connected with the input end of the charge and discharge control unit;
the output end of the charge and discharge control unit is connected with the input end of the capacitor corresponding to each flash memory unit;
the detection unit is used for monitoring the voltage of the capacitor corresponding to each flash memory unit when the capacitor corresponding to each flash memory unit is charged and discharged, and sending the monitoring result to the charging and discharging control unit;
and the charge and discharge control unit is used for receiving the monitoring result sent by the detection unit and controlling the charge and discharge operation of the capacitor corresponding to each flash memory unit based on the monitoring result.
In the above scheme, the circuit further includes: first MOS pipe and second MOS pipe, wherein:
a first pole of the first MOS tube is connected with a power supply, a second pole of the first MOS tube is connected with the input end of the capacitor corresponding to each flash memory unit, and a third pole of the first MOS tube is connected with the output end of the charge and discharge control unit;
the first pole of the second MOS tube is grounded, the second pole of the second MOS tube is connected with the input end of the capacitor corresponding to each flash memory unit, and the third pole of the second MOS tube is connected with the output end of the charge-discharge control unit.
In the above solution, the detecting unit includes: a first detector, wherein:
the input end of the first detector is connected with the input end of the capacitor corresponding to each flash memory unit, and the output end of the first detector is connected with the input end of the charge and discharge control unit.
In the foregoing aspect, the charge/discharge control unit includes: a first controller and a second controller, wherein:
the input end of the first controller is connected with the output end of the first detector, and the output end of the first controller is connected with the third pole of the first MOS tube;
the input end of the second controller is connected with the output end of the first detector, and the output end of the second controller is connected with the third pole of the second MOS tube.
In the above solution, the detecting unit includes: a second detector and a third detector, wherein:
the input end of the second detector is connected with the input end of the capacitor corresponding to each flash memory unit, and the output end of the second detector is connected with the input end of the charge and discharge control unit;
the input end of the third detector is connected with the input end of the capacitor corresponding to each flash memory unit, and the output end of the third detector is connected with the input end of the charge and discharge control unit.
In the above scheme, an enable end of the third detector is connected to an output end of the charge and discharge control unit;
and the enabling end of the second detector is connected with an external enabling signal.
In the foregoing aspect, the charge/discharge control unit includes: a first controller and a second controller, wherein:
the input end of the first controller is connected with the output end of the second detector, and the output end of the first controller is connected with the third pole of the first MOS tube;
the input end of the second controller is connected with the output end of the third detector, and the output end of the second controller is connected with the third pole of the second MOS tube.
In the above scheme, the output terminal of the first controller is connected to the enable terminal of the third detector.
In the above scheme, the type of the first MOS transistor is different from the type of the second MOS transistor.
An adaptive charging and discharging device, the device comprising: a controller and a processor, wherein:
the controller is used for monitoring a first voltage value of a capacitor corresponding to each flash memory unit after the capacitor corresponding to each flash memory unit of the storage array is precharged;
the processor is configured to control a charging operation of the capacitor corresponding to each flash memory cell based on a relationship between a first voltage value of the capacitor corresponding to each flash memory cell and a first preset threshold voltage.
In the foregoing solution, the processor is further configured to:
and if the capacitor with the first voltage value larger than the first preset threshold voltage exists in the capacitor corresponding to each flash memory unit, controlling the capacitor with the first voltage value larger than the first preset threshold voltage to stop charging.
In the foregoing solution, the processor is further configured to:
and outputting a monitoring instruction for indicating to monitor the discharging operation of the capacitor corresponding to each flash memory unit.
In the above scheme, the controller is further configured to monitor a second voltage value of the capacitor corresponding to each flash memory cell after discharging the capacitor corresponding to each flash memory cell;
the processor is further configured to control a discharging operation of the capacitor corresponding to each flash memory cell based on a relationship between a second voltage value of the capacitor corresponding to each flash memory cell and a second preset threshold voltage.
In the foregoing solution, the processor is further configured to:
if the capacitor with the second voltage value smaller than the second preset threshold voltage exists in the capacitor corresponding to each flash memory unit, the capacitor with the second voltage value smaller than the second preset threshold voltage is controlled to stop discharging, and indication information used for indicating that the capacitor with the second voltage value smaller than the second preset threshold voltage is discharged is output.
In the foregoing solution, the controller is further configured to:
and after the capacitor corresponding to each flash memory unit is discharged, monitoring a second voltage value of the capacitor corresponding to each flash memory unit based on the monitoring instruction.
An adaptive charging and discharging method, the method comprising:
after a capacitor corresponding to each flash memory unit of a storage array is precharged, monitoring a first voltage value of the capacitor corresponding to each flash memory unit;
and controlling the charging operation of the capacitor corresponding to each flash memory unit based on the relation between the first voltage value of the capacitor corresponding to each flash memory unit and the first preset threshold voltage.
In the foregoing solution, the controlling the charging operation of the capacitor corresponding to each flash memory cell based on a relationship between a first voltage value of the capacitor corresponding to each flash memory cell and a first preset threshold voltage includes:
and if the capacitor with the first voltage value larger than the first preset threshold voltage exists in the capacitor corresponding to each flash memory unit, controlling the capacitor with the first voltage value larger than the first preset threshold voltage to stop charging.
In the foregoing solution, if there is a capacitor having a first voltage value greater than a first preset threshold voltage in the capacitor corresponding to each flash memory cell, after controlling the capacitor having the first voltage value less than the first preset threshold voltage to stop charging, the method further includes:
and outputting a monitoring instruction for indicating to monitor the discharging operation of the capacitor corresponding to each flash memory unit.
In the above scheme, the method further comprises:
after the capacitor corresponding to each flash memory unit is discharged, monitoring a second voltage value of the capacitor corresponding to each flash memory unit;
and controlling the discharging operation of the capacitor corresponding to each flash memory unit based on the relation between the second voltage value of the capacitor corresponding to each flash memory unit and the second preset threshold voltage.
In the foregoing solution, the controlling the discharging operation of the capacitor corresponding to each flash memory cell based on a relationship between a second voltage value of the capacitor corresponding to each flash memory cell and a second preset threshold voltage includes:
if the capacitor with the second voltage value smaller than the second preset threshold voltage exists in the capacitor corresponding to each flash memory unit, the capacitor with the second voltage value smaller than the second preset threshold voltage is controlled to stop discharging, and indication information used for indicating that the capacitor with the second voltage value smaller than the second preset threshold voltage is discharged is output.
In the foregoing solution, after discharging the capacitor corresponding to each flash memory cell, monitoring a second voltage value of the capacitor corresponding to each flash memory cell includes:
and after the capacitor corresponding to each flash memory unit is discharged, monitoring a second voltage value of the capacitor corresponding to each flash memory unit based on the monitoring instruction.
The embodiment of the invention provides a self-adaptive charging and discharging circuit, a method and equipment, wherein the circuit comprises a detection unit and a charging and discharging control unit; the input end of the detection unit is connected with the output end of the capacitor corresponding to each flash memory unit of the storage array, and the output end of the detection unit is connected with the input end of the charge-discharge control unit; the output end of the charge and discharge control unit is connected with the input end of the capacitor corresponding to each flash memory unit, so that the detection unit detects the charge and discharge condition of the capacitor of the bit line and then sends the charge and discharge condition to the charge and discharge control unit, and the charge and discharge control unit can control the charge and discharge condition of the capacitor of the bit line, thereby solving the problem that the charge and discharge method of the capacitor of the bit line in the relative technology has insufficient charge or excessive discharge, avoiding the occurrence of output error data, and improving the accuracy and the working efficiency of the output data.
Drawings
Fig. 1 is a schematic structural diagram of a self-adaptive charging/discharging circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another adaptive charge/discharge circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a self-adaptive charging/discharging circuit according to another embodiment of the present invention;
fig. 4 is a schematic structural diagram of another adaptive charge/discharge circuit according to another embodiment of the present invention;
fig. 5 is a schematic flowchart of a self-adaptive charging and discharging method according to an embodiment of the present invention;
fig. 6 is a schematic flow chart of another adaptive charging and discharging method according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a self-adaptive charging and discharging device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail below with reference to the accompanying drawings and examples. It should be understood that the examples provided herein are merely illustrative of the present invention and are not intended to limit the present invention. In addition, the following embodiments are provided as partial embodiments for implementing the present invention, not all embodiments for implementing the present invention, and the technical solutions described in the embodiments of the present invention may be implemented in any combination without conflict.
An embodiment of the present invention provides an adaptive charging and discharging circuit, which is shown in fig. 1 and includes: a detection unit 1 and a charge-discharge control unit 2, wherein:
the input end of the detection unit 1 is connected with the output end of a capacitor corresponding to each flash memory unit of the storage array, and the output end of the detection unit 1 is connected with the input end of the charge-discharge control unit 2;
the output end of the charge and discharge control unit 2 is connected with the input end of the capacitor corresponding to each flash memory unit.
And the detection unit is used for monitoring the voltage of the capacitor corresponding to each flash memory unit when the capacitor corresponding to each flash memory unit is charged and discharged, and sending the monitoring result to the charging and discharging control unit.
And the charge and discharge control unit is used for receiving the monitoring result sent by the detection unit and controlling the charge and discharge operation of the capacitor corresponding to each flash memory unit based on the monitoring result of the voltage of the capacitor corresponding to each flash memory unit.
The memory array can be a three-dimensional NAND type flash memory array; in one possible implementation, charging the capacitor corresponding to each flash memory cell in the memory array may be accomplished by charging the bit line corresponding to the capacitor in each flash memory cell.
The detection unit may include a detector, and the detection unit is mainly configured to monitor and acquire a voltage condition on each bit line in real time when the bit line corresponding to the capacitor of the flash memory cell in the three-dimensional NAND-type flash memory array is charged and discharged, and may send the monitored voltage condition on each bit line to the charge and discharge control unit.
The charge and discharge control unit comprises a controller used for controlling charge and discharge operations on each bit line, and can control the charge and discharge operations on each bit line according to the condition of the voltage on each bit line and preset logic after receiving the condition of the voltage on each bit line sent by the monitoring unit; that is, the charge and discharge control unit may control whether to continue the charge and discharge operation on each bit line.
The embodiment of the invention provides a self-adaptive charge and discharge circuit, which comprises a detection unit and a charge and discharge control unit; the input end of the detection unit is connected with the output end of the capacitor corresponding to each flash memory unit of the storage array, and the output end of the detection unit is connected with the input end of the charge-discharge control unit; the output end of the charge and discharge control unit is connected with the input end of the capacitor corresponding to each flash memory unit, so that the detection unit detects the charge and discharge condition of the capacitor corresponding to the flash memory unit and then sends the charge and discharge condition to the charge and discharge control unit, and the charge and discharge control unit can control the charge and discharge operation of the capacitor corresponding to the flash memory unit, thereby solving the problem that the charge and discharge method of the capacitor of the bit line in the relative technology has insufficient charge or excessive discharge, avoiding the occurrence of output wrong data, and improving the accuracy and the working efficiency of the output data.
Based on the foregoing embodiments, an embodiment of the present invention provides an adaptive charging and discharging circuit, which, as shown in fig. 1, includes: detecting element 1, charge-discharge control unit 2, first MOS pipe 3 and second MOS pipe 4, detecting element 1 includes: the first detector 11, the charge and discharge control unit 2 includes: a first controller 21 and a second controller 22, wherein:
the first pole of the first MOS transistor 3 is connected to the power supply, the second pole of the first MOS transistor 3 is connected to the input terminal of the capacitor corresponding to each flash memory cell, and the third pole of the first MOS transistor 3 is connected to the output terminal of the charge/discharge control unit 2.
The first MOS tube can be switched on and off under the control of the charge and discharge control unit; if the charging and discharging control unit sends a signal for controlling the capacitor corresponding to the flash memory unit to continue to be charged to the first MOS tube according to the monitoring result sent by the detection unit, the first MOS tube continues to be in a starting state, and further continues to charge the capacitor corresponding to the flash memory unit; if the charging and discharging control unit sends a signal for controlling to stop charging the capacitor corresponding to the flash memory unit to the first MOS tube according to the monitoring result sent by the detection unit, the first MOS tube is in a turn-off state, and then the charging of the capacitor corresponding to the flash memory unit is stopped.
The first pole of the second MOS transistor 4 is grounded, the second pole of the second MOS transistor 4 is connected to the input terminal of the capacitor corresponding to each flash memory cell, and the third pole of the second MOS transistor 4 is connected to the output terminal of the charge and discharge control unit.
The second MOS tube can be switched on and off under the control of the charge and discharge control unit; if the charge-discharge control unit sends a signal for controlling the capacitor corresponding to the flash memory unit to continue discharging to the second MOS tube according to the monitoring result sent by the detection unit, the second MOS tube continues to be in a starting state, and further continues to discharge the capacitor corresponding to the flash memory unit; and if the charge-discharge control unit sends a signal for controlling the stop of the discharge processing of the capacitor corresponding to the flash memory unit to the second MOS tube according to the monitoring result sent by the detection unit, the second MOS tube is in a turn-off state, and the discharge operation of the capacitor corresponding to the flash memory unit is further stopped.
The input end of the first detector 11 is connected to the input end of the capacitor corresponding to each flash memory cell, and the output end of the first detector 11 is connected to the input end of the charge and discharge control unit 2.
In the embodiment of the present invention, when the capacitor corresponding to each flash memory cell is precharged or discharged, the capacitor corresponding to each flash memory cell may be monitored in real time by the first detector, and the real-time voltage of the capacitor corresponding to each flash memory cell is determined and sent to the first controller or the second controller. In addition, the first detector is externally connected with an enable signal, and the external enable signal can control the first detector to monitor the capacitor corresponding to each flash memory unit in real time.
In other embodiments of the present invention, an input terminal of the first controller 21 is connected to an output terminal of the first detector 11, and an output terminal of the first controller 21 is connected to a third pole of the first MOS transistor 3;
an input end of the second controller 22 is connected to an output end of the first detector 11, and an output end of the second controller 22 is connected to a third pole of the second MOS transistor 4.
When the capacitor corresponding to the flash memory unit is precharged, the first detector detects real-time voltage of the capacitor corresponding to the flash memory unit and determines the voltage, then the determined voltage value is sent to the first controller, the first controller judges the magnitude relation between the voltage of the capacitor corresponding to the flash memory unit and the first preset threshold voltage, if the voltage of the capacitor corresponding to the flash memory unit is larger than the first preset threshold voltage, the first controller sends a signal for controlling the capacitor corresponding to the flash memory unit to stop charging to the first MOS transistor, and at the moment, the first MOS transistor is in a turn-off state and stops charging the capacitor corresponding to the flash memory unit.
When the capacitor corresponding to the flash memory unit discharges, the first detector detects the real-time voltage of the capacitor corresponding to the flash memory unit and determines the voltage, then the determined voltage value is sent to the second controller, the second controller judges the magnitude relation between the voltage of the capacitor corresponding to the flash memory unit and the second preset threshold voltage, if the voltage of the capacitor corresponding to the flash memory unit is smaller than the second preset threshold voltage, the second controller sends a signal for controlling the capacitor corresponding to the flash memory unit to stop discharging to the second MOS transistor, and at the moment, the second MOS transistor is in a turn-off state so as to stop discharging of the capacitor corresponding to the flash memory unit. Of course, the second control signal may also output indication information for indicating that the discharge of the capacitor is completed.
It should be noted that, if the first controller determines that the voltage of the capacitor corresponding to the flash memory unit is smaller than or equal to the first preset threshold voltage, the first controller may not send the indication signal to the first MOS transistor, and at this time, the first MOS transistor is defaulted to continue to be in the on state and charge the capacitor corresponding to the flash memory unit; if the second controller judges that the voltage of the capacitor corresponding to the flash memory unit is greater than or equal to the second preset threshold voltage, the second controller may not send an indication signal to the second MOS transistor, and at this time, the second MOS transistor is defaulted to continue in the on state and discharge the capacitor corresponding to the flash memory unit.
Based on the foregoing embodiments, in other embodiments of the present invention, bit lines may also be provided at positions connected to a power supply that are symmetrical to the structure shown in fig. 1; at this time, the circuit configuration is as shown in fig. 2, the connection structure of the first MOS transistor, the second MOS transistor, the first detector, the first controller, and the second controller is not changed, but only the position of the bit line is changed.
In one possible implementation, the first pole may be referred to as a source, the second pole may be referred to as a drain, and the third pole may be referred to as a gate.
The embodiment of the invention provides a self-adaptive charge and discharge circuit, which comprises a detection unit and a charge and discharge control unit; the input end of the detection unit is connected with the output end of the capacitor corresponding to each flash memory unit of the storage array, and the output end of the detection unit is connected with the input end of the charge-discharge control unit; the output end of the charge and discharge control unit is connected with the input end of the capacitor corresponding to each flash memory unit, so that the detection unit detects the charge and discharge condition of the capacitor of the bit line and then sends the charge and discharge condition to the charge and discharge control unit, and the charge and discharge control unit can control the charge and discharge condition of the capacitor of the bit line, thereby solving the problem that the charge and discharge method of the capacitor of the bit line in the relative technology has insufficient charge or excessive discharge, avoiding the occurrence of output error data, and improving the accuracy and the working efficiency of the output data.
Based on the foregoing embodiments, an embodiment of the present invention provides an adaptive charging/discharging circuit, which, as shown in fig. 3, includes: detecting element 1, charge-discharge control unit 2, first MOS pipe 3 and second MOS pipe 4, detecting element 1 includes: the second detector 12 and the third detector 13, and the charge and discharge control unit 2 includes: a first controller 21 and a second controller 22, wherein:
the first pole of the first MOS transistor 3 is connected to the power supply, the second pole of the first MOS transistor 3 is connected to the input terminal of the capacitor corresponding to each flash memory cell, and the third pole of the first MOS transistor 3 is connected to the output terminal of the charge/discharge control unit 2.
The first pole of the second MOS transistor 4 is grounded, the second pole of the second MOS transistor 4 is connected to the input terminal of the capacitor corresponding to each flash memory cell, and the third pole of the second MOS transistor 4 is connected to the output terminal of the charge and discharge control unit.
The input end of the second detector 12 is connected to the input end of the capacitor corresponding to each flash memory cell, and the output end of the second detector 12 is connected to the input end of the charge and discharge control unit 2.
The input end of the third detector 13 is connected to the input end of the capacitor corresponding to each flash memory cell, and the output end of the third detector 13 is connected to the input end of the charge and discharge control unit 2.
In the embodiment of the present invention, when the capacitor corresponding to each flash memory cell is precharged, the capacitor corresponding to each flash memory cell may be monitored in real time by the second detector, and the real-time voltage of the capacitor corresponding to each flash memory cell is determined and sent to the first controller; if the capacitor corresponding to each flash memory unit is discharged, the capacitor corresponding to each flash memory unit may be monitored in real time by the third detector, and the real-time voltage of the capacitor corresponding to each flash memory unit is determined and sent to the second controller.
In other embodiments of the present invention, the enable terminal of the third detector 13 is connected to the output terminal of the charge and discharge control unit 2. The enable terminal of the second detector 12 is connected to an external enable signal.
The input end of the first controller 21 is connected with the output end of the second detector 12, and the output end of the first controller 21 is connected with the third pole of the first MOS transistor 3;
an input end of the second controller 22 is connected to an output end of the third detector 13, and an output end of the second controller 22 is connected to a third pole of the second MOS transistor 4.
An output of the first controller 21 is connected to an enable terminal of the third detector 13.
It should be noted that, when the first controller determines that the voltage of the capacitor corresponding to the flash memory cell is greater than the first preset threshold voltage, the first controller may further send an enable signal to the third detector through the enable terminal of the second detector, so as to instruct the third detector to monitor the discharging operation of the capacitor corresponding to each flash memory cell.
The type of the first MOS tube is different from that of the second MOS tube.
In a possible implementation manner, the first MOS transistor may be a P-type MOS transistor, and the second MOS transistor may be an N-type MOS transistor. The first pole may be referred to as a source, the second pole may be referred to as a drain, and the third pole may be referred to as a gate.
The memory array is a three-dimensional NAND-type flash memory array.
Based on the foregoing embodiments, in other embodiments of the present invention, the bit lines may also be disposed at positions connected to the power supply that are symmetrical to the structure shown in fig. 3; at this time, as shown in fig. 4, the circuit configuration is such that the connection structure of the first MOS transistor, the second detector, the third detector, the first controller, and the second controller is not changed, but only the position of the bit line is changed.
It should be noted that, for specific descriptions of related devices and concepts in other embodiments in this embodiment, reference may be made to descriptions in other embodiments, and further description is omitted here.
The embodiment of the invention provides a self-adaptive charge and discharge circuit, which comprises a detection unit and a charge and discharge control unit; the input end of the detection unit is connected with the output end of the capacitor corresponding to each flash memory unit of the storage array, and the output end of the detection unit is connected with the input end of the charge-discharge control unit; the output end of the charge and discharge control unit is connected with the input end of the capacitor corresponding to each flash memory unit, so that the detection unit detects the charge and discharge condition of the capacitor of the bit line and then sends the charge and discharge condition to the charge and discharge control unit, and the charge and discharge control unit can control the charge and discharge condition of the capacitor of the bit line, thereby solving the problem that the charge and discharge method of the capacitor of the bit line in the relative technology has insufficient charge or excessive discharge, avoiding the occurrence of output error data, and improving the accuracy and the working efficiency of the output data.
Based on the foregoing embodiments, an embodiment of the present invention provides an adaptive charging and discharging method, which is shown in fig. 5 and includes the following steps:
When the capacitor corresponding to the flash memory unit of the storage array is precharged, the capacitor can be monitored in real time, and then the voltage of the capacitor is determined in real time to obtain a first voltage value. In one possible implementation, the first voltage value may be a magnitude of a voltage value of the capacitor after the capacitor is charged for a first time period; of course, the first duration may be determined based on actual demand and historical data.
The first preset threshold voltage may be a preset voltage value, and the first preset threshold voltage may be a voltage value corresponding to a capacitor corresponding to the flash memory cell when the capacitor is normally charged and the charging is completed. In one possible implementation, charging complete may refer to no overcharging occurring and the capacitor fully charged.
When the capacitor corresponding to the flash memory unit of the storage array is discharged, the capacitor can be monitored in real time, and then the voltage of the capacitor is determined in real time to obtain a second voltage value. In one possible implementation, the second voltage value may be a magnitude of a voltage value of the capacitor after discharging the capacitor for a second duration; of course, the second period of time may be determined based on actual demand and historical data.
The second preset threshold voltage may be a preset voltage value, and the second preset threshold voltage may be a voltage value corresponding to when the capacitor corresponding to the flash memory cell is normally discharged and the discharge is completed. In one possible implementation, discharge completion may refer to no over-discharge and the capacitor has discharged.
According to the self-adaptive charging and discharging method provided by the embodiment of the invention, when the capacitor corresponding to the flash memory unit is charged and discharged, the voltage of the capacitor corresponding to the flash memory unit can be monitored, and whether the charging and discharging operation is continued or not is controlled based on the voltage of the capacitor corresponding to the flash memory unit, so that the problem that the charging and discharging method of the capacitor of the bit line in the relative technology has insufficient charging or excessive discharging is solved, the output of wrong data is avoided, and the accuracy and the working efficiency of the output data are improved.
Based on the foregoing embodiments, an embodiment of the present invention provides an adaptive charging and discharging method, which is shown in fig. 6 and includes the following steps:
If the first voltage value of the capacitor corresponding to the flash memory unit is greater than the first preset threshold voltage, it indicates that the capacitor corresponding to the flash memory unit has completed normal charging, and at this time, the charging of the capacitor may be stopped.
If the second voltage value of the capacitor corresponding to the flash memory cell is smaller than the second preset threshold voltage, it indicates that the capacitor corresponding to the flash memory cell has completed normal discharge, and at this time, the discharge of the capacitor may be stopped.
In other embodiments of the present invention, step 402 may be followed by the following steps:
and outputting a monitoring instruction for indicating to monitor the discharging operation of the capacitor corresponding to each flash memory unit.
Accordingly, step 403 may be implemented by:
and after the capacitor corresponding to each flash memory unit is discharged, monitoring a second voltage value of the capacitor corresponding to each flash memory unit based on the monitoring instruction.
It should be noted that, for the descriptions of the same steps and the same contents in this embodiment as those in other embodiments, reference may be made to the descriptions in other embodiments, which are not described herein again.
According to the self-adaptive charging and discharging method provided by the embodiment of the invention, when the capacitor corresponding to the flash memory unit is charged and discharged, the voltage of the capacitor corresponding to the flash memory unit can be monitored, and whether the charging and discharging operation is continued or not is controlled based on the voltage of the capacitor corresponding to the flash memory unit, so that the problem that the charging and discharging method of the capacitor of the bit line in the relative technology has insufficient charging or excessive discharging is solved, the output of wrong data is avoided, and the accuracy and the working efficiency of the output data are improved.
Based on the foregoing embodiments, an embodiment of the present invention provides an adaptive charging and discharging device, which may be applied to an adaptive charging and discharging method provided in embodiments corresponding to fig. 4 to 5, and as shown in fig. 7, the device 5 includes: a controller 51 and a processor 52, wherein:
the controller 51 is configured to monitor a first voltage value of a capacitor corresponding to each flash memory cell of the memory array after precharging the capacitor corresponding to each flash memory cell;
the processor 52 is configured to control a charging operation of the capacitor corresponding to each flash memory cell based on a relationship between a first voltage value of the capacitor corresponding to each flash memory cell and a first preset threshold voltage.
In other embodiments of the present invention, processor 52 is further configured to perform the following steps:
and if the capacitor with the first voltage value larger than the first preset threshold voltage exists in the capacitor corresponding to each flash memory unit, controlling the capacitor with the first voltage value larger than the first preset threshold voltage to stop charging.
In other embodiments of the present invention, processor 52 is further configured to perform the following steps:
and outputting a monitoring instruction for indicating to monitor the discharging operation of the capacitor corresponding to each flash memory unit.
In other embodiments of the present invention, the controller 51 is further configured to perform the following steps:
after the capacitor corresponding to each flash memory unit is discharged, monitoring a second voltage value of the capacitor corresponding to each flash memory unit;
the processor 52 is further configured to control a discharging operation of the capacitor corresponding to each flash memory cell based on a relationship between the second voltage value of the capacitor corresponding to each flash memory cell and the second preset threshold voltage.
In other embodiments of the present invention, processor 52 is further configured to perform the following steps:
if the capacitor with the second voltage value smaller than the second preset threshold voltage exists in the capacitor corresponding to each flash memory unit, the capacitor with the second voltage value smaller than the second preset threshold voltage is controlled to stop discharging, and indication information used for indicating that the capacitor with the second voltage value smaller than the second preset threshold voltage finishes discharging is output.
In other embodiments of the present invention, the controller 51 is further configured to monitor the second voltage value of the capacitor corresponding to each flash memory cell based on the monitoring instruction after discharging the capacitor corresponding to each flash memory cell.
The self-adaptive charging and discharging equipment provided by the embodiment of the invention can monitor the voltage of the capacitor corresponding to the flash memory unit when the capacitor corresponding to the flash memory unit is charged and discharged, and control whether to continue charging and discharging operations based on the voltage of the capacitor corresponding to the flash memory unit, thereby solving the problem that the charging and discharging method of the capacitor of the bit line in the relative technology has insufficient charging or excessive discharging, avoiding the occurrence of output wrong data, and improving the accuracy and the working efficiency of the output data.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (such as a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method described in the embodiments of the present invention.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (19)
1. An adaptive charging and discharging circuit, the circuit comprising: the detecting element, charge-discharge control unit and second MOS pipe, wherein:
the input end of the detection unit is connected with the input end of a capacitor corresponding to each flash memory unit of the storage array, and the output end of the detection unit is connected with the input end of the charge and discharge control unit;
the output end of the charge and discharge control unit is connected with the input end of the capacitor corresponding to each flash memory unit;
the detection unit is used for monitoring the voltage of the capacitor corresponding to each flash memory unit when the capacitor corresponding to each flash memory unit is charged and discharged, and sending the monitoring result to the charging and discharging control unit;
the charge and discharge control unit is used for receiving the monitoring result sent by the detection unit and controlling the charge and discharge operation of the capacitor corresponding to each flash memory unit based on the monitoring result;
the first pole of the second MOS tube is used for grounding, the second pole of the second MOS tube is connected with the input end of the capacitor corresponding to each flash memory unit, and the third pole of the second MOS tube is connected with the output end of the charge-discharge control unit;
when the charge and discharge control unit controls the second MOS tube to be in a starting state, the capacitor corresponding to the flash memory unit discharges; and the charge and discharge control unit stops the discharge of the capacitor corresponding to the flash memory unit when controlling the second MOS tube to be in a turn-off state.
2. The circuit of claim 1, further comprising: a first MOS transistor, wherein:
the first pole of the first MOS tube is connected with a power supply, the second pole of the first MOS tube is connected with the input end of the capacitor corresponding to each flash memory unit, and the third pole of the first MOS tube is connected with the output end of the charge-discharge control unit.
3. The circuit of claim 2, wherein the detection unit comprises: a first detector, wherein:
the input end of the first detector is connected with the input end of the capacitor corresponding to each flash memory unit, and the output end of the first detector is connected with the input end of the charge and discharge control unit.
4. The circuit of claim 3, wherein the charge and discharge control unit comprises: a first controller and a second controller, wherein:
the input end of the first controller is connected with the output end of the first detector, and the output end of the first controller is connected with the third pole of the first MOS tube;
the input end of the second controller is connected with the output end of the first detector, and the output end of the second controller is connected with the third pole of the second MOS tube.
5. The circuit of claim 2, wherein the detection unit comprises: a second detector and a third detector, wherein:
the input end of the second detector is connected with the input end of the capacitor corresponding to each flash memory unit, and the output end of the second detector is connected with the input end of the charge and discharge control unit;
the input end of the third detector is connected with the input end of the capacitor corresponding to each flash memory unit, and the output end of the third detector is connected with the input end of the charge and discharge control unit.
6. The circuit of claim 5, wherein an enable terminal of the third detector is connected to an output terminal of the charge and discharge control unit;
and the enabling end of the second detector is connected with an external enabling signal.
7. The circuit of claim 6, wherein the charge and discharge control unit comprises: a first controller and a second controller, wherein:
the input end of the first controller is connected with the output end of the second detector, and the output end of the first controller is connected with the third pole of the first MOS tube;
the input end of the second controller is connected with the output end of the third detector, and the output end of the second controller is connected with the third pole of the second MOS tube.
8. The circuit of claim 7, wherein the output of the first controller is connected to the enable of the third detector.
9. The circuit of claim 2, wherein the first MOS transistor is of a different type than the second MOS transistor.
10. An adaptive charging and discharging device, characterized in that the device comprises: a controller and a processor, wherein:
the controller is used for monitoring a first voltage value of a capacitor corresponding to each flash memory unit after the capacitor corresponding to each flash memory unit of the storage array is precharged;
the processor is used for controlling the charging operation of the capacitor corresponding to each flash memory unit based on the relation between the first voltage value of the capacitor corresponding to each flash memory unit and the first preset threshold voltage;
the processor is further configured to: and if the capacitor with the first voltage value larger than the first preset threshold voltage exists in the capacitor corresponding to each flash memory unit, controlling the capacitor with the first voltage value larger than the first preset threshold voltage to stop charging.
11. The device of claim 10, wherein the processor is further configured to:
and outputting a monitoring instruction for indicating to monitor the discharging operation of the capacitor corresponding to each flash memory unit.
12. The apparatus according to claim 10 or 11,
the controller is further configured to monitor a second voltage value of the capacitor corresponding to each flash memory cell after discharging the capacitor corresponding to each flash memory cell;
the processor is further configured to control a discharging operation of the capacitor corresponding to each flash memory cell based on a relationship between a second voltage value of the capacitor corresponding to each flash memory cell and a second preset threshold voltage.
13. The device of claim 12, wherein the processor is further configured to:
if the capacitor with the second voltage value smaller than the second preset threshold voltage exists in the capacitor corresponding to each flash memory unit, the capacitor with the second voltage value smaller than the second preset threshold voltage is controlled to stop discharging, and indication information used for indicating that the capacitor with the second voltage value smaller than the second preset threshold voltage is discharged is output.
14. The apparatus of claim 12,
the processor is further configured to: outputting a monitoring instruction for indicating to monitor the discharging operation of the capacitor corresponding to each flash memory unit;
the controller is further configured to:
and after the capacitor corresponding to each flash memory unit is discharged, monitoring a second voltage value of the capacitor corresponding to each flash memory unit based on the monitoring instruction.
15. An adaptive charging and discharging method, characterized in that the method comprises:
after a capacitor corresponding to each flash memory unit of a storage array is precharged, monitoring a first voltage value of the capacitor corresponding to each flash memory unit;
and if the capacitor with the first voltage value larger than the first preset threshold voltage exists in the capacitor corresponding to each flash memory unit, controlling the capacitor with the first voltage value larger than the first preset threshold voltage to stop charging.
16. The method of claim 15, wherein if a capacitor having a first voltage value greater than a first predetermined threshold voltage exists in the capacitor corresponding to each flash memory cell, controlling the capacitor having the first voltage value greater than the first predetermined threshold voltage to stop charging further comprises:
and outputting a monitoring instruction for indicating to monitor the discharging operation of the capacitor corresponding to each flash memory unit.
17. The method according to claim 15 or 16, characterized in that the method further comprises:
after the capacitor corresponding to each flash memory unit is discharged, monitoring a second voltage value of the capacitor corresponding to each flash memory unit;
and controlling the discharging operation of the capacitor corresponding to each flash memory unit based on the relation between the second voltage value of the capacitor corresponding to each flash memory unit and the second preset threshold voltage.
18. The method of claim 17, wherein the controlling the discharging operation of the capacitor corresponding to each flash memory cell based on the relationship between the second voltage value of the capacitor corresponding to each flash memory cell and the second predetermined threshold voltage comprises:
if the capacitor with the second voltage value smaller than the second preset threshold voltage exists in the capacitor corresponding to each flash memory unit, the capacitor with the second voltage value smaller than the second preset threshold voltage is controlled to stop discharging, and indication information used for indicating that the capacitor with the second voltage value smaller than the second preset threshold voltage is discharged is output.
19. The method of claim 17,
if a capacitor with a first voltage value larger than a first preset threshold voltage exists in the capacitor corresponding to each flash memory unit, after the capacitor with the first voltage value larger than the first preset threshold voltage is controlled to stop charging, the method further includes: outputting a monitoring instruction for indicating to monitor the discharging operation of the capacitor corresponding to each flash memory unit;
after the capacitor corresponding to each flash memory cell is discharged, monitoring a second voltage value of the capacitor corresponding to each flash memory cell, including:
and after the capacitor corresponding to each flash memory unit is discharged, monitoring a second voltage value of the capacitor corresponding to each flash memory unit based on the monitoring instruction.
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