CN109830796A

CN109830796A - A kind of antenna based on CMOS technology

Info

Publication number: CN109830796A
Application number: CN201910247016.5A
Authority: CN
Inventors: 周杨; 李旺; 张根烜; 段宗明; 吴博文
Original assignee: CETC 38 Research Institute
Current assignee: CETC 38 Research Institute
Priority date: 2019-03-29
Filing date: 2019-03-29
Publication date: 2019-05-31

Abstract

The invention discloses an antenna based on CMOS technology, comprising a substrate, a dielectric layer and a metal layer. The upper surface of the substrate is provided with a dielectric layer, and the upper surface of the dielectric layer is provided with a metal layer; the metal layer It includes a patch, a microstrip line, a transition mechanism and a coplanar waveguide mechanism. The patch is arranged at the center of the dielectric layer. One end of the microstrip line is connected to one side of the patch, and the other end is connected to the coplanar through the transition mechanism. A waveguide mechanism, the coplanar waveguide mechanism is arranged at one end of the dielectric layer. The advantages of the invention are that integrating the antenna on the chip is more conducive to the miniaturization and high-density integration of the overall system, and it is also convenient for the antenna to be matched and interconnected with the chip or other devices, reducing the loss of interconnection with other circuits and devices. Good performance and low cost.

Description

A kind of antenna based on CMOS technology

Technical field

The present invention relates to wireless communication technique field, specially a kind of antenna based on CMOS technology.

Background technique

CMOS (Complementary Metal Oxide Semiconductor), complementary metal oxide semiconductor, electricity A kind of amplifying device of voltage-controlled system is the basic unit for forming cmos digital integrated circuit.

Wireless communication technique is that the characteristic that can be propagated in free space using electromagnetic wave signal carries out information exchange A kind of communication modes, with the continuous development of wireless communication technique, to the system integration propose small size, low cost, high-performance, Highly integrated equal more challenges and requirement.Wireless telecommunication system is all to carry out electromagnetic wave by antenna to transmit information, thus antenna Passive device as large area is to the performance of System all-in-one Integration and integrated level important in inhibiting.And the day of tradition preparation Line can only separately be connect with chip, cannot be integrated, and consistency is poor, and volume is big, and when antenna is connect with other integrated circuits Difficulty of matching is big.

Summary of the invention

Technical problem to be solved by the present invention lies in: the antenna of tradition preparation can only separately be connect with chip, Bu Nengji At consistency is poor, and volume is big, and difficulty of matching is big when antenna is connect with other integrated circuits.

In order to solve the above technical problems, the invention provides the following technical scheme:

A kind of antenna based on CMOS technology, including substrate, dielectric layer and metal layer, the upper surface of the substrate, which is equipped with, to be situated between The upper surface of matter layer, the dielectric layer is equipped with metal layer.

The metal layer includes patch, microstrip line, transition mechanism and co-planar waveguide mechanism, and the patch is arranged in dielectric layer Center, the microstrip line one end connection patch side, the other end by transition mechanism connection co-planar waveguide mechanism, One end of dielectric layer is arranged in the co-planar waveguide mechanism.

Preferably, CMOS technology uses CMOS 65nm technique.

Preferably, CMOS technology specific work steps is as follows:

Step 1: in the upper surface coated media layer of substrate；

Step 2: the deposited metal layer on dielectric layer.

Preferably, the co-planar waveguide mechanism is symmetrical co-planar waveguide mechanism, including center band and counterpoise grounding, the center Band connection transition mechanism, the counterpoise grounding are symmetricly set on the two sides of center band, have gap between the center band and counterpoise grounding.

Preferably, the microstrip line and co-planar waveguide mechanism are planar transmission line.

Preferably, the patch is square shape or E shape.

Preferably, the patch is E shape.

Preferably, the substrate is CMOS silicon substrate.

Preferably, the metal layer is deposited on dielectric layer by disposable plane photoetching and electroplating technology.

Compared with prior art, the beneficial effects of the present invention are:

1, it realizes that antenna integrates on the chip of W-waveband by using CMOS 65nm technique, antenna is integrated on chip It is more advantageous to miniaturization, the High Density Integration of total system, moreover it is possible to reduce circuit or the damage of device connection between antenna and chip Consumption,.

2, by disposable plane photoetching and electroplating technology deposited metal layer, convenient for the antenna and chip or other devices into Row matching interconnection, consistency is good, low in cost.

Detailed description of the invention

Fig. 1 is a kind of perspective view of the antenna based on CMOS technology of the embodiment of the present invention；

Fig. 2 is the left view of co-planar waveguide of embodiment of the present invention mechanism；

The simulation result diagram of Fig. 3 is the embodiment of the present invention when being E shape patch return loss S11；

The simulation result diagram of Fig. 4 is the embodiment of the present invention when being E shape patch voltage standing wave ratio VSWR.

Specific embodiment

For convenient for those skilled in the art understand that technical solution of the present invention, now in conjunction with Figure of description to the technology of the present invention side Case is described further.

In this application unless specifically defined or limited otherwise, term " installation ", " connected ", " connection ", " fixation " etc. Term shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or integral；It can be mechanical connect It connects, is also possible to be electrically connected, can also be communication；It can be directly connected, can also indirectly connected through an intermediary, it can be with It is the interaction relationship of the connection or two elements inside two elements.For the ordinary skill in the art, may be used To understand the concrete meaning of above-mentioned term in this application as the case may be.

Refering to fig. 1 to Fig. 2, present embodiment discloses a kind of antennas based on CMOS technology, including substrate 1,2 and of dielectric layer Metal layer 3, in the present embodiment, the substrate 1 are CMOS silicon substrate, with a thickness of 370 μm, but are not limited only to the thickness, can root According to actual demand, its thickness is set；The upper surface of the substrate 1 is coated with dielectric layer 2, and the upper surface of the dielectric layer 2 passes through one Secondary mild-natured face photoetching and electroplating technology deposited metal layer 3.

Specifically, CMOS technology antenna Step is as follows:

Step 1: in the upper surface coated media layer 2 of substrate 1；

Step 2: the deposited metal layer 3 on dielectric layer 2.

In the present embodiment, which uses CMOS 65nm technique using CMOS technology, then corresponding CMOS technology antenna It needs 9 layers of metal, i.e., coats first medium layer in the upper surface of substrate 1, deposit the first metal layer on first medium layer, the One metal coats second metal layer in second dielectric layer, repeats the above steps at upper coating second dielectric layer, until the 9th The 9th metal layer is coated on dielectric layer, then completes the CMOS 65nm process flow.

The frequency of the chip of traditional W-waveband is generally in 75-110GHz, other CMOS technologies, such as 0.13 μm of CMOS The cutoff frequency of 0.18 μm of technique of technique and CMOS is all the frequency requirement that W-waveband is not achieved, that is, is unable to satisfy the electricity of W-waveband Road requires, and the cutoff frequency of CMOS 65nm technique MOSFET can reach 200GHz, and antenna may be implemented completely in W-waveband It is integrated on chip, antenna is integrated in the miniaturization for being more advantageous to total system on chip, High Density Integration, moreover it is possible to reduce antenna The loss that circuit or device are connect between chip, in addition, by disposable plane photoetching and electroplating technology deposited metal layer 3, Matching interconnection is carried out convenient for the antenna and chip or other devices, consistency is good, low in cost.

The metal layer 3 includes patch 31, microstrip line 32, transition mechanism 33 and co-planar waveguide mechanism 34, the patch 31 The center of dielectric layer 2 is set, and the transition mechanism 33 is trapezoidal shape structure, and the co-planar waveguide mechanism 34 is symmetrical total Surface wave leads mechanism, and co-planar waveguide mechanism 34 includes center band 341 and counterpoise grounding 342, and the counterpoise grounding 342 is symmetricly set on center With 341 two sides, there is gap between the center band 341 and counterpoise grounding 342, the conduction for electromagnetic wave；The microstrip line 32 Right end connection patch 31 left side, microstrip line 32 left end connection trapezoidal transition mechanism 33 long side, trapezoidal transition mechanism 33 Short side connection center band 341 right end, and guarantee between having between the two sides bevel edge of trapezoidal transition mechanism 33 and counterpoise grounding 342 Gap is symmetrically recessed the trapezoidal shape of indent in the present embodiment between two counterpoise groundings 342, form gap with transition mechanism 33, Short circuit is caused to prevent from connecting with counterpoise grounding 342.

The microstrip line 32 and co-planar waveguide mechanism 34 are planar transmission line, easily designed and processing, when frequency range arrives The advantage of millimere-wave band, co-planar waveguide mechanism 34 is more prominent, the two combine it is more convenient realize with other active, passive devices with And circuit interconnection.

Further, the patch is square shape or E shape, and in the present embodiment, which is E shape, refering to Fig. 3 The simulation result of return loss S11 and voltage standing wave ratio VSWR when to Fig. 4, respectively E shape patch, as can be seen from the figure accord with Requirement of the conjunction to antenna S parameter, i.e. resistance matching is good, further to guarantee that antenna be with chip or the progress of other devices With interconnection.

It is obvious to a person skilled in the art that invention is not limited to the details of the above exemplary embodiments, Er Qie In the case where without departing substantially from spirit or essential attributes of the invention, the present invention can be realized in other specific forms.Therefore, no matter From the point of view of which point, the present embodiments are to be considered as illustrative and not restrictive, and the scope of the present invention is by appended power Benefit requires rather than above description limits, it is intended that all by what is fallen within the meaning and scope of the equivalent elements of the claims Variation is included within the present invention, and any reference signs in the claims should not be construed as limiting the involved claims.

Embodiment described above only indicates that the embodiment of invention, protection scope of the present invention are not only limited to above-mentioned implementation Example without departing from the inventive concept of the premise, can also make several deformations and change for those skilled in the art Into these belong to the scope of the present invention.

Claims

1. An antenna based on CMOS technology, characterized in that: comprising a substrate, a dielectric layer and a metal layer, the upper surface of the substrate is provided with a dielectric layer, and the upper surface of the dielectric layer is provided with a metal layer;

The metal layer includes a patch, a microstrip line, a transition mechanism and a coplanar waveguide mechanism, the patch is arranged at the center of the dielectric layer, one end of the microstrip line is connected to one side of the patch, and the other end passes through the transition The mechanism is connected to the coplanar waveguide mechanism, and the coplanar waveguide mechanism is arranged at one end of the dielectric layer.

2 . The antenna based on a CMOS process according to claim 1 , wherein the CMOS process adopts a CMOS 65nm process. 3 .

3. a kind of antenna based on CMOS technology according to claim 1, is characterized in that: CMOS technology concrete working steps are as follows:

Step 1: Coating a dielectric layer on the upper surface of the substrate;

Step 2: Deposit a metal layer on the dielectric layer.

4 . The antenna based on CMOS process according to claim 1 , wherein the coplanar waveguide mechanism is a symmetrical coplanar waveguide mechanism, comprising a center strip and a ground strip, the center strip is connected to the transition mechanism, and the The ground straps are symmetrically arranged on both sides of the center strap, and there is a gap between the center strap and the ground strap.

5 . The CMOS-based antenna according to claim 1 , wherein the microstrip line and the coplanar waveguide mechanism are both planar transmission lines. 6 .

6 . The antenna based on CMOS technology according to claim 1 , wherein the patch is in a square shape. 7 .

7 . The antenna based on CMOS process according to claim 1 , wherein the patch is E-shaped. 8 .

8. The antenna based on a CMOS process according to claim 1, wherein the substrate is a CMOS silicon substrate.

9 . The antenna based on CMOS process according to claim 1 , wherein the metal layer is deposited on the dielectric layer by a one-time planar photolithography and electroplating process. 10 .