CN109841256B - Flash memory reference circuit - Google Patents
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- CN109841256B CN109841256B CN201711230684.4A CN201711230684A CN109841256B CN 109841256 B CN109841256 B CN 109841256B CN 201711230684 A CN201711230684 A CN 201711230684A CN 109841256 B CN109841256 B CN 109841256B
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Abstract
The invention discloses a flash memory reference circuit, comprising: the positive temperature coefficient current module is used for generating a first current, and the first current is a positive temperature coefficient current; the negative temperature coefficient current module is used for generating a second current, and the second current is a negative temperature coefficient current; the first end of the control module is electrically connected with the first end of the positive temperature coefficient current module, the second end of the control module is electrically connected with the first end of the negative temperature coefficient current module, the third end of the control module is electrically connected with the second end of the negative temperature coefficient current module, the control module is used for generating reference current according to the first current and the second current and outputting the reference current from the fourth end of the control module, and the temperature coefficient of the reference current is positive temperature coefficient, negative temperature coefficient or zero temperature coefficient. The embodiment of the invention provides a flash memory reference circuit, which obtains reference currents with different temperature coefficients through a positive temperature coefficient current module, a negative temperature coefficient current module and a control module.
Description
Technical Field
The embodiment of the invention relates to the technical field of nonvolatile memories, in particular to a flash memory reference circuit.
Background
With the development of consumer electronics market, flash memory has been widely used as a main memory in products such as mobile phones and digital cameras, and the market scale is continuously expanding.
In the read operation in the prior art, a certain voltage is applied to the gate and a certain voltage is applied to the drain of a memory cell to be read, and then the drain current of the memory cell is compared with the reference current generated by the reference circuit, so that the programmed state and the erased state of the memory cell are obtained. However, in the prior art, due to factors such as temperature or differences between devices included in the read circuit and the reference circuit, the temperature coefficient of the reference current generated by the reference circuit and the temperature coefficient of the drain current read by the memory cell are not matched, so that during reading operation, the drain current of the memory cell is compared with the reference current generated by the reference circuit, and the obtained programmed state and the erased state of the memory cell are also deviated from the actual state of the memory cell.
There is a need for a reference circuit that can generate reference currents with different temperature coefficients, such as a positive temperature coefficient reference current, a negative temperature coefficient reference current, and a zero temperature coefficient reference current, and that can generate reference currents with different temperature coefficients to match the temperature coefficient of the drain current read by the memory cell, so that the reading operation of the memory cell is more accurate.
Disclosure of Invention
Embodiments of the present invention provide a flash memory reference circuit, which can obtain reference currents with different temperature coefficients, so that the temperature coefficient of the reference current and the temperature coefficient of the read current can be consistent when a memory cell is read.
The embodiment of the invention provides a flash memory reference circuit, which comprises a positive temperature coefficient current module, a reference circuit and a control circuit, wherein the positive temperature coefficient current module is used for generating a first current, and the first current is a positive temperature coefficient current;
a negative temperature coefficient current module for generating a second current, the second current being a negative temperature coefficient current;
the first end of the control module is electrically connected with the first end of the positive temperature coefficient current module, the second end of the control module is electrically connected with the first end of the negative temperature coefficient current module, the third end of the control module is electrically connected with the second end of the negative temperature coefficient current module, the control module is used for generating reference current according to the first current and the second current and outputting the reference current through the fourth end of the control module, and the temperature coefficient of the reference current is positive temperature coefficient, negative temperature coefficient or zero temperature coefficient.
Optionally, the control module includes a first current mirror unit, a second current mirror unit, a third current mirror unit, and an arithmetic unit;
the first current mirror unit comprises a first PMOS tube and a second PMOS tube;
the second current mirror unit comprises a third PMOS tube and a fourth PMOS tube;
the third current mirror unit comprises the first PMOS tube and a fifth PMOS tube;
the arithmetic unit comprises the fourth PMOS tube and the fifth PMOS tube;
the grid electrode of the first PMOS tube is electrically connected with the grid electrode of the second PMOS tube;
the grid electrode of the third PMOS tube is electrically connected with the grid electrode of the fourth PMOS tube;
the grid electrode of the first PMOS tube is electrically connected with the grid electrode of the fifth PMOS tube;
the source electrode of the first PMOS tube, the source electrode of the second PMOS tube, the source electrode of the third PMOS tube, the source electrode of the fourth PMOS tube and the source electrode of the fifth PMOS tube are respectively electrically connected with a first power supply;
the drain electrode of the first PMOS tube is used as the first end of the control module and is electrically connected with the first end of the positive temperature coefficient current module;
the drain electrode of the second PMOS tube is used as a second end of the control module and is electrically connected with the first end of the negative temperature coefficient current module;
the drain electrode of the third PMOS tube is used as a third end of the control module and is electrically connected with the second end of the negative temperature coefficient current module;
the drain electrode of the fourth PMOS tube is electrically connected with the drain electrode of the fifth PMOS tube, and the fourth PMOS tube is used as the fourth end of the control module and is used for outputting the reference current;
the ratio of the width-length ratio corresponding to the channel of the fifth PMOS tube to the width-length ratio corresponding to the channel of the first PMOS tube is a first weight value;
the ratio of the width-length ratio corresponding to the channel of the fourth PMOS tube to the width-length ratio corresponding to the channel of the third PMOS tube is a second weighted value;
the reference current is a sum of a product of the first current and the first weight value and a product of the second current and the second weight value.
Optionally, the positive temperature coefficient current module includes a first resistor and a first NMOS transistor;
the drain electrode of the first NMOS tube is electrically connected with the drain electrode and the grid electrode of the first PMOS tube respectively;
the source electrode of the first NMOS tube is electrically connected with the first end of the first resistor;
the second end of the first resistor is grounded;
the grid electrode of the first NMOS tube is electrically connected with a reference voltage source, the reference voltage source is a zero temperature coefficient voltage source, and the reference voltage provided by the reference voltage source enables the first NMOS tube to be in a sub-threshold region.
Optionally, the negative temperature coefficient current module includes a second NMOS transistor, a third NMOS transistor, and a second resistor;
the source electrode of the second NMOS tube is grounded, and the drain electrode of the second NMOS tube is electrically connected with the drain electrode of the second PMOS tube and the grid electrode of the third NMOS tube respectively;
the drain electrode of the third NMOS tube is electrically connected with the grid electrode and the drain electrode of the third PMOS tube respectively;
the source electrode of the third NMOS tube is electrically connected with the grid electrode of the second NMOS tube and the first end of the second resistor respectively;
the second end of the second resistor is grounded;
the third NMOS tube is in a saturation region.
Optionally, the length corresponding to the channel of the first PMOS transistor is equal to the length corresponding to the channel of the fifth PMOS transistor;
the length corresponding to the channel of the third PMOS tube is equal to the length corresponding to the channel of the fourth PMOS tube;
the ratio of the threshold voltage of the first NMOS tube to the resistance value of the first resistor is a third current;
the ratio of the threshold voltage of the second NMOS tube to the resistance value of the second resistor is a fourth current;
a product of the third current and the first weight value is equal to a product of the fourth current and the second weight value;
the temperature coefficient of the reference current is a zero temperature coefficient.
Optionally, the length corresponding to the channel of the first PMOS transistor is equal to the length corresponding to the channel of the fifth PMOS transistor;
the length corresponding to the channel of the third PMOS tube is equal to the length corresponding to the channel of the fourth PMOS tube;
the ratio of the threshold voltage of the first NMOS tube to the resistance value of the first resistor is a third current;
the ratio of the threshold voltage of the second NMOS tube to the resistance value of the second resistor is a fourth current;
a product of the third current and the first weight value is greater than a product of the fourth current and the second weight value;
the temperature coefficient of the reference current is a positive temperature coefficient.
Optionally, the length corresponding to the channel of the first PMOS transistor is equal to the length corresponding to the channel of the fifth PMOS transistor;
the length corresponding to the channel of the third PMOS tube is equal to the length corresponding to the channel of the fourth PMOS tube;
the ratio of the threshold voltage of the first NMOS tube to the resistance value of the first resistor is a third current;
the ratio of the threshold voltage of the second NMOS tube to the resistance value of the second resistor is a fourth current;
a product of the third current and the first weight value is smaller than a product of the fourth current and the second weight value;
the temperature coefficient of the reference current is a negative temperature coefficient.
The flash memory reference circuit provided by the technical scheme of the embodiment of the invention comprises a positive temperature coefficient current module, a negative temperature coefficient current module and a control module, wherein a first current is generated by the positive temperature coefficient current module, the first current is a positive temperature coefficient current, the negative temperature coefficient current module is used for generating a second current, the second current is a negative temperature coefficient current, the control module is used for generating reference currents with different temperature coefficients according to the first current and the second current, and the temperature coefficient of the reference current is a positive temperature coefficient, a negative temperature coefficient or a zero temperature coefficient. The problem that in the prior art, due to the fact that temperature or devices included in a reading circuit and a reference circuit are different and the like, the temperature coefficient of reference current generated by the reference circuit is not matched with the temperature coefficient of drain current read by a storage unit, when reading operation is conducted, the drain current of the storage unit is compared with the reference current generated by the reference circuit, and the fact that the programming state and the erasing state of the storage unit are deviated from the actual state of the storage unit is solved.
Drawings
Fig. 1 is a schematic structural diagram of a flash memory reference circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a flash memory reference circuit according to a second embodiment of the present invention;
fig. 3 is a schematic structural diagram of another flash memory reference circuit according to a second embodiment of the present invention;
fig. 4 is a schematic structural diagram of another flash memory reference circuit according to a second embodiment of the present invention;
fig. 5 is a schematic structural diagram of another flash memory reference circuit according to a second embodiment of the present invention;
FIG. 6 is a schematic diagram of a flash read circuit in the prior art.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Example one
Fig. 1 is a flash memory reference circuit according to an embodiment of the present invention, which includes: the ptc current module 100, the ptc current module 100 is configured to generate a first current, and the first current is a ptc current. The negative temperature coefficient current module 200, the negative temperature coefficient current module 200 is configured to generate a second current, which is a negative temperature coefficient current. The control module 300 is configured to, a first end of the control module 300 is electrically connected to a first end of the positive temperature coefficient current module 100, a second end of the control module 300 is electrically connected to a first end of the negative temperature coefficient current module 200, a third end of the control module 300 is electrically connected to a second end of the negative temperature coefficient current module 200, the control module 300 is configured to generate a reference current according to the first current and the second current and output the reference current by a fourth end of the control module 300, and a temperature coefficient of the reference current is a positive temperature coefficient, a negative temperature coefficient or a zero temperature coefficient.
The temperature coefficient is the rate at which the physical properties of a material change with temperature. The temperature coefficient (temperature coefficient) refers to a relative change of a specific physical quantity when the temperature changes by 1K.
In the present embodiment, the positive temperature coefficient current means that the value of the current increases with the increase of the temperature; negative temperature coefficient current means that the magnitude of the current decreases with increasing temperature; the zero temperature coefficient current means that the value of the current is substantially constant with temperature.
Illustratively, the first current is a positive temperature coefficient current, and then the value of the first current increases with increasing temperature, and the second current is a negative temperature coefficient current, and then the value of the second current decreases with increasing temperature. After the first current and the second current are processed by the control module, a reference current can be obtained, and the reference circuit in this embodiment can generate reference currents with different temperature coefficients. After the control module processes the first current and the second current, for example, the reference currents with different temperature coefficients may be generated by adjusting a ratio of the first current and the second current in the reference currents.
The flash memory reference circuit provided by the technical scheme of the embodiment of the invention comprises a positive temperature coefficient current module, a negative temperature coefficient current module and a control module, wherein a first current is generated by the positive temperature coefficient current module, the first current is a positive temperature coefficient current, the negative temperature coefficient current module is used for generating a second current, the second current is a negative temperature coefficient current, the control module is used for generating reference currents with different temperature coefficients according to the first current and the second current, and the temperature coefficient of the reference current is a positive temperature coefficient, a negative temperature coefficient or a zero temperature coefficient. The problem that in the prior art, due to the fact that temperature or devices included in a reading circuit and a reference circuit are different and the like, the temperature coefficient of reference current generated by the reference circuit is not matched with the temperature coefficient of drain current read by a storage unit, when reading operation is conducted, the drain current of the storage unit is compared with the reference current generated by the reference circuit, and the fact that the programming state and the erasing state of the storage unit are deviated from the actual state of the storage unit is solved.
Example two
On the basis of the above embodiments, the embodiments of the present invention further limit the devices and connection relationships included in the control module 300, the positive temperature coefficient current module 100, and the negative temperature coefficient current module 200 in the reference circuit. Fig. 2 shows a reference circuit provided in this embodiment.
The control module 300 includes a first current mirror unit 301, a second current mirror unit 302, a third current mirror unit 303, and an operation unit 304.
The mirror image unit comprises a mirror image circuit, the mirror image circuit is generally built by a separator, mainly comprises a triode or an MOS tube, the output is mainly current, the output of the mirror image current is constant, and the mirror image current is generally used for a current source.
Referring to fig. 3, optionally, the first current mirror unit 301 includes a first PMOS transistor 3011 and a second PMOS transistor 3012. The second current mirror unit 302 includes a third PMOS transistor 3021 and a fourth PMOS transistor 3022. The third current mirror unit 303 includes a first PMOS transistor 3011 and a fifth PMOS transistor 3031. The operation unit 304 comprises a fourth PMOS transistor 3032 and a fifth PMOS transistor 3031; the gate of the first PMOS transistor 3011 and the gate of the second PMOS transistor 3012 are electrically connected, in fig. 3 and 4, to Vptat; the gate of the third PMOS transistor 3021 and the gate of the fourth PMOS transistor 3022 are electrically connected, and in fig. 3 and 4, are electrically connected to Vctat; the grid electrode of the first PMOS tube 3011 and the grid electrode of the fifth PMOS tube 3031 are electrically connected, and are electrically connected to Vptat in both the graph of FIG. 3 and the graph of FIG. 4; the source electrode of the first PMOS transistor 3011, the source electrode of the second PMOS transistor 3012, the source electrode of the third PMOS transistor 3021, the source electrode of the fourth PMOS transistor 3022, and the source electrode of the fifth PMOS transistor 3031 are electrically connected to the first power supply 400, respectively; the drain of the first PMOS transistor 3011 is used as the first end of the control module 300 and is electrically connected to the first end of the ptc current module 100; the drain of the second PMOS transistor 3012 is used as the second end of the control module 300 and is electrically connected to the first end of the negative temperature coefficient current module 200; the drain of the third PMOS transistor 3021 is used as the third end of the control module and is electrically connected to the second end of the negative temperature coefficient current module 200; the drain electrode of the fourth PMOS transistor 3022 is electrically connected to the drain electrode of the fifth PMOS transistor 3031, and serves as the fourth end of the control module, and is configured to output a reference current (Iref); the ratio of the width-length ratio corresponding to the channel of the fifth PMOS tube 3031 to the width-length ratio corresponding to the channel of the first PMOS tube 3011 is a first weight value; the ratio of the width-to-length ratio corresponding to the channel of the fourth PMOS pipe 3022 to the width-to-length ratio corresponding to the channel of the third PMOS pipe 3021 is a second weight value; the reference current is the sum of a product of the first current and a first weight value and a product of the second current and a second weight value.
Since the reference current is the sum of the product of the first current and the first weight value and the product of the second current and the second weight value. When any one of the first current, the first weight value, the second current and the second weight value is changed, the value of the reference current and the temperature coefficient may be affected. The case where the temperature coefficient of the reference current is zero temperature coefficient, positive temperature coefficient, and negative temperature coefficient will be described below, respectively. Before that, the positive temperature coefficient current module and the negative temperature coefficient current module are further limited.
Optionally, referring to fig. 4, the ptc current module 100 includes a first resistor 101 and a first NMOS transistor 102; the drain electrode of the first NMOS tube 102 is electrically connected to the drain electrode and the gate electrode of the first PMOS tube 3011, respectively; the source electrode of the first NMOS tube 102 is electrically connected with the first end of the first resistor 101; the second end of the first resistor 101 is grounded; the grid electrode of the first NMOS tube 102 is electrically connected with a reference voltage source 103, the reference voltage source 103 is a zero temperature coefficient voltage source, and the first NMOS tube is enabled to work in a sub-threshold region by designing the size of the first NMOS tube.
Taking an NMOS transistor as an example, the threshold voltage (Vth) is 0.7V, and the subthreshold region is a region where an inversion layer is formed in the mos transistor channel but a strong inversion layer is not formed yet, that is, when the applied gate-source voltage Vgs < Vth,
in this embodiment, the ratio between the value obtained by subtracting the threshold voltage (Vth) of the first NMOS transistor from the reference voltage (Vbg) provided by the reference voltage source 103 and the first resistor 101 is the value of the first current. Since the reference voltage (Vbg) provided by the reference voltage source 103 has a zero temperature coefficient voltage, the threshold voltage (Vth) of the first NMOS transistor is a negative temperature coefficient voltage, and the temperature characteristic of the first resistor 101 with respect to the threshold voltage of the first NMOS transistor is negligible, the first current is a positive temperature coefficient current, and is represented by Iptat in fig. 4.
Optionally, referring to fig. 4, the negative temperature coefficient current module 200 includes a second NMOS transistor 201, a third NMOS transistor 202, and a second resistor 203; the source electrode of the second NMOS transistor 201 is grounded, and the drain electrode of the second NMOS transistor 201 is electrically connected to the drain electrode of the second PMOS transistor 3012 and the gate electrode of the third NMOS transistor 3021, respectively; the drain electrode of the third NMOS transistor 202 is electrically connected to the gate electrode and the drain electrode of the third PMOS transistor 3021, respectively; the source electrode of the third NMOS transistor 202 is electrically connected to the gate electrode of the second NMOS transistor 201 and the first end of the second resistor 203, respectively; the second end of the second resistor 203 is grounded; the third NMOS transistor 202 is in the saturation region.
In this embodiment, the gate-source voltage of the second NMOS transistor is about the threshold voltage of the second NMOS transistor. The ratio of the threshold voltage (Vth) of the second NMOS transistor 201 to the second resistor 203 is the value of the second current. The threshold voltage (Vth) of the second NMOS transistor 201 is a voltage with a negative temperature coefficient, and the temperature characteristic of the second resistor 101 with respect to the threshold voltage of the first NMOS transistor is negligible, so the second current is a current with a negative temperature coefficient. The second current is represented in fig. 4 by Ictat.
Optionally, on the basis of the above technical solution, the length corresponding to the channel of the first PMOS transistor is equal to the length corresponding to the channel of the fifth PMOS transistor; the length corresponding to the channel of the third PMOS tube is equal to the length corresponding to the channel of the fourth PMOS tube; the ratio of the threshold voltage of the first NMOS tube to the resistance value of the first resistor is a third current; the ratio of the threshold voltage of the second NMOS tube to the resistance value of the second resistor is a fourth current; when the product of the third current and the first weighted value is equal to the product of the fourth current and the second weighted value, the temperature coefficient of the reference current is zero. When the product of the third current and the first weighted value is larger than the product of the fourth current and the second weighted value, the temperature coefficient of the reference current is a positive temperature coefficient. When the product of the third current and the first weighted value is smaller than the product of the fourth current and the second weighted value, the temperature coefficient of the reference current is a negative temperature coefficient.
Illustratively, the length corresponding to the channel of the first PMOS transistor 3011 is equal to the length corresponding to the channel of the fifth PMOS transistor 3031; the width corresponding to the channel of the first PMOS transistor 3011 is equal to the width corresponding to the channel of the fifth PMOS transistor 3031; the length corresponding to the channel of the third PMOS pipe 3021 is equal to the length corresponding to the channel of the fourth PMOS pipe 3022, and the width corresponding to the channel of the third PMOS pipe 3021 is equal to the width corresponding to the channel of the fourth PMOS pipe 3022; the ratio (third current) between the threshold voltage of the first NMOS transistor 102 and the resistance of the first resistor and the ratio (fourth current) between the threshold voltage of the second NMOS transistor 201 and the resistance of the second resistor can be made equal by adjusting the resistance of the first resistor and the second resistor; the temperature coefficient of the reference current is zero. The length corresponding to the channel of the first PMOS tube is equal to the length corresponding to the channel of the fifth PMOS tube; the width corresponding to the channel of the first PMOS tube is equal to the width corresponding to the channel of the fifth PMOS tube, namely, the first current passes through the first PMOS tube and is mirrored to the fifth PMOS tube, and the current flowing out of the drain electrode of the fifth PMOS tube is equal to the value of the first current, namely, the first weight value is 1. Similarly, the current flowing out of the drain electrode of the fourth PMOS transistor is equal to the second current in value, and the second weighted value is 1.
The ratio (third current) between the threshold voltage of the first NMOS transistor 102 and the resistance of the first resistor is equal to the ratio (fourth current) between the threshold voltage of the second NMOS transistor 201 and the resistance of the second resistor, so that the current flowing out of the drains of the fourth PMOS transistor 3022 and the fifth PMOS transistor 3031 of the arithmetic unit is the reference voltage Vbg and the first resistor ratio.
Optionally, on the basis of the above technical solution, the length corresponding to the channel of the first PMOS transistor 3011 is equal to the length corresponding to the channel of the fifth PMOS transistor 3031; the ratio of the width corresponding to the channel of the first PMOS pipe 3011 to the width corresponding to the channel of the fifth PMOS pipe 3031 is greater than the ratio of the width corresponding to the channel of the third PMOS pipe 3021 to the width corresponding to the channel of the fourth PMOS pipe 3022; the ratio (third current) between the threshold voltage of the first NMOS transistor 102 and the resistance of the first resistor is equal to the ratio (fourth current) between the threshold voltage of the second NMOS transistor 201 and the resistance of the second resistor; the temperature coefficient of the reference current is a positive temperature coefficient. The length corresponding to the channel of the first PMOS transistor 3011 is equal to the length corresponding to the channel of the fifth PMOS transistor 3031; the ratio of the width corresponding to the channel of the first PMOS transistor 3011 to the width corresponding to the channel of the fifth PMOS transistor 3031 is greater than the ratio of the width corresponding to the channel of the third PMOS transistor 3021 to the width corresponding to the channel of the fourth PMOS transistor 3022, which means that the ratio of the current flowing from the drain of the fifth PMOS transistor 3031 to the first current is greater than the ratio of the current flowing from the drain of the fourth PMOS transistor 3022 to the second current, and the first weight value is greater than the second weight value.
The ratio (third current) between the threshold voltage of the first NMOS transistor 102 and the resistance of the first resistor is equal to the ratio (fourth current) between the threshold voltage of the second NMOS transistor 201 and the resistance of the second resistor, so as to ensure the reference current flowing out of the operation unit, as shown in formula 1:
the reference current of Iref, Vbg is a reference voltage, R1 is a first resistance value, m is a first weighted value, n is a second weighted value, R2 is a second resistance value, Vth1 is a threshold voltage of the first NMOS transistor, and Vth2 is a threshold voltage of the second NMOS transistor.
Therefore, in this case, the product of the third current and the first weight value is greater than the product of the fourth current and the second weight value, and the temperature coefficient of the reference current is a positive temperature coefficient.
Optionally, on the basis of the above technical solution, the length corresponding to the channel of the first PMOS transistor 3011 is equal to the length corresponding to the channel of the fifth PMOS transistor 3031; the ratio of the width of the channel corresponding to the first PMOS pipe 3011 to the width of the channel corresponding to the fifth PMOS pipe 3031 is smaller than the ratio of the width of the channel corresponding to the third PMOS pipe 3021 to the width of the channel corresponding to the fourth PMOS pipe 3022; the ratio (third current) between the threshold voltage of the first NMOS transistor 102 and the resistance of the first resistor is equal to the ratio (fourth current) between the threshold voltage of the second NMOS transistor 201 and the resistance of the second resistor; the temperature coefficient of the reference current is a negative temperature coefficient. The length corresponding to the channel of the first PMOS transistor 3011 is equal to the length corresponding to the channel of the fifth PMOS transistor 3031; the ratio of the width corresponding to the channel of the first PMOS transistor 3011 to the width corresponding to the channel of the fifth PMOS transistor 3031 is smaller than the ratio of the width corresponding to the channel of the third PMOS transistor 3021 to the width corresponding to the channel of the fourth PMOS transistor 3022, which means that the ratio of the current flowing from the drain of the fifth PMOS transistor 3031 to the first current is smaller than the ratio of the current flowing from the drain of the fourth PMOS transistor 3022 to the second current, and the first weight value is smaller than the second weight value.
The ratio between the threshold voltage of the first NMOS transistor 102 and the resistance of the first resistor is equal to the ratio between the threshold voltage of the second NMOS transistor 201 and the resistance of the second resistor, so that, referring to formula 1, the product of the third current and the first weight value is smaller than the product of the fourth current and the second weight value, and the temperature coefficient of the reference current is a negative temperature coefficient.
It should be noted that the above technical solution is directed to the case that the arithmetic unit shown in fig. 4 only includes one fourth PMOS transistor 3022 and one fifth PMOS transistor 3031. Fig. 5 exemplarily shows a case where the arithmetic unit includes two fourth PMOS transistors 3022 and two fifth PMOS transistors 3031.
It should be noted that the second current mirror unit 302 is composed of a third PMOS transistor 3021 and a fourth PMOS transistor 3022, where the second current mirror unit 302 may include at least one fourth PMOS transistor 3022. The embodiment of the present invention does not limit the specific number of the fourth PMOS transistors 3022 in the second current mirror unit, and a person skilled in the relevant art may determine the number of the fourth PMOS transistors 3022 according to specific situations. As the number of the fourth PMOS transistors 3022 included in the second current mirror unit 302 increases, the proportion of the negative temperature coefficient current in the reference current increases.
The third current mirror unit 303 is formed by a first PMOS transistor 3011 and a fifth PMOS transistor 3031, wherein the third current mirror unit 303 may include at least one fifth PMOS transistor 3031. The embodiment of the present invention does not limit the specific number of the fifth PMOS transistors 3031 in the third current mirror unit, and a person skilled in the relevant art may determine the number of the fifth PMOS transistors 3031 according to specific situations. As the number of the fifth PMOS transistors 3031 included in the third current mirror unit 303 increases, the ratio of the positive temperature coefficient current in the reference current increases.
Referring to fig. 6, it should be noted that the read operation is the most basic and important operation of the flash memory, and the design of the read path is also quite complex, the quality of the design of the read path directly determines whether the read operation functions normally, and the performance of the read path directly determines the read speed of the chip. The memory cells of the flash memory can store data due to the unique floating gate structures, and different charges stored by the floating gates of the memory cells mean different threshold voltages. If at four terminals of the memory cell: the control gate, the source, the drain and the body are applied with proper voltages respectively, and the memory cells corresponding to different threshold voltages have different reading currents. The memory cells can be divided into programmed memory cells and erased memory cells according to the difference of the read current. Or corresponding different logical values "0" and "1". Therefore, the read operation of the flash memory is actually to select the memory cell to be read and apply a voltage to its control gate and a voltage to its drain. The drain current of the memory cell is converted to a voltage and compared with a standard voltage by a sensitive comparator 600, thereby obtaining a logic value "0" or "1". As shown in fig. 5, Icell in the figure represents the read current of the selected memory cell, Iref represents the reference current generated by the reference circuit, Iref is a reference current, the current/voltage conversion module 500 is a circuit for converting the current into the voltage, and the current/voltage conversion module 500 converts the read current Icell of the memory cell and the reference current Iref generated by the reference circuit into the corresponding voltages.
It should be noted that, in the prior art, the flash memory reference circuit uses the reference cell and its reference current to determine the state of the memory cell during the read/write operation. However, the reference cell may be affected by various factors, for example, a disturbance in the power supply may cause a change in the voltage applied to the reference cell, thereby causing a change in the reference cell current. More seriously, because the performance of the reference unit may change after multiple operations, the designed reference current may drift, which causes the memory to work normally, thereby greatly reducing the service life of the memory.
According to the flash memory reference circuit provided by the embodiment of the invention, the reference memory cell is replaced by the MOS transistor and the resistor to generate the reference current, so that the problems that the threshold voltage of the reference memory cell is changed and the threshold voltage is increased when the reference memory cell is read for many times are solved. In addition, the reference current in this embodiment is the sum of the current with the positive temperature coefficient and the current with the negative temperature coefficient, and may also generate the reference current with different temperature coefficients, so that when the memory cell is read, the temperature coefficient of the reference current and the temperature coefficient of the read current may be kept consistent, and the read operation of the memory cell may be more accurate.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (6)
1. A flash reference circuit, comprising:
the positive temperature coefficient current module is used for generating a first current, and the first current is a positive temperature coefficient current;
a negative temperature coefficient current module for generating a second current, the second current being a negative temperature coefficient current;
the first end of the control module is electrically connected with the first end of the positive temperature coefficient current module, the second end of the control module is electrically connected with the first end of the negative temperature coefficient current module, the third end of the control module is electrically connected with the second end of the negative temperature coefficient current module, the control module is used for generating reference current according to the first current and the second current and outputting the reference current from the fourth end of the control module, and the temperature coefficient of the reference current is positive temperature coefficient, negative temperature coefficient or zero temperature coefficient;
the control module comprises a first current mirror image unit, a second current mirror image unit, a third current mirror image unit and an operation unit;
the first current mirror unit comprises a first PMOS tube and a second PMOS tube;
the second current mirror unit comprises a third PMOS tube and a fourth PMOS tube;
the third current mirror unit comprises the first PMOS tube and a fifth PMOS tube;
the arithmetic unit comprises the fourth PMOS tube and the fifth PMOS tube;
the grid electrode of the first PMOS tube is electrically connected with the grid electrode of the second PMOS tube;
the grid electrode of the third PMOS tube is electrically connected with the grid electrode of the fourth PMOS tube;
the grid electrode of the first PMOS tube is electrically connected with the grid electrode of the fifth PMOS tube;
the source electrode of the first PMOS tube, the source electrode of the second PMOS tube, the source electrode of the third PMOS tube, the source electrode of the fourth PMOS tube and the source electrode of the fifth PMOS tube are respectively electrically connected with a first power supply;
the drain electrode of the first PMOS tube is used as the first end of the control module and is electrically connected with the first end of the positive temperature coefficient current module;
the drain electrode of the second PMOS tube is used as a second end of the control module and is electrically connected with the first end of the negative temperature coefficient current module;
the drain electrode of the third PMOS tube is used as a third end of the control module and is electrically connected with the second end of the negative temperature coefficient current module;
the drain electrode of the fourth PMOS tube is electrically connected with the drain electrode of the fifth PMOS tube, and the fourth PMOS tube is used as the fourth end of the control module and is used for outputting the reference current;
the ratio of the width-length ratio corresponding to the channel of the fifth PMOS tube to the width-length ratio corresponding to the channel of the first PMOS tube is a first weight value;
the ratio of the width-length ratio corresponding to the channel of the fourth PMOS tube to the width-length ratio corresponding to the channel of the third PMOS tube is a second weighted value;
the reference current is a sum of a product of the first current and the first weight value and a product of the second current and the second weight value.
2. The circuit of claim 1,
the positive temperature coefficient current module comprises a first resistor and a first NMOS (N-channel metal oxide semiconductor) tube;
the drain electrode of the first NMOS tube is electrically connected with the drain electrode and the grid electrode of the first PMOS tube respectively;
the source electrode of the first NMOS tube is electrically connected with the first end of the first resistor;
the second end of the first resistor is grounded;
the grid electrode of the first NMOS tube is electrically connected with a reference voltage source, the reference voltage source is a zero temperature coefficient voltage source, and the reference voltage provided by the reference voltage source enables the first NMOS tube to be in a sub-threshold region.
3. The circuit of claim 2,
the negative temperature coefficient current module comprises a second NMOS tube, a third NMOS tube and a second resistor;
the source electrode of the second NMOS tube is grounded, and the drain electrode of the second NMOS tube is electrically connected with the drain electrode of the second PMOS tube and the grid electrode of the third NMOS tube respectively;
the drain electrode of the third NMOS tube is electrically connected with the grid electrode and the drain electrode of the third PMOS tube respectively;
the source electrode of the third NMOS tube is electrically connected with the grid electrode of the second NMOS tube and the first end of the second resistor respectively;
the second end of the second resistor is grounded;
the third NMOS tube is in a saturation region.
4. The circuit of claim 3,
the length corresponding to the channel of the first PMOS tube is equal to the length corresponding to the channel of the fifth PMOS tube;
the length corresponding to the channel of the third PMOS tube is equal to the length corresponding to the channel of the fourth PMOS tube;
the ratio of the threshold voltage of the first NMOS tube to the resistance value of the first resistor is a third current;
the ratio of the threshold voltage of the second NMOS tube to the resistance value of the second resistor is a fourth current;
a product of the third current and the first weight value is equal to a product of the fourth current and the second weight value;
the temperature coefficient of the reference current is a zero temperature coefficient.
5. The circuit of claim 3,
the length corresponding to the channel of the first PMOS tube is equal to the length corresponding to the channel of the fifth PMOS tube;
the length corresponding to the channel of the third PMOS tube is equal to the length corresponding to the channel of the fourth PMOS tube;
the ratio of the threshold voltage of the first NMOS tube to the resistance value of the first resistor is a third current;
the ratio of the threshold voltage of the second NMOS tube to the resistance value of the second resistor is a fourth current;
a product of the third current and the first weight value is greater than a product of the fourth current and the second weight value; the temperature coefficient of the reference current is a positive temperature coefficient.
6. The circuit of claim 3,
the length corresponding to the channel of the first PMOS tube is equal to the length corresponding to the channel of the fifth PMOS tube;
the length corresponding to the channel of the third PMOS tube is equal to the length corresponding to the channel of the fourth PMOS tube;
the ratio of the threshold voltage of the first NMOS tube to the resistance value of the first resistor is a third current;
the ratio of the threshold voltage of the second NMOS tube to the resistance value of the second resistor is a fourth current;
a product of the third current and the first weight value is smaller than a product of the fourth current and the second weight value;
the temperature coefficient of the reference current is a negative temperature coefficient.
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| CN201711230684.4A CN109841256B (en) | 2017-11-29 | 2017-11-29 | Flash memory reference circuit |
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| CN201711230684.4A CN109841256B (en) | 2017-11-29 | 2017-11-29 | Flash memory reference circuit |
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| CN112286337B (en) * | 2020-10-30 | 2023-04-21 | 佛山鸿博微电子技术有限公司 | Low-power-consumption bandgap circuit for MCU and implementation method thereof |
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| WO2014163521A1 (en) * | 2013-04-01 | 2014-10-09 | Freescale Semiconductor, Inc | A current generator circuit and method of calibration thereof |
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| US5777509A (en) * | 1996-06-25 | 1998-07-07 | Symbios Logic Inc. | Apparatus and method for generating a current with a positive temperature coefficient |
| CN101042591A (en) * | 2006-03-24 | 2007-09-26 | 智原科技股份有限公司 | Bandgap reference circuit for low supply voltage and method for supplying bandgap reference current |
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Address after: Room 101, Floor 1-5, Building 8, Yard 9, Fenghao East Road, Haidian District, Beijing 100094 Patentee after: Zhaoyi Innovation Technology Group Co.,Ltd. Patentee after: HEFEI GEYI INTEGRATED CIRCUIT Co.,Ltd. Address before: 100083 12 Floors, Block A, Tiangong Building, Science and Technology University, 30 College Road, Haidian District, Beijing Patentee before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. Patentee before: HEFEI GEYI INTEGRATED CIRCUIT Co.,Ltd. |