CN109946586B - Detection method of chip electrical connection defect - Google Patents
Detection method of chip electrical connection defect Download PDFInfo
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Abstract
本申请公开了一种芯片电连接缺陷的检测方法。所述方法包括：去除衬底，以暴露所述衬底上的有源区相连接的最下部层面的导电通道的端部；采用电子扫描显微镜的第一模式，从最下部层面的导电通道开始,获得所述多个层面的导电通道的形貌图像；采用电子扫描显微镜的第二模式，从最下部层面的互连线开始,获得所述多个层面的互连线的形貌图像；在所述多个层面的导电通道的形貌图像中，根据不同导电通道的端部的衬度，获得随后层面的互连线的缺陷定位信息；以及在所述多个层面的互连线的形貌图像中，根据所述缺陷定位信息发现缺陷位置，其中，所述第一模式的工作电压比所述第二模式的工作电压低。该检测方法可以实现缺陷位置的快速定位。
The present application discloses a detection method for chip electrical connection defects. The method includes: removing the substrate to expose the ends of the conductive channels of the lowermost level to which the active regions on the substrate are connected; using the first mode of the scanning electron microscope, starting from the conductive channels of the lowermost level , obtain the topographic images of the conductive channels of the multiple layers; use the second mode of the scanning electron microscope, starting from the interconnect lines of the lowest level, obtain the topographic images of the interconnect lines of the multiple layers; In the topographic images of the conductive channels of the multiple layers, according to the contrast of the ends of the different conductive channels, the defect location information of the interconnect lines of the subsequent layers is obtained; and the shape of the interconnect lines of the multiple layers is obtained. In the appearance image, the defect location is found according to the defect location information, wherein the working voltage of the first mode is lower than the working voltage of the second mode. The detection method can realize the rapid positioning of the defect position.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a method for detecting chip electrical connection defects.
Background
The increase in memory density of memory devices is closely related to the progress of semiconductor manufacturing processes. As the Critical Dimension (CD) of a pattern feature becomes smaller, the storage density of the memory device becomes higher. The three-dimensional memory device includes a plurality of memory cells stacked in a vertical direction, can increase the integration degree by a multiple on a unit area of a wafer, and can reduce the cost.
There are a large number of electrical connection structures inside the three-dimensional memory device for providing conductive paths, such as longitudinally extending conductive vias and laterally extending interconnect lines, for bit lines, word lines, select lines, source lines, and the like of the three-dimensional memory device. The failure of the three-dimensional memory device may be caused by a defect of the active region and may also be caused by a defect of the electrical connection structure. Therefore, one of the important aspects of failure analysis of three-dimensional memory devices is the detection of chip electrical connection defects.
In the detection of the chip electrical connection defect, the defect position can be located by the change of the chip internal current under a given voltage by using micro light microscopy (Emission microscopy) and light-induced resistance variation (OBIRCH). The detection method relies on a complete current path. If the electrical connections within the chip are broken, it is difficult to locate the defect site. The further improved method adopts a nanometer probe station, 2 probes are used for contacting two ends of the interconnecting wire, one end is pressurized, and the other end is grounded to judge whether the interconnecting wire is disconnected or not. Alternatively, the metal lines can be viewed directly through the surface layer under high voltage by Scanning Electron Microscopy (SEM) directly.
However, the above-described inspection method has difficulty in satisfying the demand for failure analysis of the complex electrical connection structure of the three-dimensional memory device, and further improvement of the inspection method of the electrical connection defect of the chip is expected to improve the inspection efficiency and accuracy.
Disclosure of Invention
In view of the foregoing problems, an object of the present invention is to provide a method for detecting a chip electrical connection defect, in which different modes of a scanning electron microscope are used to image a conductive channel layer and an interconnect layer respectively, so as to achieve fast positioning of a defect position.
According to an embodiment of the present invention, there is provided a method for detecting a defect in electrical connection of a chip, the chip including a substrate and an electrical connection structure on the substrate, the electrical connection structure including a plurality of levels of conductive vias and a plurality of levels of interconnect lines connected to each other, the method including: removing the substrate to expose the end of the conductive channel of the lowest layer connected with the active region on the substrate; acquiring a morphology image of the conductive channels of the multiple layers from the conductive channel of the lowest layer by adopting a first mode of an electron scanning microscope; adopting a second mode of the electronic scanning microscope, and obtaining a morphology image of the interconnection lines of the multiple layers from the interconnection line of the lowest layer; obtaining the defect positioning information of the interconnection lines of the subsequent layers in the shape images of the conductive channels of the multiple layers according to the contrast of the end parts of different conductive channels; and finding the position of the defect in the appearance images of the interconnection lines of the multiple layers according to the defect positioning information.
Preferably, the conductive channels of the multiple levels and the interconnect lines of the multiple levels are alternately stacked, the interconnect lines of the multiple levels extend laterally, the conductive channels of the multiple levels extend longitudinally, and the conductive channels of the multiple levels and the interconnect lines of the multiple levels are connected to each other to form a conductive path of the active region.
Preferably, when obtaining the topographic images of the conductive channels of the multiple layers, the covering layer of the conductive channels of the corresponding layer close to the substrate is removed in advance to expose the end parts of the conductive channels.
Preferably, when the topographic images of the interconnection lines of the multiple levels are obtained, the covering layer, close to the substrate, of the interconnection lines of the corresponding levels is removed in advance to expose the surfaces of the interconnection lines.
Preferably, the operating voltage of the first mode is 500 to 5KV, and the operating voltage of the second mode is 5 to 15 KV.
Preferably, the operating voltage of the first mode is selected in dependence on the contrast such that the contrast of the ends of the conductive paths in the defective and normal conductive paths is greater than a predetermined value.
Preferably, the operating voltage of the second mode is selected according to the spatial resolution of the topography, so that the topographical features of the interconnect lines can be resolved in a topographical image.
Preferably, the operating voltage of the first mode is lower than the operating voltage of the second mode.
Preferably, the spatial resolution of the topographic image obtained in the first mode is lower than the spatial resolution of the topographic image obtained in the second mode
According to the electric connection defect detection method provided by the embodiment of the invention, after the substrate and the corresponding active region are removed, the topography image is obtained layer by layer from the conductive channel of the lower layer. The conductive channel layer is imaged using a low operating voltage mode of a scanning electron microscope to obtain contrast between the defect and the normal conductive channel to provide defect localization information at subsequent levels. And imaging the interconnection line layer by adopting a high working voltage mode of a scanning electron microscope to obtain a high-resolution image of the interconnection line and further observe an accurate defect position. When the method is applied to a three-dimensional memory device with a complex structure and a large area, the defect position can be quickly found by the method, so that the detection efficiency is improved, the superposition phenomenon of metal wire images of different layers can be reduced, and the detection accuracy is improved.
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The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 shows a schematic cross-sectional view of an exemplary chip internal structure.
Fig. 2 shows a schematic view of the principle of an electrical connection defect detection method according to an embodiment of the present invention.
Fig. 3a to 3f show schematic cross-sectional views of various stages of an electrical connection defect detection method according to an embodiment of the present invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.
The inventor finds that the detection result of the contact position can only be obtained by adopting the nano probe station to detect the electric connection defect, the detection spatial resolution is limited by the size of the probe, and the detection time is too long because the multi-point detection is needed for a large-area chip. Therefore, the nano-probe station has difficulty in meeting the large area detection requirement of the three-dimensional memory device. The appearance of the visual field area can be obtained by adopting the detection of a scanning electron microscope, and the defect position can be found by observing the appearance image of the chip layer by layer. The spatial resolution of a scanning electron microscope is related to the operating voltage. The spatial resolution can be improved by adopting high voltage, but the electron penetration depth is deeper, and the image superposition of the electric connection structures of different layers causes difficulty in distinguishing defect characteristics. Therefore, it is difficult to satisfy the requirement of detecting the complex structure of the three-dimensional memory device by using the topographic image of the scanning electron microscope.
Fig. 1 shows a schematic cross-sectional view of an exemplary chip internal structure. The chip structure will be used to illustrate an electrical connection defect detection method according to an embodiment of the present invention. The actual chip structure is associated with a specific chip type, e.g., a chip of a three-dimensional memory device has a more complex structure. However, the electrical connection defect detection method according to the embodiment of the present invention can be applied to electrical connection structures of different types of chips.
As shown, the chip 100 includes a semiconductor substrate 101, two transistors T1 and T2, and corresponding electrical connection structures.
In the chip 100, the transistor T1 includes a source region 111 and a drain region 112 formed in a semiconductor substrate 101, a stacked structure of a gate dielectric 113 and a gate conductor 114 formed on the semiconductor substrate 101 between the source region 111 and the drain region 112, and sidewalls 115 on both sides of the stacked structure. The transistor T2 includes a source region 121, a drain region 122 formed in the semiconductor substrate 101, a gate stack of a gate dielectric 123 and a gate conductor 124 formed on the semiconductor substrate 101 between the source region 121 and the drain region 122, and sidewalls 125 on both sides of the stack. An interlayer insulating layer 102 covers the semiconductor substrate 101 and the gate stack structure.
Further, the electrical connection structures in the chip 100 are used for the conductive channels and the interconnection lines connected to the source 111 of the transistor T1 and the source 121 of the transistor T2, respectively. The electrical connection structure includes, for example, multiple levels of conductive vias and multiple levels of interconnect lines. The interconnection lines are located on the interlayer insulating layers 102-104 of different levels and used for the transverse extension of the conductive paths, and the conductive channels penetrate through the corresponding interlayer insulating layers 102-104 and used for the longitudinal extension of the conductive paths, so that the interconnection lines of the adjacent levels are connected. An interlayer insulating layer 105 covers the uppermost interconnect line. Although not shown, additional pads may be formed on the interlayer insulating layer 105 for providing electrical connection between the electrical connection structure inside the chip and an external circuit.
As shown, the first conductive path connected to the source 111 of the transistor T1 includes, in order, a conductive via 211, an interconnect line 212, a conductive via 213, an interconnect line 214, a conductive via 215, and an interconnect line 216, and the second conductive path connected to the source 121 of the transistor T2 includes, in order, a conductive via 221, an interconnect line 222, a conductive via 223, an interconnect line 224, a conductive via 225, and an interconnect line 226. Electrical connection defects of the chip 100 may exist in the conductive vias and interconnect lines at either level.
Fig. 2 shows a schematic view of the principle of an electrical connection defect detection method according to an embodiment of the present invention. For the sake of clarity, only the electrical connection structure of the chip 100 is shown in the drawing, and the corresponding interlayer insulating layer is not shown. In this example, it is assumed that the interconnect line 212 of the first conductive path is disconnected.
The detection method comprises the step of preprocessing the chip. The pre-treatment removes the substrate and the corresponding active area, exposing the conductive channel of the lower level. The detection method starts from the conductive channel of the lower layer, and detects the interconnecting wire and the conductive channel of the upper layer one by one. In the detection method, different modes of a scanning electron microscope are adopted to respectively image the conductive channel layer and the interconnection line layer so as to realize the rapid positioning of the defect position.
For the conductive channel layer, the scanning electron microscope is irradiated with 500V-5 KV (e.g. 1KV) working voltage. Due to the fact that the working voltage is low, the spatial resolution of the appearance image of the conductive channel layer is correspondingly low. More positive charge accumulates in the disconnected conductive path than in the normal conductive path. Thus, when the electron beam 106 irradiates the exposed end of the conductive channel, the conductive channel captures a greater number of electrons in the broken conductive path, thereby generating a smaller number of secondary electrons. The amount of secondary electrons received in the detection probe 107 is smaller and, therefore, the imaging brightness of the exposed end portion of the conductive path is lower. In the low-resolution morphology image, more obvious contrast of the conductive channel can be obtained, and whether the corresponding conductive path is disconnected or not can be judged by observing brightness at the conductive channel. As shown, the brightness of the exposed end of the conductive via 211 in the first conductive path is lower than the brightness of the exposed end of the conductive via 221 in the second conductive path. This step provides defect localization information for subsequent levels, i.e., locations of open defects in the interconnect lines connected to the conductive vias 211.
For the interconnect layer, the scanning electron microscope is irradiated with an operating voltage of 5KV to 15K (e.g., 10 KV). Due to the large surface area of the interconnect lines, it is also difficult to obtain contrast between defects and normal interconnect lines with low operating voltages. A higher operating voltage is used in this step to obtain a high resolution topographical image of the interconnect layer. And further observing the accurate defect position in the morphology image of the corresponding interconnection layer according to the positioning information obtained in the morphology image of the conductive channel layer. For example, a defect location 311 may be found in the interconnect line 212 in the first conductive path.
According to the detection method, after the substrate and the corresponding active region are removed, the topography image is obtained layer by layer from the conductive channel of the lower layer. The conductive channel layer is imaged using a low operating voltage mode of a scanning electron microscope to obtain contrast between the defect and the normal conductive channel to provide defect localization information at subsequent levels. And imaging the interconnection line layer by adopting a high working voltage mode of a scanning electron microscope to obtain a high-resolution image of the interconnection line and further observe an accurate defect position. When the method is applied to a three-dimensional memory device with a complex structure and a large area, the defect position can be quickly found by the method, so that the detection efficiency is improved, the superposition phenomenon of metal wire images of different layers can be reduced, and the detection accuracy is improved.
Fig. 3a to 3f show schematic cross-sectional views of various stages of an electrical connection defect detection method according to an embodiment of the present invention. In this example, assume that the interconnect lines 212, 214, and 246 of the first conductive path each have a defective location of disconnection.
The detection method starts with the chip 100 shown in fig. 1.
In step S01, the chip 100 is preprocessed by grinding to remove the substrate 101 and the active regions of the transistors T1 and T2.
Referring to fig. 1, the first conductive path connected to the source 111 of the transistor T1 includes a conductive via 211, an interconnection line 212, a conductive via 213, an interconnection line 214, a conductive via 215, and an interconnection line 216 in this order, and the second conductive path connected to the source 121 of the transistor T2 includes a conductive via 221, an interconnection line 222, a conductive via 223, an interconnection line 224, a conductive via 225, and an interconnection line 226 in this order.
After removing the semiconductor substrate 101 and the active regions of the transistors T1 and T2, the ends of the conductive vias 211 and 221 of the lower level are exposed.
In step S02, the scanning electron microscope obtains a topographic image of the conductive channels of the lower layer using an operating voltage of, for example, 1KV, as shown in fig. 3 a.
The working voltage is lower, and therefore, the spatial resolution of the topographic image of the conductive channel layer is correspondingly lower. The conductive channels 211 and 221 are located in the open and normal conductive paths, respectively, where more positive charge accumulates than in the normal conductive path. When the electron beam 106 irradiates the exposed ends of the conductive paths 211 and 221, the conductive path 211 captures a greater number of electrons than the conductive path 221, and thus generates a smaller number of secondary electrons. In the topographic image, the brightness of the conductive channel 211 is smaller than that of the conductive channel 221, and based on the contrast between the two, the defect location information of the subsequent layer, that is, the position of the broken defect in the interconnection line connected to the conductive channel 211, can be obtained.
In step S03, the interlayer insulating layer 102 is removed by grinding, and the gate stack structure and the conductive via therein are also removed together.
In step S04, the sem obtains a topographic image of the interconnection lines on the lower layer using, for example, 5-10 KV of operating voltage, as shown in fig. 3 b.
The operating voltage is higher and, therefore, the spatial resolution of the topographic image of the interconnect layer is correspondingly higher. Due to the large surface area of the interconnect lines, it is difficult to obtain contrast between defects and normal interconnect lines even with low operating voltages. And further observing the accurate defect position in the morphology image of the corresponding interconnection layer according to the positioning information obtained in the morphology image of the conductive channel layer. For example, a defect location 311 may be found in the interconnect line 212 in the first conductive path.
Further, as shown in fig. 3c to 3f, steps S01 to S04 are repeated, and the topographic image is obtained layer by layer starting from the conductive channel of the subsequent layer. The conductive channel layer is imaged using a low operating voltage mode of a scanning electron microscope to obtain contrast between the defect and the normal conductive channel to provide defect localization information at subsequent levels. And imaging the interconnection line layer by adopting a high working voltage mode of a scanning electron microscope to obtain a high-resolution image of the interconnection line and further observe an accurate defect position. Thus, the inspection of the conductive paths and interconnections of all levels can be accomplished.
In the above description, the details of the patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the invention, and these alternatives and modifications are intended to fall within the scope of the invention.
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| CN111745531B (en) * | 2020-07-01 | 2021-08-27 | 长江存储科技有限责任公司 | Curved surface grinding device and chip extraction method |
| CN112687535B (en) * | 2020-12-25 | 2024-05-10 | 苏州芯联成软件有限公司 | III-V material chip delamination method |
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| US7317203B2 (en) * | 2005-07-25 | 2008-01-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and monitor structure for detecting and locating IC wiring defects |
| US8193491B2 (en) * | 2008-09-29 | 2012-06-05 | Hermes Microvision, Inc. | Structure and method for determining a defect in integrated circuit manufacturing process |
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