CN100342454C - Reference Current Generation Circuit for Multi-bit Flash Memory - Google Patents

Abstract

A reference current generation circuit of a multi-bit flash memory is disclosed, which uses the same boosted word line voltage to apply to the gates of the reference memory cells of different reference current generation units,and different substrate voltages are applied to the substrate of the reference memory cell to achieve different required levels of reference current, so as to effectively improve the reference current with temperature and power voltage V_CCHas different drift problems.

Description

Reference Current Generation Circuit for Multi-bit Flash Memory

technical field

The present invention relates to a multiple bit flash memory (Multiple Bit Flash Memory), and in particular to a reference current generating circuit of a multiple bit flash memory.

Background technique

Flash memory is a non-volatile memory (Non-Volatile Memory) that can perform multiple data writing (Program), reading (Read) and clearing (Erase), because the data stored in it will not be affected by power supply The interrupt disappears, and it is easy to change the characteristics of the stored data through clearing and writing operations, so it is widely used in electronic devices such as personal computers.

A typical flash memory is composed of many flash memory cells (Flash Cell), and each flash memory cell is usually used to store one bit of data. The structure of the flash memory cell uses doped polysilicon to make the floating gate (Floating Gate) and the control gate (Control Gate), while the floating gate and the control gate are separated by a dielectric layer, and the floating The gate and the substrate are separated by a tunnel oxide layer (Tunnel Oxide). When the operation of writing/erasing data is performed on the flash memory cell, a bias voltage is applied to the control gate and the drain, so that electrons are injected into the floating gate or electrons are pulled out from the floating gate. When reading the data in the flash memory unit, a word-line voltage (Word-Line Voltage) is applied to the control gate. At this time, the charged state of the floating gate will affect the opening of the lower channel (Channel). On/off state, and the on/off state of this channel is the basis for judging the data value "0" or "1".

With the advancement of semiconductor technology and the demand for increased flash memory capacity, a multi-bit flash memory has been developed, that is, each flash memory unit stores more than two bits of data. Therefore, when reading the data stored in the flash memory unit, the read current must be compared with the reference current to determine the stored data value.

Please refer to FIG. 1 , which is a schematic diagram of the threshold voltage (Threshold Voltage) distribution of a 2-bit flash memory cell of a flash memory. The abscissa in the figure represents the magnitude of the threshold voltage Vth, and the ordinate represents the number of flash memory cells for each threshold voltage Vth, and the distribution of the number generally presents a Gaussian distribution as shown in the figure. The figure shows that when clearing the flash memory cell, its starting voltage Vth will be below EV; when writing "01" data value to the flash memory cell, its starting voltage Vth will be between PV ₁ and lower than R ₂ ; when writing "10" data value to the flash memory cell, its starting voltage Vth will be between PV ₂ and lower than R ₃ ; and when writing "11" data value to the flash memory cell , its starting voltage Vth is above PV ₃ . Therefore, when clearing the flash memory cells, the word line voltage of EV will be applied to the control gate, and the read current will be used to judge whether the clearing operation is completed; when performing writing "01", "10" and "11" When the data value is sent to the flash memory cell, the word line voltages of PV ₁ , PV ₂ and PV ₃ will be respectively applied to the control gate, and the read current will be used to judge whether the write operation is completed; and when the read flash is executed When the data value is stored in the memory cell, the word line voltages of R ₁ , R ₂ and R ₃ are respectively applied to the control gate, and the read current is used to determine what the read data value is, and the read current Compared with the reference current generated by the reference current generation circuit, the data value read by it is judged.

It is known that the reference current generation circuit used to achieve the above purpose is achieved by applying different levels of Boosted Word-Line Voltage (BWLV) to the gates of different reference memory cells. Take the above-mentioned 2-bit flash memory unit as an example, because there are EV, PV ₁ , PV ₂ , PV ₃ , R ₁ , R ₂ and R ₃ etc. Erase Verify/Program Verify/ Reading (Read) has 7 different levels of word line voltage, so it will need 7 different levels of push-up word line voltage to complete, such as taking a 3-bit flash memory unit as an example, 15 different levels are required. bit is accomplished by boosting the word line voltage. Since each push-up word line voltage is susceptible to different changes due to the influence of temperature and power supply voltage V _CC , the reference currents generated by the reference current generating circuit in this way will also vary with temperature and power supply voltage V _CC . There are different drifts due to changes.

Contents of the invention

The purpose of the present invention is to provide a reference current generating circuit, which can improve the problem that the reference current has different drifts with changes in temperature and power supply voltage V _CC .

In order to achieve the above and other objects, the present invention provides a reference current generating circuit suitable for a multi-bit flash memory, the reference current generating circuit includes a plurality of reference current generating units, and each reference current generating unit includes a load and A reference storage unit. The load has a first connection end and a second connection end, the first connection end is connected to a working power supply, the second connection end is connected to the first source/drain of the reference storage unit, and the second source/drain of the reference storage unit is grounded, The gate is connected with a boost word line voltage, and the base is connected with a base voltage. Wherein, the gate of each reference current generating unit is connected to the same boost word line voltage, and the substrate voltage connected to the base of each reference current generating unit is based on a reference current generated by the reference current generating unit. vary in size.

In a preferred embodiment of the present invention, its reference storage unit is a dummy storage unit (Dummy Cell), and the so-called dummy storage unit connects the floating gate and the control gate of the flash memory unit of the multi-bit flash memory of the same structure made together. Wherein, in order to grasp the characteristics of the reference memory unit more easily, the length and width of the gate channel of the reference memory unit are made larger, and the length and width of the gate channel of the flash memory unit of the reset flash memory are larger, For example, the length and width of the gate channel of the design reference memory cell are 1 μm.

In addition, in order to further improve the characteristics of the reference memory cells, more reference memory cells than required by each reference current generating unit can be fabricated in the same layout block (bank), and one or more reference memory cells can be used. The same reference memory cell is used to generate the reference current. And when a plurality of identical reference memory cells in the same layout block are used to generate the reference current, all the same reference memory cells used are connected in parallel to generate the reference current.

It can be seen from the above description that the reference current generation circuit provided by the present invention uses the same boost word line voltage to apply to the gates of different reference memory cells, and to apply different base voltages to the reference memory cells The substrate is used to achieve the required reference currents of different levels, so the problem of different drifts of the reference current with changes in temperature and power supply voltage V _CC can be effectively improved.

Description of drawings

1 is a schematic diagram showing the distribution of the initial voltage of a 2-bit flash memory cell of a flash memory;

FIG. 2 is a schematic diagram showing a reference current generating circuit according to a preferred embodiment of the present invention; and

FIG. 3 shows a schematic diagram of a reference current relationship curve of a reference current generating circuit according to a preferred embodiment of the present invention.

200: Reference current generating circuit

210, 270: load

211, 271: the first connection end

212, 272: the second connection end

213, 273: first source/drain

214, 274: second source/drain

215, 275: grid

216, 276: base

Detailed ways

Please refer to FIG. 2 , which is a schematic diagram of a reference current generating circuit according to a preferred embodiment of the present invention. As shown in the figure, the reference current generating circuit 200 includes m reference current generating units bank1˜bankm, where the value of m depends on the number of bits of the flash memory unit of the multi-bit flash memory using the reference current generating circuit 200. For example, m=7 for a 2-bit flash memory unit, m=15 for a 3-bit flash memory unit, and so on for other flash memory units. The memory cell, that is, m=7, will be described as an example.

Taking the 2-bit flash memory unit as an example, there will be seven reference current generation units in the figure, including bank1~bank7, and the reference current generation unit bank1 includes a load 210 and reference storage units k ₁₁ ~k _1n connected in parallel, while the reference The current generating unit bank7 includes a load 270 and reference storage units k ₇₁ -k _7n connected in parallel, and the structure of other unshown reference current generating units bank2 - bank6 is also the same.

Wherein, the reference memory cells k ₁₁ -k _7n are, for example, a dummy cell (DummyCell), that is, the floating gate and the control gate of the flash memory cells of the multi-bit flash memory with the same structure are connected together. Because the characteristics of a process with a larger gate channel size are generally easier to grasp, in order to make it easier to grasp the characteristics of the reference memory cells k ₁₁ -k _7n and make the generated reference current more accurate, the reference memory cells The length and width of the gate channel of k ₁₁ ~k _7n are more manufactured. The length and width of the gate channel of the flash memory unit of the multi-bit flash memory are larger, for example, when the process of the multi-bit flash memory uses 0.18 μm During the process, the length and width of the gate channels of the reference memory cells k ₁₁ -k _7n can be designed to be 1 μm. .

In addition, in the layout design, in order to further improve the characteristics of the reference memory cells k ₁₁ -k _7n , each of the reference current generating units bank1 -bank7 can be individually required for the reference memory cells k ₁₁ -k _1n , . . . k ₇₁ to k _7n are produced individually in the same layout block (bank). That is to say, the reference memory cells k ₁₁ -k _1n are made in the same layout block, and the reference memory cells k ₇₁ -k _7n are also made in another layout block, and a non-layout block is selected in each layout block The boundary reference storage unit is used to reduce the characteristic variation factor caused by the marginal effect.

As shown in the figure, the load 210 of the reference current generation unit bank1 has a first connection terminal 211 and a second connection terminal 212, the first connection terminal 211 is connected to a working power supply V _DD , and the second connection terminal 212 is connected to the reference storage unit k ₁₁ The first source/drain 213 connected in parallel to k _1n , etc., the second source/drain 214 connected in parallel to the reference memory cells k ₁₁ to k _1n , etc. are grounded, and the gate 215 is connected in parallel to a push-up word line voltage BWLV , the substrate 216 is connected in parallel to a substrate voltage Vb ₁ to generate a reference current Id ₁ .

In addition, the load 270 of the reference current generation unit bank7 has a first connection terminal 271 and a second connection terminal 272. The first connection terminal 271 is connected to a working power supply V _DD , and the second connection terminal 272 is connected to the reference storage units k ₇₁ -k _7n , etc. The first source/drain 273 connected in parallel, the second source/drain 274 connected in parallel with the reference memory cells k ₇₁ to k _7n etc. are grounded, the gate 275 is connected in parallel to a push-up word line voltage BWLV, and the base 276 is connected in parallel to a base voltage Vb ₇ to generate a reference current Id ₇ .

Wherein, because the gates 215-275 of each reference current generating unit bank1-bank7 are connected in parallel to the same boost word line voltage BWLV, and because the generated reference current Id is different from the gate channel width W of the reference memory unit itself , the gate channel length L, the push-up word line voltage BWLV and the starting voltage Vth are as follows:

Id∝W/L(BWLV-Vth), and the gate channel width W and gate channel length L of each reference storage unit k ₁₁ ~ k _7n are designed to be the same in this embodiment, and the starting voltage Vth is equal to The base voltage Vb is in a proportional relationship, so the base of each reference current generating unit bank1-bank7 is connected to different base voltages _Vb1 - _Vb7 according to the size of the reference current _Id1 - _Id7 to be generated, for example Connect to different substrate voltages such as 0V, -0.5V, -1V, -1.5V, -2V, -2.5V and -3V respectively to obtain different reference currents Id ₁ ~ Id ₇ , the relationship curves are shown in Figure 3 Show.

Although each of the above-mentioned reference current generating units bank1-bank7 generates different reference currents Id ₁ -Id ₇ by a plurality of identical reference storage units k ₁₁ -k _1n ...k ₇₁ -k _7n etc., or The average values thereof can be further obtained as reference currents Id ₁ -Id ₇ . However, those skilled in the art should know that only one of the reference memory cells in each of the reference current generating units bank1-bank7 can be used to generate the reference currents Id ₁ -Id ₇ . For example, in the reference current generation unit bank1, only the reference storage unit k ₁₁ is used to generate the reference current Id ₁ , and in the reference current generation unit bank7, only the reference storage unit k ₇₁ is used to generate the reference current Id ₇ , other reference storage units are not incorporated into this reference current generation circuit.

In summary, the present invention has at least the following advantages:

1. Since the same word line voltage is used to apply to the gates of different reference memory cells, and then different base voltages are applied to the bases of the reference memory cells to achieve the required reference currents of different levels, so It can effectively improve the problem that the reference current has different drifts as the temperature and the power supply voltage V _CC vary.

2. Due to the use of the gate channel width and length of the reference memory cell of non-critical dimension (non-critical dimension) and the selection of one or more reference memory cells of multiple reference memory cells in the same layout block (bank) to generate the reference current, so it is easier to grasp the characteristics of each reference memory cell.

Claims (6)

1. A reference current generation circuit, suitable for a multi-position flash memory, comprising a plurality of reference current generation units, characterized in that each reference current generation unit in the plurality of reference current generation units comprises: A load has a first connection end and a second connection end, and the first connection end is connected to a working power supply; and A reference storage unit has a base, a gate, a first source/drain and a second source/drain, the first source/drain is connected to the second connection terminal, and the second source/drain Grounded, the gate is connected to a push-up word line voltage, and the base is connected to a base voltage; Wherein, the gate of each reference current generation unit in the plurality of reference current generation units is connected to the same boosted word line voltage, and the gate of each reference current generation unit in the plurality of reference current generation units The substrate voltage connected to the substrate is different according to the magnitude of the reference current generated by the reference current generating units. 2. The reference current generating circuit as claimed in claim 1, wherein the reference storage unit is a dummy storage unit. 3. The reference current generating circuit according to claim 1, wherein the length and width of the gate channel of the reference memory unit are larger than the length and width of the gate channel of the flash memory unit of the multi-bit flash memory. The width dimension is large. 4. The reference current generating circuit as claimed in claim 3, wherein the length and width of the gate channel of the reference memory cell are 1 μm. 5. The reference current generating circuit as claimed in claim 1, wherein the reference memory cell is located in one of a plurality of identical reference memory cells in a same layout block (bank). 6. The reference current generating circuit as claimed in claim 1, wherein the reference memory cell is connected in parallel with a plurality of same reference memory cells located in the same layout block to generate the reference current.

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