CN100353347C - Method for realizing PCI multi-function card - Google Patents
Method for realizing PCI multi-function card Download PDFInfo
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- CN100353347C CN100353347C CNB021530122A CN02153012A CN100353347C CN 100353347 C CN100353347 C CN 100353347C CN B021530122 A CNB021530122 A CN B021530122A CN 02153012 A CN02153012 A CN 02153012A CN 100353347 C CN100353347 C CN 100353347C
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Abstract
The present invention provides a method for more effectively realizing connecting perpheral elements to a (PCI) multi-function card in an interacting mode. The multi-function indicating bit in the configuration space of the main function of the PCI multi-function card, namely the bit 7 in the header type field (Header Type) of a 0EH address, is set as 1; when register addressing is configured, a configuration register addressing signal (IDSEL#) which is used for the other function of the multi-function card is generated by using the function number of configuration access to participate in the PCI configuration register decoding; when the other function of the PCI multi-function card carries out a main device bus application, and the main function of the PCI multi-function card carries out the arbitration of the bus application and carries out the bus application to the PCI bus, so that the method for effectively realizing the multi-function card is achieved.
Description
Technical field the present invention specifically, is the method that realizes the mutual connecting bus of peripheral component (PCI) multifunction card about a kind of about realizing the method for multifunction card.
Background technology is along with the improve of computer technology, and on personal computer (PC), PCI has substituted ISA gradually, eisa bus becomes the new standard of the local bus of computing machine, even ISA, eisa bus no longer are provided on some personal computer.But because motherboard resources, the PCI slot that provides on personal computer is limited, generally has only 3-6, for ever-increasing configuration requirement, and PCI slot resource some anxiety that just seems relatively.If can on a pci card, realize two or more PCI functions, can save the PCI slot resource of system effectively, reduce the production cost of PCI integrated circuit board factory simultaneously.
In " though PCI local bus standard " agreement to how realizing that the PCI multifunction card has explanation, but owing to realize that PCI's is multi-functional different with the single function of PCI aspect a lot, comprising the multi-functional configuration space decoding of PCI, preventing of main device bus application conflict, the arbitration that bus is used.Therefore, only custom-designed multifunctional circuit, otherwise integrated circuit board production firm can't simply be originally that with two the circuit design for single function pci card design becomes a multi-functional pci card.If row that sticks into for the design of single function wherein once can be improved, make it can either use on unifunctional pci card, during simultaneously as multifunction card, another card for single function design simply can be synthesized multifunction card again, more combination is provided for integrated circuit board manufacturer, realizes the variation of product easily.
Summary of the invention the invention provides a kind of method of more effective realization PCI multifunction card for above purpose, and this method comprises:
In the configuration space of the PCI multifunction card function of tonic chord, multi-functional indicating bit, be that position 7 in the leader type field (Header Type) of 0EH address is necessary for 1.
When the configuration register addressing, utilize the function number participation PCI configuration register decoding of configuration access, produce the configuration register address signal (IDSEL#) of another function that is used for multifunction card;
Utilize function No. 0, to IDSEL# pin, AD[1:0] and AD[10:8] encoded radio decipher, produce the step be used for second function is carried out the signal IDSEL2# of PCI configuration access;
With the bus application signal wire (REQ#) of second function as input, and send bus application request to pci bus by the bus filing of the award logic of function 0, after obtaining the bus right to use, bus arbitration logic by function 0 determines the priority that bus is used, and uses affirmation line (GNT2#) to offer the step of second function conflict free bus.
In a word, when multi-functional another function of PCI is carried out the main device bus application, carry out the arbitration of bus application by the multi-functional function of tonic chord of PCI, and carry out the application of bus to pci bus.
Description of drawings has been pointed out theme of the present invention particularly in claims of present patent application, and clearly it has been proposed patent protection.Yet with reference to following detailed description and accompanying drawing, relevant structure that can better understand the present invention and implementation method with and purpose, feature and advantage.
Fig. 1 is the block diagram of the method for realization PCI multifunction card of the present invention;
Fig. 2 is explanation is realized IDSEL2# decoding by function 0 a schematic diagram;
Fig. 3 be the explanation multifunction card carry out the bus filing of the award by function 0.
Specific implementation method has been described specific details and so that provide the present invention has comprehensively been understood in the following detailed description.Yet the professional and technical personnel will appreciate that the present invention also can implement with other similar details.
By " PCI local bus standard " regulation, the PCI function must provide the information of " identity and feature ", therefore, each PCI function, each function that comprises multi-functional pci card all will provide above information by special-purpose " configuration space (Configuration Space) ", with reference to following table.
| Byte offset | 32 16 15 0 of sense bit | |||
| 00H | Device code (Device ID) | Vendor code (Vendor ID) | ||
| 04H | Status word (Status) | Command word (Command) | ||
| 08H | Base class code (Base Class | Subclass code (Sub Class | The specified register DLL (dynamic link library) | Revision (Revision |
| Code) | Code) | (Prog.I/F) | ID) | |
| 0CH | Include self-test (BIST) | Leader type (Header Type) | Time-delay counting (Latency Timer) | Cache memory sizes (Cache Line Size) |
| 10H 14H 18H 1CH 20H 24H | Base address register (Base Address Register) | |||
| 28H | CardBus bus configuration district register (CardBus CIS Pointer) | |||
| 2CH | Subsystem code (Subsystem ID) | Suppliers of the subsystems' code (Subsystem Vendor ID) | ||
| 30H | Expansion ROM base address register (Expansion ROM Base Address) | |||
| 34H 38H | Keep (Reserved) | |||
| 3CH | Maximum latent time (Max Lat) | The minimum response time (Min Gnt) | Interrupt pin number (Interrupt Pin) | Interrupt trunk number (Interrupt Line) |
Last table explanation be information in the configuration space that provides of PCI function, comprising: whether the PCI plug-in card is arranged on the slot; The function that this pci card has (providing) by PCI base class code; The production firm of this PCI plug-in card (providing) by vendor code; Product type (providing) by device code; And this pci card needs configuration and shared computer resource.
By " PCI local bus standard " regulation, the position 7 that is positioned at the leader type field (Head Type) of 0EH byte is used for identifying a multifunctional equipment.If this position is 0 then represents that corresponding apparatus is a single-function device; Otherwise, if 1 this equipment of explanation is multifunctional equipment.Although the invention is not restricted to this, as a specific embodiment of the present invention, this value can be set by the port pin: when external terminal connect high level, this position was 1; When external terminal connect low level, this position was 0.As of the present invention another is embodiment, and this value also can be downloaded (as network card equipment) by external EEPROM when powering in system automatically by being stored in fixed bit among the external EEPROM.Such realization makes this equipment both can work in No. 0 function of multifunctional equipment, can independently be used in single-function device again.
For multifunctional equipment, stipulate according to " PCI local bus standard ", 0 class configuration access can be accepted and respond to requirement, and can accept the function number field that 0 class view is asked configuration, utilize its IDSEL# pin, AD[1:0], and AD[10:8] these three conditions of encoded radio determine whether responding corresponding configuration response.If equipment is multifunctional equipment, must have function No. 0, and second function can be 1~7 any one central number.In the present invention, utilize function No. 0, to IDSEL# pin, AD[1:0], and AD[10:8] encoded radio decipher, produce the required IDSEL2# signal of second function.Although the invention is not restricted to this,, utilize as AD[1:0 as a specific embodiment of the present invention]=00, AD[10:8]=001, during IDSEL#=0, the useful signal of generation IDSEL2# offers the visit that second function is configured function.Fig. 2 offers the specific implementation that the IDSEL2# of second function deciphers.
When two functions of multifunctional equipment can be operated in holotype following time, if bus application signal wire REQ# and GNT# are not arbitrated, will produce bus contention, data manipulation can't be gone on, more serious meeting causes systemic breakdown.Can both carry out normal data transfer operation in order to make two functions, by No. 0 function bus application and acquisition are arbitrated, although the invention is not restricted to this, as a specific embodiment of the present invention, as shown in Figure 3, be responsible for the bus request of this function and function 1 is handled by the pci bus filing of the award logic of No. 0 function inside, here, this moderator adopts the algorithm of fixed mechanism, the bus request that is this function is made as high priority, and the bus request of function 1 is a low priority, when two functions are applied for bus simultaneously, at first obtains bus by function 0.
Though herein declarative description certain this feature of the present invention and a kind of implementation method, for the professional and technical personnel, many modifications, replacement, variation and equivalent substitution will appear.Therefore, protection scope of the present invention is as the criterion by the scope of appended claim.
Claims (3)
1. method that realizes the PCI multifunction card, this method may further comprise the steps:
With the position 7 in the leader type field in the configuration space of the PCI multifunction card function of tonic chord, promptly multi-functional indicating bit is set at 1 step;
Utilize function No. 0, to IDSEL# pin, AD[1:0] and AD[10:8] encoded radio decipher, produce the step be used for second function is carried out the signal IDSEL2# of PCI configuration access;
With the bus application signal wire (REQ#) of second function as input, and send bus application request to pci bus by the bus filing of the award logic of function 0, after obtaining the bus right to use, bus arbitration logic by function 0 determines the priority that bus is used, and uses affirmation line (GNT2#) to offer the step of second function conflict free bus.
2. method according to claim 1, wherein the function of tonic chord is No. 0 function.
3. method according to claim 1, wherein the number of second function can be any one number in the middle of the 1-7.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB021530122A CN100353347C (en) | 2002-11-25 | 2002-11-25 | Method for realizing PCI multi-function card |
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| CNB021530122A CN100353347C (en) | 2002-11-25 | 2002-11-25 | Method for realizing PCI multi-function card |
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| CN1503145A CN1503145A (en) | 2004-06-09 |
| CN100353347C true CN100353347C (en) | 2007-12-05 |
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| JP4626582B2 (en) * | 2006-07-03 | 2011-02-09 | ソニー株式会社 | Card-type peripheral device and card communication system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09153009A (en) * | 1995-12-01 | 1997-06-10 | Hitachi Ltd | Hierarchical bus arbitration method |
| CN1193393A (en) * | 1995-06-15 | 1998-09-16 | 英特尔公司 | Architecture for an I/O processor that integrates a PCI bridge |
| WO2001016610A1 (en) * | 1999-09-02 | 2001-03-08 | Philips Semiconductors, Inc. | Device for and method of preventing bus contention |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1193393A (en) * | 1995-06-15 | 1998-09-16 | 英特尔公司 | Architecture for an I/O processor that integrates a PCI bridge |
| JPH09153009A (en) * | 1995-12-01 | 1997-06-10 | Hitachi Ltd | Hierarchical bus arbitration method |
| WO2001016610A1 (en) * | 1999-09-02 | 2001-03-08 | Philips Semiconductors, Inc. | Device for and method of preventing bus contention |
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