CN100365787C - FLASH internal unit test method that supports write buffer - Google Patents

Abstract

The present invention relates to a testing method of a FLASH internal unit which supports writing buffer. The present invention comprises the following steps: a full wafer is erased; then loop walk 0 data blocks are written according to an address order, and the write operation is carried out according to the mode of writing buffer zones; after all internal units are written, data is read for checking. On the premise of guaranteeing testing efficiency, relatively complete testing cover of FLASH faults is realized by the method of the present invention, and the method of the present invention is suitable for testing FLASH internal units which support writing buffer in various situations.

Description

FLASH internal unit test method that supports write buffer

technical field

The invention relates to a FLASH memory, in particular to a method for testing a FLASH internal unit supporting write buffering.

Background technique

FLASH device failures are mainly manifested in the following forms:

(1) Open circuit or short circuit of the wire;

(2) The address decoder cannot address correctly;

(3) Multiple writing;

(4) The data of one unit is affected by the data or read and write operations of other units and changes;

(5) It cannot be restored after writing, and the correct information cannot be obtained when reading out immediately;

(6) When the read amplifier reads a series of information x and then reads x', there is no correct response;

(7) FLASH cannot keep the written information.

Combining the basic structure and fault manifestation of FLASH, the following fault model can be obtained:

(1) Faults in the memory cell array:

①Stuck-at fault: The logic value of a unit does not change with any behavior of the unit, nor is it affected by other units. (S-A-1 or S-A-0);

②Stuck-open fault: a fault caused by an open circuit;

③Transition fault: at least one of the state transitions of 0->1 or 1->0 is not executed correctly;

④ Data-maintaining fault: the storage unit cannot maintain a logical value for a certain period of time;

⑤State coupling fault (Coupling fault): If and only when unit j is in a certain state y(y∈{0,1}), unit i is always a certain value x(x∈{0,1} ), then unit i is said to be coupled to unit j. The coupling relationship does not necessarily have symmetry, that is, unit i is coupled to unit j, not necessarily unit j is also coupled to unit I.

⑥ Multiple access fault: Writing x (x∈{0, 1}) to unit i causes unit j to also write x, and ⑥ means unit i has multiple access faults. Multiple write failures are not necessarily symmetrical.

(2) Faults in the address decoding circuit:

①No storage unit is selected;

②Select the selected unit and select other units.

Faults in the decoder can be equivalent to faults in the memory cell array. Fault ① is equivalent to a fixed open circuit fault, and fault ② is equivalent to a multiple write fault.

(3) Faults in the read and write logic:

① One or more fixed logic faults in the input and output wires;

② One or more fixed open circuit faults in the buffer or latch;

③ State coupling failure between any two bits in the buffer or latch.

Faults in the read-write logic circuit can also be equivalent to faults in the memory cell array. Fault ① is equivalent to a fixed logic fault, fault ② is equivalent to a fixed open-circuit fault, and fault ③ is equivalent to a state coupling fault.

From the above analysis, we can know that the test of FLASH is equivalent to the internal unit test of FLASH, and the internal unit of FLASH mainly includes the following fault types: fixed logic fault, fixed open circuit fault, state transition fault, data retention fault, state coupling fault and multiple write failures.

Now commonly used test methods are all read and write word by word, without taking into account the characteristics of this type of FLASH that supports write buffer operations and adopt effective test methods to improve test efficiency. According to the conventional test method, the test method of reading and writing word by word is very inefficient, and it may take tens of minutes or even more than an hour to perform a complete test on a FLASH chip. By using the characteristics of the write buffer, the test time can be controlled within a few minutes, which can better meet the requirements of test efficiency.

To use the write buffer of FLASH for testing, it is necessary to consider the special mode of batch processing, and combine the characteristics of FLASH itself to design effective test data.

Contents of the invention

In view of the above-mentioned shortcomings of the prior art, the present invention provides a method for testing the internal unit of FLASH that supports write buffering, and under the premise of ensuring the test efficiency, relatively complete test coverage for FLASH faults is carried out.

The FLASH internal unit test method that supports write buffering provided by the present invention comprises the following steps: first erase the entire chip of FLASH that supports write buffering, then perform a write operation in the manner of writing a buffer, and fill the entire buffer once. The write operation is to write the data blocks of cycle step 0 in order of addresses. After all internal units are written, read back the data stored in each data unit and verify it with the written data.

The order by address is from the lowest address to the highest address or from the highest address to the lowest address.

In the data block of cycle step 0, the data of each row is all 1 except for one bit which is 0, and the position of 0 is sequentially moved and cycled.

The position of the 0 is that the data of the next row is shifted left by one or more bits or shifted right by one or more bits than the data of the previous row.

By constructing the above-mentioned specific test data, the present invention can improve the fault coverage rate of the test, especially improve the detection ability of multiple writing faults and basic coupling faults.

Detailed ways

Some FLASH devices (such as 28F160S5 and 28F320S5, 28F128J3A, 28F320J3A and 28F640J3A, 28F320J5 and 28F640J5, etc.) support the read and write mode of the write buffer (Write Buffer). Using the Write Buffer technology to write FLASH can significantly improve the test speed of FLASH, but because The writing method of Write Buffer is very different from the ordinary writing method, so the test method is also different.

Because one buffer is written at a time, the writing speed is doubled. Therefore, the following methods can be used to test the FLASH that supports write buffering:

First erase the entire chip, then start from the lowest (or highest) address and end at the highest (or lowest) address, write the data of step 0 in sequence, after all writing is completed, then read it back for verification. The write operation is performed through the Write Buffer. Since the written data is the process of the number "0" cyclically moving, this test method is named "Cycle Walking 0 Algorithm" here.

Now for example, assuming that the address space is from 0000 to 1111 and the data line is 3 bits, the data table is written as follows:

  Test address data input 0000 110 0001 101 0010 011 0011 110 0100 101 0101 011 0110 110 0111 101 1000 011 1001 110 1010 101 1011 011 1100 110 1101 101 1110 011 1111 110

The characteristic of this test method is that when performing the write FLASH operation, it is carried out in the way of writing the buffer, and the written data block is a data block of cycle step 0, that is, each row of data except one bit is 0, and the rest of the bits are all 1 , where the position of 0 is not fixed, but in the form of sequential movement and circular walking.

In the above example, the position of 0 is that the data in the next row is shifted to the left one bit at a time compared with the data in the previous row. In actual operation, it is not limited to this. Shift only one bit at a time, or two or more bits at a time.

The present invention can effectively detect the short-circuit fault of the adjacent unit because of adopting the walking 0 algorithm. Because the characteristics of the FLASH device itself are: only the number "0" can be written, the number "1" cannot be written, and it can only be "1" after erasing, so in the process of constructing test data, more "1" and "1" appear. A small amount of "0", and the position of "0" is changed, so that more faults that cause "1" to be wrongly written as "0" due to short circuit can be detected.

Claims (6)

1. the FLASH internal element method of testing of buffering is write in a support, comprise the following steps: that earlier the FLASH that supports to write buffering is carried out full wafer to be wiped, carry out write operation by the mode of compose buffer then, once write completely whole buffering area, described write operation is the data block that writes circulation walking 0 by sequence of addresses, after all internal elements had been write, the data of storing in each data cell of reading back were again carried out verification with the data that write.

2. the FLASH internal element method of testing of buffering is write in support as claimed in claim 1, it is characterized in that: described is to be undertaken by the order that begins from lowest address to location end superlatively by sequence of addresses.

3. the FLASH internal element method of testing of buffering is write in support as claimed in claim 1, it is characterized in that: described is to carry out to the order that lowest address finishes by beginning from location superlatively by sequence of addresses.

4. the FLASH internal element method of testing of buffering is write in support as claimed in claim 1, it is characterized in that: the data block of described circulation walking 0, data of its each row are 0 except one, and everybody be 1 entirely other, and wherein 0 position is that order moves, the circulation walking.

5. the FLASH internal element method of testing of buffering is write in support as claimed in claim 4, it is characterized in that: it is one or more that described 0 position is that the next line data move to left than lastrow data.

6. the FLASH internal element method of testing of buffering is write in support as claimed in claim 4, it is characterized in that: described 0 position is that the next line data are more one or more than lastrow data shift right.