CN100378951C - Method for manufacturing via-first dual damascene - Google Patents

Abstract

A method for manufacturing via-first dual damascene comprises providing a semiconductor substrate having a dielectric layer formed thereon, including via openings; filling a gap-filling polymer layer in the via hole; back-etching the gap-filling polymer layer to a predetermined depth to form a polymer plug in the via hole, wherein the exposed surface of the polymer plug is lower than the upper surface of the dielectric layer, thereby forming a concave hole; forming a photoresist layer on the dielectric layer, wherein the recess hole is filled with the photoresist layer; performing a photolithography process to form a trench conductive line pattern in the photoresist layer directly above the via opening, wherein the trench conductive line pattern has a first section not overlapping with the via opening, the first section has a fixed line width, and a second section with a gradually reduced line width overlapping with the via opening; the dielectric layer is etched through the trench conductive line pattern using the photoresist layer as an etching mask.

Description

Via Priority Dual Damascene Fabrication Method

technical field

The invention relates to a dual damascene process, in particular to a via-first dual damascene manufacturing method, which can solve the gap between two adjacent via holes caused by etching trench wire patterns. The bridging (bridging) problem.

Background technique

Copper dual damascene (dual damascene) technology with low dielectric constant dielectric layer has become a high-integration, high-speed (high-speed) logic integrated circuit chip manufacturing and for deep sub-micron (deep sub-micro) semiconductor technology below 0.18 microns The best metal interconnection solution. This is due to the low resistance value of copper (30% lower than aluminum) and the preferred anti-electromigration resistance (electromigration resistance), while the low dielectric constant material can help reduce the RC delay (RC delay) between metal wires, by It can be seen that the copper metal dual damascene interconnection technology is becoming more and more important in the integrated circuit technology.

Dual damascene manufacturing methods basically include the so-called trench-first dual damascene, via-first dual damascene, partial-via dual damascene, and self-aligned ( self-aligned) double mosaic and other options. Among them, the via-first dual damascene simply means using multiple photolithography and etching steps to first define the via hole, and then define a trench above the via hole to form an integrated dual damascene structure.

Please refer to FIG. 1 to FIG. 5 , which are schematic cross-sectional views of a conventional via-preferential dual-damascene manufacturing method. As shown in FIG. 1 , the conventional method first provides a semiconductor substrate 100 on which conductive structures 111 and 112 , such as copper damascene wires, are formed in the bottom layer or device layer 101 . Next, a protective capping layer 115 is sequentially deposited on the semiconductor substrate 100, and its composition is usually silicon nitride, covering the exposed surfaces of the conductive structures 111 and 112, and a stacked dielectric layer 120, which usually includes A first dielectric layer 121 , a second dielectric layer 123 , and an etch stop layer 122 between the first dielectric layer 121 and the second dielectric layer 123 . On the first dielectric layer 121, a silicon oxynitride (SiNO) stop layer 130 is then deposited.

Next, a first photoresist layer (also referred to as “via hole photoresist”) 140 is formed on the silicon oxynitride stop layer 130, and a via is defined in the first photoresist layer 140. The via holes 141 and 142, wherein it is assumed that the via hole 141 is an isolated via pattern, that is, there are no other via hole patterns defined around it, and the via hole 142 is a dense pattern. Via pattern. Next, perform an etching process, use the first photoresist layer 140 as an etching mask, and sequentially etch the silicon oxynitride stop layer 130, The dielectric layer 120 is stacked until the protective cap layer 115 to form via holes 151 , 152 a and 152 b.

As shown in FIG. 2 , after removing the first photoresist layer 140 , a gap-filling polymer layer 200 is coated on the semiconductor substrate 100 to fill the via holes 151 , 152 a and 152 b. The coating of the gap-filling polymer layer 200 is similar to the general photoresist coating process, and can be baked and hardened.

As shown in FIG. 3 , an etch-back process is then performed to etch back the gap-filling polymer layer 200 to a predetermined depth, so that polymer plugs 201, 202a and 202b are formed in the via holes 151, 152a and 152b respectively, And the surface of the gap-filling polymer layer 200 is lower than the silicon oxynitride stop layer 130 to form concave holes 301 , 302 a and 302 b. As shown in FIG. 4 , the conventional method then coats a second photoresist layer 400 on the semiconductor substrate 100 and fills the cavities 301 , 302 a and 302 b.

As shown in FIG. 5 , an exposure process is then performed, using a photomask defining the grooved wire pattern, and using a predetermined exposure light source to expose the grooved wire pattern above the concave holes 301 , 302 a and 302 b respectively. Subsequently, the exposed photoresist is removed by using a developing solution, so as to form trench wire patterns 411 , 412 a and 412 b above the concave holes 301 , 302 a and 302 b respectively.

Please refer to FIG. 6, which depicts a top view of the trench pattern formed in the second photoresist layer 400 and the via hole formed in the dielectric layer in FIG. 5, and FIG. Follow the section seen by the tangent line I-I in Fig. 6. As shown in FIG. 5 and FIG. 6, the line width L of the trench wire pattern 412a is approximately equal to the diameter of the via hole 152a below it, and the line width L of the trench wire pattern 412b is approximately equal to the diameter of the via hole 152b below it. size. The line width of the trench wire pattern 411 is obviously larger than the diameter of the via hole 151 below it.

The disadvantage of the above-mentioned prior art is that when the second photoresist layer 400 is used as an etching mask to perform the etching process of the wiring trench on the stacked dielectric layer 120, the first exposed holes 301, 302a and 302b will be exposed. A dielectric layer 121 will also be etched laterally at the same time. Since the via hole 152a and the via hole 152b are very close to each other, it is likely to be found between the via hole 152a and the via hole 152b after the subsequent copper chemical mechanical polishing. bridging problem.

Contents of the invention

The main purpose of the present invention is to provide an improved via-first dual damascene manufacturing method to solve the above-mentioned problem of bridging between vias in the prior art.

To achieve the above purpose, a preferred embodiment of the present invention provides a via-preferred dual damascene manufacturing method, which includes the following steps:

providing a semiconductor substrate on which a dielectric layer is formed, wherein the dielectric layer includes a via hole;

filling a gap-filling polymer layer in the via opening;

Etching back the gap-filling polymer layer to a predetermined depth, forming a polymer plug in the via hole, and the exposed surface of the polymer plug is lower than an upper surface of the dielectric layer, thereby forming a concave hole;

forming a photoresist layer on the dielectric layer, and the photoresist layer fills the concave hole;

performing a photolithography process to form a trench line pattern in the photoresist layer directly above the via hole, wherein the trench line pattern has a first segment, and the line width of the first segment is fixed as L, and the second segment whose line width is tapered and overlaps with the via hole; and

Using the photoresist layer as an etch mask, the dielectric layer is etched through the trench wire pattern.

In order to further understand the features and technical content of the present invention, please refer to the following detailed description and accompanying drawings of the present invention. However, the drawings are for reference and illustration only, and are not intended to limit the present invention.

Description of drawings

1 to 5 are schematic cross-sectional views of a conventional via-preferential dual damascene manufacturing method.

FIG. 6 is a schematic top view of the trench pattern formed in the second photoresist layer and the via hole formed in the dielectric layer in FIG. 5 .

7 to 12 are schematic cross-sectional views of a via-preferred dual damascene manufacturing method according to a preferred embodiment of the present invention.

FIG. 13 is a schematic top view of the trench pattern formed in the second photoresist layer and the location of the via hole formed in the stack dielectric layer in FIG. 11 .

FIG. 14 is a schematic diagram of a photomask layout used to form the photoresist trench pattern as shown in FIG. 13 .

FIG. 15 is a schematic top view of the dual damascene structure formed in the stacked dielectric layer after the chemical mechanical polishing process in FIG. 12 is completed.

simple notation

100 Semiconductor substrate 101 Bottom layer or element layer

111, 112 Conductive structure 115 Protective cover

120 stack dielectric layers

121 first dielectric layer 122 etch stop layer

123 Second dielectric layer 130 Silicon oxynitride stop layer

140 First photoresist layer 141, 142 Via opening

151, 152a/b Interlayer hole 200 Filling polymer layer

201, 202a/b polymer plug

301, 302a/b Recessed hole 400 Second photoresist layer

411, 412a/b grooved wire pattern

500 photomask layout

511 Translucent Line Area 512a/b Translucent Line Area

532a/b Opaque correction area 525 Opaque area

700 Semiconductor substrate 701 Bottom layer or component layer

711, 712 Conductive structure 715 Protective cover

720 stack dielectric layers

721 First Dielectric Layer 722 Etch Stop Layer

723 Second Dielectric Layer 730 Silicon Oxynitride Stop Layer

740 First photoresist layer 741, 742 Via opening

751, 752a/b Interfacial hole 800 Filling polymer layer

801, 802a/b polymer plug

901, 902a/b Recessed hole 911, 912a/b Via sidewall

1000 second photoresist layer 1011, 1012a/b trench wire pattern

1200 The first section 1300 The second section

1401 Via Plug 1402a/b Via Plug

1410 dual damascene structure 1412a/b dual damascene structure

1600 The first section 1700 The second section

Detailed ways

Please refer to FIG. 7 to FIG. 12 , which are schematic cross-sectional views of a via-preferred dual damascene manufacturing method according to a preferred embodiment of the present invention. As shown in FIG. 7 , firstly, a semiconductor substrate 700 is provided, on which conductive structures 711 and 712 , such as copper damascene wires, are formed in the bottom layer or device layer 701 . The bottom layer or component layer 701 may be a low dielectric constant layer, but is not limited thereto. Next, a protective capping layer 715 is sequentially deposited on the semiconductor substrate 700 , and its composition is usually silicon nitride, covering the exposed surfaces of the conductive structures 711 and 712 .

Similarly, a stacked dielectric layer 720 is then formed on the protection cap layer 715, which generally includes a first dielectric layer 721, a second dielectric layer 723, and a layer between the first dielectric layer 721 and the second dielectric layer. The dielectric constants of the etch stop layer 722 between the dielectric layers 723 , the first dielectric layer 721 and the second dielectric layer 723 are generally less than 3, preferably. For example, the first dielectric layer 721 and the second dielectric layer 723 may be FLARE ^TM , SiLK ^TM , poly(arylene ether) polymers, parylene compounds, polyimide ( polyimide) polymers, fluorinated polyimide, HSQ, BCB, fluorosilicate glass (FSG), silicon dioxide, porous silica glass (nanoporoussilica) or Teflon, etc., but not limited to the above listed composition.

In FIG. 7 , a silicon oxynitride (SiNO) stop layer 730 is then deposited on the first dielectric layer 721 . Next, a first photoresist layer (also referred to as “via hole photoresist”) 740 is formed on the silicon oxynitride stop layer 730, and a via is defined in the first photoresist layer 740. The via openings 741 and 742, where it is assumed that the via hole 741 is an isolated via pattern, that is, there are no other via hole patterns defined around it, and the via hole 742 is a dense pattern. Via pattern. Next, an etching process is performed, using the first photoresist layer 740 as an etching mask, and sequentially etching the silicon oxynitride stop layer 730, The dielectric layer 720 is stacked until the protective cap layer 715 to form via holes 751, 752a and 752b with a diameter of approximately 0.08-0.2 microns.

As shown in FIG. 8 , after removing the first photoresist layer 740 , a gap-filling polymer layer 800 is coated on the semiconductor substrate 700 to fill the via holes 751 , 752 a and 752 b. The gap-filling polymer layer 800 can be made of I-line photoresist, such as containing novolak resin, polystyrene resin (poly hydroxystyrene, PHS), or acrylate (acrylate) etc. i-line photoresist Resist ingredients. The coating of the gap-filling polymer layer 800 is similar to the general photoresist coating process, and can be baked and hardened.

As shown in FIG. 9, an etch-back process is then performed to etch back the gap-filling polymer layer 800 to a predetermined depth, so that polymer plugs 801, 802a and 802b are formed in the via holes 751, 752a and 752b respectively, And the surface of the etched gap-filling polymer layer 800 is lower than the silicon oxynitride stop layer 730 to form concave holes 901 , 902 a and 902 b. The recesses 901, 902a and 902b are respectively formed by the exposed sidewalls 911, 912a and 912b of the via holes 751, 752a and 752b and the corresponding upper surfaces of the polymer plugs 801, 802a and 802b. As shown in FIG. 10 , a second photoresist layer (also referred to as “trench photoresist”) 1000 is then coated on the semiconductor substrate 700 to fill the concave holes 901 , 902 a and 902 b.

As shown in FIG. 11 , an exposure process is then performed, using a photomask (as shown in FIG. 14 ) defining a trench wire pattern to expose trenches on the top of the concave holes 901, 902a and 902b respectively with a predetermined exposure light source. Slotted wire pattern. Subsequently, the exposed photoresist is removed by using a developing solution, so as to form trench wire patterns 1011 , 1012a and 1012b above the concave holes 901 , 902a and 902b respectively. The main feature of the present invention is that after development, part of the sidewalls 912a and 912b of the two adjacent concave holes 902a and 902b are covered by the second photoresist layer 1000, in order to protect the space between the adjacent two concave holes 902a and 902b. The first dielectric layer 721 prevents it from being corroded in subsequent trench etching.

Please refer to FIG. 11 and FIG. 13 at the same time, wherein FIG. 13 shows the trench pattern formed in the second photoresist layer 1000 in FIG. 11 and the position of the via holes formed in the stack dielectric layer. As a schematic diagram, FIG. 11 is a cross-section viewed along the tangent line II-II in FIG. 13 . As shown in FIG. 11 and FIG. 13 , the line width of the trench wire pattern 1011 is obviously larger than the diameter of the via hole 751 below it. According to a preferred embodiment of the present invention, the trench wire pattern 1012a or 1012b is further divided into a first segment 1200 that does not overlap with the underlying via hole, which has approximately the same line width L, and the line width is tapered. The second section 1300 of , which is directly above the via hole.

Please refer to FIG. 14 , which is a schematic diagram of a photomask layout used to form the photoresist trench pattern as shown in FIG. 13 . The photomask layout 500 includes an opaque region 525, a light-transmitting line region 511 for exposing the trench line pattern 1011 in the second photoresist layer 1000, and a light-transmitting line region 511 for exposing the trench line pattern 1011 in the second photoresist layer 1000. In the second photoresist layer 1000 , the light-transmitting line region 512 a for exposing the groove-line pattern 1012 a and the light-transmitting line region 512 b for exposing the groove-line pattern 1012 b in the second photoresist layer 1000 . The line width of the light-transmitting line region 512a is equal to the size of the via hole 752a, and the line width of the light-transmitting line region 512b is equal to the size of the via hole 752b. The via holes 752a and the via holes 752b are close to each other, forming a dense via hole pattern with a small pitch. In the region directly above the via hole 752a, a pair of opaque correction regions 532a are deliberately used to retract the light-transmitting line region 512a, and a pair of opaque correction regions are used in the region directly above the via hole 752b. 532b corrects the shrinkage of the light-transmitting line region 512b.

According to a preferred embodiment of the present invention, the size of the correction region 532a and the correction region 532b are equal, each correction region is a rectangle and represented by a side length 1 and a side width w, wherein the side length 1 of each correction region must be equal to or greater than the via The diameter size of the hole, and the side width w of each correction area is recommended to be 5%-30% of the side length 1 is the best. Taking a via hole with a diameter of 0.2 μm as an example, the size of each modified region may be about 200 nm (minimum side length)×10 −60 nm (side width).

As shown in FIGS. 11 to 13 , using the second photoresist layer 1000 as an etching mask, a dry etching process is performed to etch a conductive trench in the first dielectric layer 721 through the trench line patterns 1011, 1012a and 1012b. Groove structure. Then remove the remaining photoresist layer and remove the protective cover layer 715 at the bottom of the via hole, then fill the wire trench structure and the via hole with metal, and then perform a chemical mechanical polishing process to form a double layer. The damascene structures 1410, 1412a and 1412b. The dual damascene structure 1410 includes a via plug 1401 , the dual damascene structure 1412 a includes a via plug 1402 a , and the dual damascene structure 1412 b includes a via plug 1402 b.

Please refer to FIG. 15 , which is a schematic top view of the dual damascene structures 1410 , 1412 a and 1412 b formed in the stacked dielectric layers after the chemical mechanical polishing process in FIG. 12 . As shown in FIG. 15, the present invention is characterized in that the dual damascene structures 1412a and 1412b can also be divided into a first segment 1600 that does not overlap with the underlying via hole, which has approximately equal line width L, and the line width exhibits The irregularly concave second section 1700 is directly above the via hole.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (14)

1. the manufacture method of the preferential dual damascene of interlayer hole comprises:

The semiconductor substrate is provided, is formed with a dielectric layer on it, wherein this dielectric layer comprises an interlayer hole perforate;

In this interlayer hole perforate, fill up a joint filling macromolecule layer;

This joint filling macromolecule layer one desired depth of etch-back forms a macromolecule plug in this interlayer hole perforate, and the exposed surface of this macromolecule plug is lower than a upper surface of this dielectric layer, forms a shrinkage pool by this;

On this dielectric layer, form a photoresist layer, and this photoresist layer fills up this shrinkage pool;

Carry out a photoetching process, to form a groove wire pattern in this photoresist layer directly over this interlayer hole perforate, wherein this groove wire pattern has first not overlapping with this an interlayer hole perforate section, and the live width of this first section is fixed as L, and a live width presents gradually-reducing shape and second section overlapping with this interlayer hole perforate; And

With this photoresist layer as etch shield, via this this dielectric layer of groove wire pattern etching.

2. the manufacture method of the preferential dual damascene of interlayer hole as claimed in claim 1, wherein this dielectric layer comprises lower floor's dielectric layer, the etching stopping layer of a upper strata dielectric layer and between this lower floor's dielectric layer and this upper strata dielectric layer.

3. the manufacture method of the preferential dual damascene of interlayer hole as claimed in claim 1, wherein this joint filling macromolecule layer comprises the I-line photoresist.

4. the manufacture method of the preferential dual damascene of interlayer hole as claimed in claim 1 wherein ought be with this photoresist layer as etch shield, and during via this this dielectric layer of groove wire pattern etching, a sidewall sections of this shrinkage pool is covered in by this photoresist layer.

5. the manufacture method of the preferential dual damascene of interlayer hole as claimed in claim 2, wherein this lower floor's dielectric layer and upper strata dielectric layer have one less than 3 dielectric constant.

6. the manufacture method of the preferential dual damascene of interlayer hole as claimed in claim 1 wherein is formed with a cap rock in addition on this dielectric layer.

7. the manufacture method of the preferential dual damascene of interlayer hole as claimed in claim 6, wherein this cap rock comprises silicon oxynitride.

8. the manufacture method of the preferential dual damascene of interlayer hole comprises:

The semiconductor substrate is provided, is formed with a dielectric layer on it, wherein this dielectric layer comprises one first interlayer hole perforate and the one second interlayer hole opening near each other with this first interlayer hole perforate;

In first and second this interlayer hole perforate, fill up a joint filling macromolecule layer;

This joint filling macromolecule layer one desired depth of etch-back, respectively at forming one first macromolecule plug in this first interlayer hole perforate, in this second interlayer hole perforate, form one second macromolecule plug, and the exposed surface of this first and second macromolecule plug is lower than a upper surface of this dielectric layer, forms one first shrinkage pool and one second shrinkage pool by this;

On this dielectric layer, form a photoresist layer, and this photoresist layer fills up this first shrinkage pool and this second shrinkage pool;

Carry out a photoetching process, to form one first groove wire pattern in this photoresist layer directly over this first interlayer hole perforate, and formation one second groove wire pattern in this photoresist layer directly over this second interlayer hole perforate, wherein this first groove wire pattern has first not overlapping with this first an interlayer hole perforate section, and the live width of this first section is fixed as L, and a live width presents gradually-reducing shape and second section overlapping with this first interlayer hole perforate; And

With this photoresist layer as etch shield, via this first and second this dielectric layer of groove wire pattern etching.

9. the manufacture method of the preferential dual damascene of interlayer hole as claimed in claim 8, wherein this dielectric layer comprises lower floor's dielectric layer, the etching stopping layer of a upper strata dielectric layer and between this lower floor's dielectric layer and this upper strata dielectric layer.

10. the manufacture method of the preferential dual damascene of interlayer hole as claimed in claim 9, wherein this lower floor's dielectric layer and upper strata dielectric layer have one less than 3 dielectric constant.

11. the manufacture method of the preferential dual damascene of interlayer hole as claimed in claim 8 wherein also is formed with a cap rock on this dielectric layer.

12. the manufacture method of the preferential dual damascene of interlayer hole as claimed in claim 11, wherein this cap rock comprises silicon oxynitride.

13. the manufacture method of the preferential dual damascene of interlayer hole as claimed in claim 8, wherein this joint filling macromolecule layer comprises the I-line photoresist.

14. the manufacture method of the preferential dual damascene of interlayer hole as claimed in claim 8, wherein this live width L equals the diameter of this first interlayer hole opening.

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