CN100388349C - Power saving method for liquid crystal display - Google Patents

Abstract

A power saving method of a liquid crystal display is used for reducing the power consumption of a plurality of source drivers. The power saving method firstly awakens the source drivers, and then (b) transmits image data and control signals of a time schedule controller to the two farthest starting source drivers at the two corresponding sides of the flexible circuit board through the corresponding source drivers of the flexible circuit board. And then, (c) switching the farthest starting source drivers on two sides corresponding to the flexible circuit board into a power-saving mode. And repeating the steps b and c until all the source drivers of the flexible circuit board are switched into the power-saving mode.

Description

Power saving method for liquid crystal display

technical field

The present invention relates to a liquid crystal display, and in particular to a liquid crystal display adopting a Chip On Glass (COG) package.

Background technique

In view of advantages such as lightness, thinness and low radiation, liquid crystal displays have gradually replaced cathode ray tube (CRT) displays and become the mainstream of computer screens and televisions. In addition to improving the display quality of LCDs, such as color, contrast, and brightness, manufacturers are also committed to improving their production technology to speed up the production process and reduce production costs.

A liquid crystal display uses a timing controller, a source driver and a gate driver to drive a liquid crystal panel. The traditional timing controller, source driver and gate driver are soldered to a printed circuit board (Printed Circuit Board, PCB), and then electrically connected to the LCD panel through a flexible printed circuit board (FPC). Therefore, a traditional liquid crystal display needs at least three printed circuit boards, and its production process is relatively complicated. With the advancement of technology, manufacturers have developed LCDs using Chip On Glass (COG) packaging to simplify the production process.

Figure 1 is a schematic diagram of a traditional LCD display using Chip On Glass (COG). The liquid crystal display 100 includes a panel 110 , a plurality of source drivers 112 , at least one gate driver 114 , a printed circuit board 120 and a flexible circuit board 130 . These source drivers 112 and gate drivers 114 are disposed on the glass substrate of the panel 110 , and are electrically connected to the printed circuit board 120 through corresponding flexible circuit boards 130 . A timing controller (not shown) is disposed on the printed circuit board 120 to receive image data and control signals, and then transmit them to individual source drivers 112 and gate drivers 114 through the flexible circuit boards 130 after processing.

However, traditional Chip On Glass (COG) LCDs require more flexible circuit boards. For example, the example in Figure 1 requires 11 pieces, and the production process still needs to be simplified. . In addition, in addition to simplifying the production process, reducing the number of flexible circuit boards can also reduce the number of contacts between the flexible circuit board and the LCD panel, thereby reducing the probability of failure.

Contents of the invention

In view of this, the purpose of the present invention is to provide a liquid crystal display with chip-on-glass packaging, which can use a small number of flexible circuit boards to achieve the purpose of data transmission.

In addition, the present invention also proposes a method for generating a gate control signal, so as to further reduce the number of flexible circuit boards.

In addition, in conjunction with the liquid crystal display of the present invention, the present invention also proposes a source driver identification method.

In addition, in conjunction with the liquid crystal display of the present invention, the present invention also provides a source driver for unidirectional or bidirectional transmission of image data and control signals received from the timing controller.

In addition, in conjunction with the liquid crystal display of the present invention, the control signal can also be integrated into a small number or a single wire by using the packet transmission technology, so as to further reduce the number of wires on the flexible circuit board.

In addition, the present invention also proposes a power management mechanism to reduce the power consumption of the liquid crystal display.

According to the object of the present invention, a power saving method of a liquid crystal display is proposed to reduce the power consumption of multiple source drivers. The source drivers are arranged in series on the glass substrate of the liquid crystal display, and the liquid crystal display has at least one flexible circuit board connected to the corresponding source driver to transmit the image data and control signals of a timing controller, and the corresponding source driver bidirectionally transmits to adjacent source drivers. The power saving method first (a) wakes up these source drivers, and then (b) transmits the image data and control signals of the timing controller to the remotest Turn on the source driver. Then, (c) switching the most remote open source drivers on the corresponding two sides of the flexible circuit board to a power saving mode. Repeat steps b and c until all source drivers of the flexible printed circuit are switched to power-saving mode.

According to another object of the present invention, a power saving method for a liquid crystal display is proposed. The power saving method first (a) switches all the source drivers to the power saving mode, and then (b) transmits the image data and control signals of the timing controller to the corresponding source drivers of the flexible circuit board, and wakes up the corresponding source drivers pole drive. Then, (c) transmitting the image data and control signals of the timing controller to the closest closed source drivers corresponding to the source driver, and waking up the nearest closed source drivers. Repeat step (c) until all the source drivers wake up.

Description of drawings

Figure 1 is a schematic diagram of a conventional LCD using glass-on-chip packaging.

FIG. 2A is a schematic diagram of a liquid crystal display using chip-on-glass packaging according to a preferred embodiment of the present invention.

FIG. 2B is a schematic diagram of another LCD using chip-on-glass packaging according to a preferred embodiment of the present invention.

FIG. 3 is a schematic diagram of the control signals of the driver of the liquid crystal display.

FIG. 4 is a schematic diagram of the format of the control signal packet.

FIG. 5A is a block diagram of a source driver according to a preferred embodiment of the present invention.

FIG. 5B is a block diagram of the waveform generator of the source driver of FIG. 5A.

FIG. 5C is a block diagram of the identifier of FIG. 5B.

FIG. 5D is a schematic diagram of a waveform for generating the control signal POL.

FIG. 5E is a schematic waveform diagram of generating the control signal TP.

FIG. 6A is a schematic diagram of a convergent data transmission method capable of saving power.

FIG. 6B is a schematic diagram of an explosive data transmission method that can save power.

[Description of main parts designation]

100, 200: LCD display

110, 210: panel

112, 212: source driver (S/D)

114, 214: gate driver

120, 220: PCB

130, 230, 232: FPCs

225: Timing controller

310: header field

312: Control field

314: data field

410, 412: Receiver

413, 415: Transceiver

414, 416: control transceiver

424, 426: data transceiver

420, 421: waveform generator

422: Bus Switcher

434: drive unit

451: Parser

453: Identifier

456: Comparison unit

460: Signal Generator

470: Initializer

Detailed ways

In order to make the above-mentioned purposes, features, and advantages of the present invention more comprehensible, a preferred embodiment is specifically cited below, and in conjunction with the accompanying drawings, the detailed description is as follows:

Please refer to FIG. 2A , which shows a schematic diagram of a liquid crystal display using Chip On Glass (COG) package according to a preferred embodiment of the present invention. The liquid crystal display 200 includes: a panel 210, a plurality of source drivers (Source Driver, S/D) 212(1)-211(10), at least one gate driver (Gate Driver) 214, a printed circuit board 220 and a flexible circuit board 230 and 232. The source driver 212 and the gate driver 214 are disposed on the glass substrate of the panel 210 . The timing controller 225 is disposed on the printed circuit board 220 to receive image data and control signals, and then transmit them to the source drivers 212(3) and 212(8) through flexible circuit boards (FPC) 230 and 232 after processing. The source drivers 212(3) and 212(8) then respectively transmit the received image data and source control signals to the adjacent source drivers 212(1), 212(2), 212(4) through the wires on the glass substrate. ), 212(5) and 212(6), 212(7), 212(9), 212(10). Based on the received source control signal, a source driver on the glass substrate, for example: the source driver 212(1) closest to the gate driver 214, can generate the gate control signal G to be provided to the gate driver 214 . Selecting the source driver 212 ( 1 ) closest to the gate driver 214 can effectively shorten the wire length with the gate driver 214 and avoid unnecessary signal delay and distortion. However, in other embodiments, other source drivers other than the source driver 212(1) can also be used to generate the gate control signal G. In this embodiment, since the liquid crystal display 200 uses wires on the glass substrate to transmit signals, there is no need to arrange multiple flexible circuit boards to correspond to each source driver and gate driver, so the number of flexible circuit boards required by the liquid crystal display 200 can be greatly reduced.

In this embodiment, the source driver 212 has a first mode and a second mode. The source drivers 212(3) and 212(8) are set to the first mode, which can simultaneously transmit data to the adjacent source drivers 212 to the left and right, and the other source drivers 212(1), 212( 2), 212(4)-212(7), 212(9) and 212(10) are set as the second mode, which can only transmit in one direction. The source drivers 212(3) and 212(8) in the first mode can respectively receive two sets of image data and control signals from the timing controller 225, and transmit the received image data and control signals to the left and right respectively. other source drivers. The source drivers 212(1), 212(2), 212(4)-212(7), 212(9) and 212(10) in the second mode can only receive the image data transmitted by the left or right source driver and The control signal is not directly electrically connected to the timing controller 225 . In this embodiment, since the liquid crystal display 200 is a large-scale liquid crystal display, taking 10 source drivers as an example, in view of the signal delay and distortion caused by the parasitic resistance and capacitance of the wires on the glass substrate, this embodiment can use two flexible The circuit boards 230 and 232 transmit data. However, the number of flexible circuit boards can be adjusted according to the actual design of the liquid crystal display, and is not limited to two flexible circuit boards, as long as the signal delay and distortion caused by the parasitic resistance and capacitance of the wires on the glass substrate remain within an acceptable range.

In this embodiment, the source driver 212 of the liquid crystal panel can be divided into two groups of left source drivers 212(1)-212(5) and right source drivers 212(6)-212(10), two flexible circuits Boards 230 and 232 are respectively electrically connected to the central source drivers 212(3) and 212(8) of the two groups of source drivers, so that the signal delay and distortion caused by the parasitic resistance and capacitance of the wires on the glass substrate can be eliminated. effectively minimized. Similarly, based on the actual design of the liquid crystal display, the source drivers 212 of the liquid crystal panel can also be divided into more than three groups, and more than three flexible circuit boards can also be electrically connected to the range of each group of source drivers, as long as The signal delay and distortion caused by the parasitic resistance and capacitance of the wires on the glass substrate can be kept within an acceptable range.

FIG. 2B is a schematic diagram of a liquid crystal display 250 using a Chip On Glass (COG) package according to another preferred embodiment of the present invention. The difference between the LCD 250 and the LCD 200 in FIG. 2A is that the right end of the panel 210 further has another gate driver 216 for driving from both ends of each scan line. The rest of the components are the same as those in FIG. 2A , and will not be repeated here.

FIG. 3 is a schematic diagram of the control signals of the driver of the liquid crystal display. The control signal can be divided into a gate control signal G and a source control signal S. For example, the gate control signal G includes a gate driver start signal STV (Gate Driver Start Signal) to indicate the start of a frame, a gate clock signal CPV (Gate Clock Signal) to enable the gate lines, and gate The driver outputs the enable signal OEV (Gate Driver Output Enable Signal) to define the enable time of the gate line. In addition, for example, the source control signal S includes a source driver start signal STH (Source Driver Start Signal) so that the source driver 212 starts to prepare to display a horizontal line, and a data enable signal DE (Data Enable Signal) to start receiving data , a load signal TP (Load Signal) to enable the source driver 212 to output a driving voltage to the data line, and a polarity control signal POL to control polarity inversion.

When the source driver start signal STH is enabled, the source driver 212 starts to prepare to receive data. After a period td1 , the data enable signal DE turns to a high level, and the timing controller 225 starts to output image data to the source driver 212 . The source driver 212 determines the polarity according to the polarity control signal POL, so as to generate output voltages with different polarities. Then, the load signal TP is enabled to enable the source driver 212 to start outputting the driving voltage to the panel 210 .

In the conventional liquid crystal display 100 , the control signals are sent by the timing controller to each source driver 112 and gate driver 114 . The existing control signal transmission method uses one wire to transmit one control signal, so many wires are needed to transmit these control signals. Moreover, since the wires from the timing controller to each source driver 112 and gate driver 114 have parasitic resistances and parasitic capacitances, the control signals are prone to delay and affect display quality.

In this embodiment, the timing controller 225 integrates these control signals into a control signal stream C, and transmits it to the source driver 212 via a wire. For example, the control signal flow C can use a packet transmission protocol to compress multiple control signals into independent control signal packets, so as to represent related events of each control signal and transmit them on the same wire. The timing controller 225 can use the DID signal to designate which source driver 212 the transmitted control signal packet should be sent to. For example, the DID signal can also be included in the control signal packet, so as to provide each source driver 212 to capture and compare. After receiving the control signal packet of the control signal flow C, the source driver 212 can decode the required control signal by itself. In this way, the wires required to transmit control signals can be significantly reduced.

Since the source driver 212 needs to identify whether the received control signal packet is for itself, each source driver also needs to have a built-in identification code signal for comparison with the destination identification code signal of the timing controller 225 .

[Transport protocol to control signal flow]

The existing control signal transmission method is to use one wire separately to transmit a control signal from the timing controller to the source driver and/or the gate driver. The source driver and the gate driver respectively need multiple control signals, so the timing control The number of wires from the device to each source driver and gate driver is large, so that there are many lines on the flexible circuit board (FPC), which increases the cost and instability. In addition, the parasitic resistance and parasitic capacitance caused by the long wire will also cause delay and distortion of the control signal and affect the display quality.

In this embodiment, the timing controller 225 transmits the control signal flow C to the source driver 212 through only one wire. Using the packet transmission technology, for example, the control signal stream C may include multiple control signal packets, and the content of each control signal packet may represent a pull high event or a pull low event of the corresponding control signal. After the source driver 212 receives the control signal packet, the corresponding control signal can be pulled high or low to generate various required control signals.

FIG. 4 is a schematic diagram of the format of the control signal packet. A control signal packet includes a header field 310 and a control item, wherein the control item includes a control field 312 and a data field 314 . The header field 310 records a predetermined pattern for identifying the start of a control signal packet. The predetermined pattern is represented by 0x11111, for example. The control field 312 is used to record the type of the event. The event types include at least a signal STH event, a signal TP event, a pull-high event, a pull-low event, and an initial setting event. The data field 314 is used to record the parameters of this event.

In this embodiment, taking each control signal packet has 16 bits as an example, if dual edge sampling (dual edge sampling) is used to receive the packet, the reading time of each control signal packet is 8 clocks, that is to say , the control signal generated by the pull-high event and the pull-low event needs at least 8 clocks of high-level maintenance time, such as control signals POL, CPV, STV, OEV can be generated by using the pull-high event and the pull-low event. In addition, for control signals whose high-level maintenance time is less than 8 clocks, such as control signals STH and TP, the signal level can be pulled up after receiving the signal STH event and the signal TP event respectively, and the predetermined time period td2 and tw1 respectively That is, it turns to low level by itself. This case is not limited to the use of double-edge sampling, and can also use rising-edge or falling-edge sampling to receive packets, which will not be repeated here.

In terms of the control signal packet for recording the signal STH event in the control field 312, it is used to enable the control signal STH of each source driver 212(1)-212(10), and its data field 414 represents the control signal packet The destination identification code signal of the destination source driver 212 . For example, if the chip identification code signals of the source drivers 212(1)-212(10) are 0x0001-0x1010 respectively, when the source driver 212(1) receives the control signal packet and learns from its data field 414 After the destination identification code signal (ID) of the destination source driver is 0x0001, the source driver 212(1) with the same chip ID can generate the signal STH by itself to prepare to receive data to display horizontal lines. After the control signal STH is pulled high, it can automatically switch to a low level after a predetermined time period td2.

In addition, since the signals TP and CPV are pulled high at the same time, as far as the control signal packet of the control field 312 recording the signal TP event is concerned, it is used to enable the control signals TP and CPV, wherein the control signal TP is turned on after a predetermined period of time tw1 It can be automatically pulled to a low level, and the control signal CPV needs to receive a control signal packet that records the pull-down event of the CPV signal before being pulled to a low level.

The signals POL, STV, and OEV can be respectively generated by a control signal packet recording a pull-up event and a control signal packet recording a pull-down event. For the control signal packet in which the control field 312 records the pull-high event, the data field 314 is used to record the signal to be pulled high, such as the signal POL, STV or OEV. For the control signal packet in which the control field 312 records the pull-down event, the data field 314 is used to record the signal to be pulled low, such as the signal POL, STV or OEV.

As for the control signal packet in which the control field 312 records the initial setting event, it is used to set various initial setting values, for example, the output thrust of the source driver 212 and so on. The control signal packet can also record other types of events, which will not be described one by one here.

In this embodiment, the control signal flow C is used to transmit the packetized control signal, and at least one wire is required for transmission. Therefore, the number of wires for transmitting all control signals from the timing controller 225 to each source driver 212 can be greatly reduced, thereby simplifying circuit layout complexity and increasing product stability. In addition, in accordance with the bandwidth of the wire and the actual design, the control signal flow C can also selectively integrate only a part of the control signals and independently transmit the other part of the control signals. In this case, although all the control signals may not be integrated into one wire, the number of wires can still be reduced.

[Source driver]

FIG. 5A is a block diagram of a source driver according to a preferred embodiment of the present invention. The source driver 212 includes: receivers 410 , 412 , transceivers 413 , 415 , a bus switch 422 , waveform generators 420 , 421 and a driving unit 434 . The transceiver 413 includes: a control transceiver 414 and a data transceiver 424 , and the transceiver 415 includes: a control transceiver 416 and a data transceiver 426 .

The bus switch 422 includes two switches SW1 and SW2. When the source drivers, such as 212(3) and 212(8), are in the first mode, their bus switcher 422 will open the switches SW1 and SW2, so that the control transceiver 414 and the control transceiver 416 are disconnected, and the The data transceiver 424 is disconnected from the data transceiver 426, so the control signal stream C1 received by the receiver 410 is output to the control transceiver 414, and the image data D1 is output to the data transceiver 424; and the control signal stream C2 received by the receiver 412 is output to the control transceiver 416, and the image data D2 is output to the data transceiver 426.

When the source drivers, such as 212(1)-212(2), 212(4)-212(7), 212(9)-212(10), are in the second mode, the receivers 410 and 412 are disabled (di s abl ed), the bus switcher 422 will close the switches SW1 and SW2, so that the transceiver 413 is electrically connected with the transceiver 415, that is: the data transceiver 424 is electrically connected with the data transceiver 426, and controls the transceiver The controller 414 is electrically connected to the control transceiver 416. In this way, the control signal flow and image data received by the left or right control transceivers 414, 416 and data transceivers 424, 426 can be transmitted to the next source driver according to the designated direction.

Waveform generators 420, 421 respectively receive control signal streams C1, C2, and generate source control signals accordingly, such as STH(1), STH(2), POL(1), POL(2), TP(1), TP(2), etc., accordingly, the gate control signal G, such as CPV(1), CPV(2), STV(1), STV(2), OEV(1), OEV(2), etc. can be generated, Wherein, the gate control signal G can be generated by a selected source driver. Taking the liquid crystal display 200 in FIG. 2A as an example, a source driver 212 on the glass substrate, such as the source driver 212(1) closest to the gate driver 214, can be used to generate the gate control signal G, the source Other source drivers except the electrode driver 212(1) will not generate the gate control signal G. In addition, taking the liquid crystal display 250 in Fig. 2B as an example, the two source drivers on the glass substrate, for example, the source drivers 212(1) and 212(10) closest to the gates 214 and 216, can be respectively used To generate the gate control signal G to the gate drivers 214 and 216 , other source drivers except the source drivers 212 ( 1 ) and 212 ( 10 ) will not generate the gate control signal G.

When the driving unit 434 receives the control signal STH, it starts to lock the image data D, then converts the image data D into corresponding analog driving voltage according to the polarity signal POL, and then transmits the driving voltage to the panel 210 after receiving the load signal TP .

Taking the source driver 212(3) as an example, it is in the first mode, and the waveform generators 420 and 421 are activated at the same time, so as to respectively receive the control signal streams C1 and C2 and generate sources for transmitting the image data D1 and D2 pole control signal and gate control signal. At this time, the control signal streams C1 and C2 and the image data D1 and D2 are independent of each other. In addition, taking the source driver 212(2) or 212(4) as an example, which is in the second mode, both the waveform generators 420 and 421 can be turned off or one can be omitted. At this time, since the control signal streams C1, C2 and the image data D1 and D2 are connected to each other, no matter whether the control signal stream C is received by the waveform generator 420 or 421, the source driver 212(2) or 212(4) can be correct. A source control signal is generated, and a correct gate control signal is generated accordingly. In addition, in the second mode, the control signal flows C1 and C2 can also be set to be the same, and it is not necessary to close or omit one of the waveform generators.

Figure 5B is a block diagram of the waveform generator of Figure 5A. The waveform generator includes: a parser 451 , an identifier 453 , a signal generator 460 and an initial setter 470 . The parser 451 is used to receive the control signal stream C, so as to parse each control signal packet and distribute it to the identifier 453 , the signal generator 460 or the initializer 470 according to its control items. The control item of the control signal packet of the event with identity identification, in this example the signal STH event, is sent to the identity recognizer 453; ; The control item of the control signal packet with the initialization event is sent to the initialization device 470 ;

FIG. 5C is a block diagram of the identifier of FIG. 5B. The identifier 453 includes a comparison unit 456 . The chip identification code Idp of each source driver can be set externally, for example, by pulling up or pulling down the pins of the source driver 212 on the glass substrate to a specific level respectively. Each source driver 212 has a different chip ID IDp. The comparison unit 456 can compare the chip identification code IDp and the target identification code IDt decoded from the control signal flow C, and trigger the control signal STH when the two match, wherein the high level maintenance time td2 of the signal STH can be compared Unit 456 is preset.

As shown in Figure 5B, the signal generator 460 will pull up the corresponding control signal after receiving the control item in the control signal packet of the pull-high event, and the high level of the control signal will remain unchanged until the signal generator 460 receives The control item of the control signal packet of the pull-down event. FIG. 5D is a schematic diagram of a waveform for generating the control signal POL. When the control item of the control signal package of the pull-up event H of POL is received, a high-level signal PH will be generated; when the control item of the control signal package of the pull-down event L of POL is received, a low level will be generated The signal PL; the coupling of the signal PH and PL is the signal POL. Other control signals, such as CPV, STV, and OEV are also generated in the same manner.

However, in a preferred embodiment of the present invention, when the high-level maintenance time of the control signal is less than 8 clocks, such as the control signal TP, since the reading of each control signal packet is 8 clocks, the pull-up event and Pulling down events to generate control signals is not applicable. FIG. 5E is a schematic diagram of the waveform of the generated signal TP. When the pull-up event of the TP signal is received, a high-level signal TH is generated; then counting starts, and a low-level signal TL is generated until the preset period tw1 is counted; the coupling of the signals TH and TL is the signal TP .

The gate control signal can be generated according to the source control signal, such as STH or TP, in addition to using the pull-up event and the pull-down event as described above. Please refer to Figure 3. For example, in the example of generating the gate control signal according to STH, the method of generating the signal CPV is as follows: when the signal STH of the source driver (1) is enabled, its counter starts to count, and when the time period td6 is passed, the signal The CPV is pulled high, and then the signal CPV is pulled low after a time period tw4. The method for generating the signal STV is as follows: when the signal STH of the source driver (1) is enabled, its counter starts to count, when the time period td7 passes, the signal STV is pulled high, and after the time period tw5 passes, the signal STV is pulled low. The method for generating the signal OEV is as follows: when the signal STH of the source driver (1) is enabled, its counter starts to count, when the time period td8 passes, the signal OEV is pulled high, and after the time period tw6, the signal OEV is pulled low.

After the initial setter 470 receives the control item in the control signal packet of the initial setting event, it outputs the DC value accordingly to set the corresponding parameter.

Since the source driver can generate the source control signal by itself, it does not need to be generated by the timing generator and then transmitted to each source driver through wires as in the existing practice, so the transmission attenuation of the source control signal can be avoided.

In addition, the source driver can generate the gate control signal and directly transmit it to the gate driver. It is not necessary to pull a long wire from the timing controller to the gate driver as in the existing practice, so the timing controller can be omitted. gate driver leads and improve signal quality.

[Power Management]

FIG. 6A is a schematic diagram of a convergent data transmission method capable of saving power. In the convergent data transmission method, the image data is first transmitted to the remote source driver 212 , and then gradually transmitted to the closer source driver 212 . As shown in FIG. 2 , the following description will take the source drivers 212 ( 1 )˜ 212 ( 5 ) on the left side of the liquid crystal display as an example. First, in step 610, the timing controller 225 transmits the image data to the source drivers 212(1) and 212(5) farther away from the flexible circuit board 230, and then the source drivers 212(1) and 212(5) ) to enter the power-saving mode, such as turning off the power of the data transceivers 424 and 426. Next, in step 612, the timing controller 225 transmits the image data to the source drivers 212(2) and 212(4), and then the source drivers 212(2) and 212(4) enter the power saving mode. Next, in step 614, the timing controller 225 transmits the image data to the source driver 212(3), and then the source driver 212(3) enters the power saving mode. Next, each source driver 212 receives the load signal TP, and at this time each source driver 212 is woken up to prepare to start driving the panel 210 . The transmission method of the source drivers 212 ( 6 )˜ 212 ( 10 ) on the right half is the same as the above method, and will not be repeated here.

FIG. 6B is a schematic diagram of an explosive data transmission method that can save power. The explosive data transmission method means that the image data is firstly sent to the nearer source driver 212 , and then gradually sent to the farther source driver 212 . As shown in FIG. 2 , the following description will take the source drivers 212 ( 1 )˜ 212 ( 5 ) on the left half of the LCD as an example. Initially, all source drivers 212 enter power saving mode. In step 622 , the timing controller 225 wakes up the source driver 212 ( 3 ) closest to the flexible circuit board 230 and transmits the image data D. Referring to FIG. Then, in step 622, the source driver 212 (3) wakes up the source drivers 212 (2) and 212 (4), and then the timing controller 225 transmits the image data D to the source drivers 212 (2) and 212 (4 ). Then, in step 624, the source drivers 212(2) and 212(4) wake up the source drivers 212(1) and 212(5) respectively, and then the timing controller 225 transmits the image data D to the source driver 212 (1) and 212(5). The transmission method of the source drivers 212 ( 6 )˜ 212 ( 10 ) on the right half is the same as the above method, and will not be repeated here.

In the above power saving mode, at least the power of the driving unit 434 and the data transceivers 424 and 426 can be turned off. Since the data transceivers 424 and 426 are used to transmit image data, the swing amplitude is large and the frequency is high, and the power consumption is very large. Therefore, unnecessary data transmission can be reduced by the above-mentioned convergent transmission method or explosive transmission method, so as to Effectively improve the efficiency of power supply. In addition, the control transceivers 414 and 416 and the waveform generator cannot be powered off to ensure that the source driver 212 can still transmit and receive control signal streams and act accordingly.

The above-mentioned convergent and explosive data transmission methods can also be used in combination. For example, the source drivers 212(1), 212(2) and 212(3) use the convergent method, and the source drivers 212(4) and 212(5) Explosive, or vice versa. Generally, those skilled in the art can make changes according to the spirit of the present invention, and will not be described in detail here.

In summary, although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art may make various modifications without departing from the spirit and scope of the present invention. and modifications, so the scope of protection of the present invention should be defined by the appended claims.

Claims (8)

1. the electricity saving method of a LCD, in order to reduce the power consumption of multiple source driver, described multiple source driver series connection is arranged on the glass substrate of this LCD, this LCD has at least one flexible PCB, this flexible PCB is connected to corresponding source electrode driver with the view data that transmits time schedule controller and control signal and by the two-way adjacent source driver that is sent to of corresponding source electrode driver, and this electricity saving method comprises:

A. wake the part source electrode driver in the described multiple source driver up;

B. the view data and the control signal of this time schedule controller is sent to the described corresponding source electrode driver of this flexible PCB via the corresponding source electrode driver of this flexible PCB the most long-range driver of wake source in both sides;

C. the most long-range driver of wake source in both sides with the described corresponding source electrode driver of this flexible PCB switches to battery saving mode; And

D. repeating step b and c switch to battery saving mode up to whole source electrode drivers.

2. method according to claim 1, wherein, step a system carries out according to load signal.

3. method according to claim 1, wherein, battery saving mode system closes the data collector and the driver element of described source electrode driver.

4. the electricity saving method of a LCD, in order to reduce the power consumption of multiple source driver, described multiple source driver series connection is arranged on the glass substrate of this LCD, this LCD has at least one flexible PCB, this flexible PCB is connected to corresponding source electrode driver with the view data that transmits time schedule controller and control signal and by the two-way adjacent source driver that is sent to of corresponding source electrode driver, and this electricity saving method comprises:

A. described multiple source driver is all switched to battery saving mode;

B. the corresponding source electrode driver that the view data and the control signal of this time schedule controller is sent to this flexible PCB and wake this correspondence source electrode driver up;

C. the source electrode driver that is in battery saving mode of the most proximal end that the view data and the control signal of this time schedule controller is sent to this correspondence source electrode driver and wake the source electrode driver that is in battery saving mode of described most proximal end up; And

D. repeating step c all wakes up up to described multiple source driver.

5. method according to claim 4, wherein, battery saving mode system closes the data collector and the driver element of described source electrode driver.

6. the electricity saving method of a LCD, in order to reduce the power consumption of multiple source driver, described multiple source driver series connection is arranged on the glass substrate of this LCD, this LCD has at least one flexible PCB, this flexible PCB is connected to corresponding source electrode driver with the view data that transmits time schedule controller and control signal and by the two-way adjacent source driver of its first side and the adjacent source driver of second side thereof of being sent to of corresponding source electrode driver, and this electricity saving method comprises:

A. wake the source electrode driver of described first side up, and the source electrode driver of described second side is switched to battery saving mode;

B. the view data of this time schedule controller and control signal are sent to the most long-range driver of wake source of first side of the described corresponding source electrode driver of this flexible PCB via the corresponding source electrode driver of this flexible PCB, and the source electrode driver that is in battery saving mode of the most proximal end of second side that the view data and the control signal of this time schedule controller is sent to this correspondence source electrode driver;

C. the most long-range driver of wake source with first side of the described corresponding source electrode driver of this flexible PCB switches to battery saving mode, and wakes the source electrode driver that is in battery saving mode of most proximal end of second side of this correspondence source electrode driver up; And

D. repeating step b and c have received view data and control signal all up to described multiple source driver.

7. method according to claim 6, wherein, step a system carries out according to load signal.

8. method according to claim 6, wherein, battery saving mode system closes the data collector and the driver element of described source electrode driver.

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