CN100389595C - Television image algorithm checking system and method - Google Patents
Television image algorithm checking system and method Download PDFInfo
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- CN100389595C CN100389595C CNB2006100118403A CN200610011840A CN100389595C CN 100389595 C CN100389595 C CN 100389595C CN B2006100118403 A CNB2006100118403 A CN B2006100118403A CN 200610011840 A CN200610011840 A CN 200610011840A CN 100389595 C CN100389595 C CN 100389595C
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- 238000004088 simulation Methods 0.000 claims abstract description 13
- 238000012545 processing Methods 0.000 claims abstract description 11
- 238000012795 verification Methods 0.000 claims description 6
- 230000000694 effects Effects 0.000 abstract description 9
- 238000006243 chemical reaction Methods 0.000 abstract description 7
- 238000011156 evaluation Methods 0.000 abstract description 2
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Abstract
The present invention discloses a system and a method for checking a television image algorithm. The system comprises an algorithm simulation device, a storage device, an encoding control device and a digital-to-analog conversion device, wherein the algorithm simulation device is used for realizing image processing algorithm by software, and processes video data to generate data flow suitable for television display format; the storage device is used for storing the data flow outputted by the algorithm simulation device; the encoding control device is used for automatically reading data in the storage device, and encodes the data into digital signals which accord with a television standard; the digital-to-analog conversion device is used for converting digital signals encoded by the encoding control device into analog signals for outputting. The system and the method of the present invention ensure that the actual effect of algorithmic processing can be seen quickly and visually in an algorithm evaluation stage, which greatly enhances the controllability of a project.
Description
Technical field
The present invention relates to a kind of verification system and method, relate in particular to a kind of verification system and method television image algorithm.
Background technology
Because the design of present video chip becomes increasingly complex, need just assess when the project planning the image processing algorithm that relates to.
But when software algorithm platform dateout was interlaced mode, the PC monitor is display image correctly, and real display effect can only can see just on TV that this checking to algorithm has caused inconvenience.
At this moment, if neither one proof of algorithm platform, so to being suitable for the pattern that TV shows, for example the checking of interlaced mode can only could be observed the display effect of image on TV after hardware is realized this algorithm, the problem of bringing be often later stage of project could be on display device the correctness of assessment algorithm, if find that algorithm has problem this moment, will prolong the project cycle, even can change the whole system framework, strengthened the uncontrollability of project.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of television image algorithm checking system and method, just can see the actual effect of algorithm process early stage quickly and intuitively in the project exploitation.
For solving the problems of the technologies described above, the invention provides a kind of television image algorithm checking system, comprising:
The algorithm simulation device is used for realizing image processing algorithm by software, and video data is handled, and generates the data flow that is suitable for the TV display format;
Storage device is used for the data flow of described algorithm simulation device output is stored;
Control code device, be used for reading automatically the data of described storage device, and it is encoded to the digital signal that meets television standard;
Digiverter is used for the digital signal behind the described control code device coding is converted to analog signal output.
Wherein, described system may further include:
Download apparatus is used for that the data flow that described algorithm simulation device generates is downloaded to described storage device and stores.
Wherein, described system may further include:
TV pick-up attacnment is used for the signal of described digiverter output is carried out the TV demonstration.
Wherein, described algorithm simulation device can be by a computer realization.
Wherein, the data flow of described algorithm simulation device generation writes described storage device with the binary file form.
Wherein, described control code device can be realized by fpga chip.
The present invention and then a kind of verification method of television image algorithm is provided comprises the steps:
(1) realizes image processing algorithm by software, video data is handled, generate the data flow that is suitable for the TV display format;
The described data flow that is suitable for the TV display format that (2) will generate is stored;
(3) read the described data flow of storage automatically, and it is encoded to the digital signal that meets television standard;
(4) digital signal that will control after code device is encoded is converted to analog signal output.
Wherein, described step (2) comprising: described data flow is downloaded to a storage device stores.
Wherein, described method may further include:
(5) exporting the analog signal after the described conversion to TV shows.
Wherein, described step (1) can be passed through a computer realization.
Wherein, in the described step (1), described data flow generates with the binary file form.
Wherein, described step (3) can realize by fpga chip.
Adopt the present invention, just can see the actual effect of algorithm process evaluation stage quickly and intuitively at algorithm, improved the controllability of project greatly, system and method highly versatile of the present invention in addition can be used on other Products Development.
Description of drawings
Fig. 1 is according to the described television image algorithm checking system block diagram based on FPGA of the embodiment of the invention.
Embodiment
The embodiment of the invention is that a cover illustrates as an example with the television image algorithm checking platform based on FPGA, can realize various television image Processing Algorithm easily by it, and show the verification algorithm effect by TV.
The verification method flow process that present embodiment provides can comprise the steps:
Step 1: realize image processing algorithm by software, video data is handled, generate the data flow that is suitable for the TV display format;
Step 2: the described data flow that is suitable for the TV display format that will generate is stored;
Step 3: read the described data flow of storage automatically, and it is encoded to the digital signal that meets television standard;
Step 4: the digital signal that will control after code device is encoded is converted to analog signal output;
Step 5: the described analog signal after will changing exports TV to and shows.
Wherein, described step 2 can be described data flow to be downloaded to a storage device store.
Specifically, as shown in Figure 1, the realization of this algorithm platform can be divided into three parts: algorithm is realized part 10, image data storage part 20, and TV signal generates 30.
First: algorithm is realized part 10.Realize various image processing algorithms with software on PC, DID is carried out various processing, the processed images data are kept in the fixed disk file with continuous auspicious form.The total auspicious number of the view data of being preserved can oneself be selected, but the data total amount should not surpass the maximum memory space of storage device.
Second portion: digital picture storage 20.To be kept at view data write storage device in the PC fixed disk file by download apparatus.The capacity of storage device can be selected as required.
Third part: TV signal generates 30.Storage device in the second portion and number-digital-to-analog conversion apparatus and a FPGA platform are integrated into a system.Utilize hardware description language Verilog or VHDL design one cover control circuit, and this circuit is realized at fpga chip by programming.The function of control circuit is the view data in the automatic read storage device and encodes the data to the digital signal that meets television standard.Number-digital-to-analog conversion apparatus is responsible for converting digital television signal to anolog TV signals, can be on television set viewing effect.
If the image effect of seeing on the TV can not meet the demands, the user can revise algorithm and repeat above flow process new algorithm is verified.
In conjunction with practical application, list a kind of concrete platform implementation at this:
Algorithm is realized part:
The video of AVI form of selecting one period 10 second is as the algorithm process object.On PC, this video is handled, generated the data flow that adopts interleaved YUYV 4:2:2 form, it is kept in the binary file by the software implementation algorithm.
The digital picture storage:
Prepare a NAND Flash plate that is 1G byte with a capacity that can read and write NAND Flash.By ICP/IP protocol the ARM platform is connected with PC, and NAND Flash plate is inserted on the ARM platform.On PC by with the supporting software of ARM platform, the content in the video data file of keeping in the previous step is write among the NAND Flash.
TV signal generates:
Prepare a FPGA platform and a DAC plate that is used for digital-to-analogue conversion that uses Xilinx XC2V8000.FPGA is used to realize hardware circuit, and the DAC plate is used for the TV signal of digital form that hardware circuit is generated and converts analog signal to.Describe out hardware circuit with verilog HDL, comprise NAND Flash circulation read control circuit and television signal coding circuit two parts.NAND Flash circulation read control circuit can be from NAND Flash reading video data, the television signal coding circuit can become video data encoding the digital signal that meets the PAL television standard.By Synplify (or other synthesis tools) Verilog HDL code is comprehensively become the edf file.Use Xilinx ISE software on the edf file basis, to generate the bit file.The NAND Flash plate and the DAC plate that have write data in the previous step are inserted on the FPGA platform, DAC output and television set are linked by video line.After powering on for the FPGA plate, by JTAG the bit file is downloaded to from PC and to finish hardware in the fpga chip and realize.Hardware is started working in the fpga chip at this moment, and circulation is read video data and converted thereof into digital pal television signa from NAND Flash, converts anolog TV signals loop play on TV to via the DAC plate.
Use the present invention,, can determine whether image algorithm needs to revise by television image is analyzed and assessed.Revise if desired, only need produce the data file in the algorithm realization part again, just can assess amended algorithm from the process that repeats the back then.This flow process can repeated multiple times, up to after algorithm can arrive the effect of wanting.
According to embodiments of the invention, the video data that algorithm process is crossed generates by software rather than hardware, and the logic scale of hardware of the realization of need programming in fpga chip is little, the resource that takies is few, simultaneously, the required peripheral hardware of FPGA is simple, as long as storage device and number-Mo conversion equipment just can obtain anolog TV signals.
Claims (12)
1. a television image algorithm checking system is characterized in that, comprising:
The algorithm simulation device is used for realizing image processing algorithm by software, and video data is handled, and generates the data flow that is suitable for the TV display format;
Storage device is used for the data flow of described algorithm simulation device output is stored;
Control code device, be used for reading automatically the data of described storage device, and it is encoded to the digital signal that meets television standard;
Digiverter is used for the digital signal behind the described control code device coding is converted to analog signal output.
2. the system as claimed in claim 1 is characterized in that, described system further comprises:
Download apparatus is used for that the data flow that described algorithm simulation device generates is downloaded to described storage device and stores.
3. the system as claimed in claim 1 is characterized in that, described system further comprises:
TV pick-up attacnment is used for the signal of described digiverter output is carried out the TV demonstration.
4. the system as claimed in claim 1 is characterized in that, described algorithm simulation device is by a computer realization.
5. the system as claimed in claim 1 is characterized in that, the data flow that described algorithm simulation device generates writes described storage device with the binary file form.
6. the system as claimed in claim 1 is characterized in that, described control code device is realized by fpga chip.
7. the verification method of a television image algorithm is characterized in that, comprises the steps:
(1) realizes image processing algorithm by software, video data is handled, generate the data flow that is suitable for the TV display format;
The described data flow that is suitable for the TV display format that (2) will generate is stored;
(3) read the described data flow of storage automatically, and it is encoded to the digital signal that meets television standard;
(4) digital signal that will control after code device is encoded is converted to analog signal output.
8. method as claimed in claim 7 is characterized in that, described step (2) comprising: described data flow is downloaded to a storage device stores.
9. method as claimed in claim 7 is characterized in that, described method further comprises:
(5) the described analog signal after will changing exports TV to and shows.
10. method as claimed in claim 7 is characterized in that, described step (1) is by a computer realization.
11. method as claimed in claim 7 is characterized in that, in the described step (1), described data flow generates with the binary file form.
12. method as claimed in claim 7 is characterized in that, described step (3) realizes by fpga chip.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100118403A CN100389595C (en) | 2006-04-30 | 2006-04-30 | Television image algorithm checking system and method |
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| CNB2006100118403A CN100389595C (en) | 2006-04-30 | 2006-04-30 | Television image algorithm checking system and method |
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| CN1845579A CN1845579A (en) | 2006-10-11 |
| CN100389595C true CN100389595C (en) | 2008-05-21 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106713979A (en) * | 2016-12-29 | 2017-05-24 | 深圳Tcl数字技术有限公司 | Conversion method and device for transmission data of smart television |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8442299B2 (en) * | 2009-11-10 | 2013-05-14 | International Business Machines Corporation | Evaluation of image processing algorithms |
| CN102215422B (en) * | 2010-04-01 | 2013-10-23 | 炬力集成电路设计有限公司 | Method, device and system for generating verification code stream of video processing integrated circuit |
| CN107734323B (en) * | 2017-09-13 | 2019-08-16 | 深圳市华星光电技术有限公司 | A kind of algorithm checking system and method |
| CN111641823B (en) * | 2020-05-06 | 2021-08-27 | 深圳市爱协生科技有限公司 | MIPI interface-based image algorithm verification system |
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| JP3552129B2 (en) * | 1995-06-29 | 2004-08-11 | ソニー株式会社 | Image distortion adjustment inspection apparatus and image distortion adjustment inspection method |
| JP2004228742A (en) * | 2003-01-21 | 2004-08-12 | Olympus Corp | Image quality evaluating apparatus |
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- 2006-04-30 CN CNB2006100118403A patent/CN100389595C/en not_active Expired - Fee Related
Patent Citations (6)
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| JPH08182013A (en) * | 1994-12-27 | 1996-07-12 | Hitachi Ltd | Digital convergence automatic adjustment device |
| JP3552129B2 (en) * | 1995-06-29 | 2004-08-11 | ソニー株式会社 | Image distortion adjustment inspection apparatus and image distortion adjustment inspection method |
| CN1386193A (en) * | 2000-06-27 | 2002-12-18 | 松下电工株式会社 | A programming apparatus of a visual inspection program |
| CN1466678A (en) * | 2001-08-31 | 2004-01-07 | ���µ繤��ʽ���� | Image processing inspection system |
| JP2004228742A (en) * | 2003-01-21 | 2004-08-12 | Olympus Corp | Image quality evaluating apparatus |
| CN1750089A (en) * | 2005-10-14 | 2006-03-22 | 彩虹集团电子股份有限公司 | Method for treating color plasma display screen grey |
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| CN106713979A (en) * | 2016-12-29 | 2017-05-24 | 深圳Tcl数字技术有限公司 | Conversion method and device for transmission data of smart television |
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