CN100395745C - Computer system and control system for peripheral device - Google Patents

Abstract

A control system for a peripheral device includes a processor, a first bus, and a bridge device. The processor includes a set of control instructions. The first bus is connected to the processor device using a first bus protocol. The bridge device communicates with the first bus using the first bus protocol and communicates with the peripheral device using a second bus protocol. The processor transmits the set of control instructions to the peripheral device through the first bus and the bridge device, so that the processor directly controls the peripheral device to perform a predetermined function.

Description

Computer system and control system of peripheral devices

technical field

The invention relates to a computer system and a peripheral device control system for controlling a peripheral device.

Background technique

With the continuous expansion of computer system functions, various ways to modularize and expand computer peripheral devices are also becoming more and more diversified. In the known technology, most computer systems have a central processing unit (Central Processing Unit, CPU) to coordinate and control various components and peripheral devices in the computer system. The central processing unit is mostly connected to the bus, and transmits data to the bus or communicates with the bus at a predetermined frequency, commonly known as the FSB of the central processing unit. The data processing speed of each peripheral device is often different from the data processing speed of the central processing unit and the bus, and there is a considerable gap between them. Therefore, the slower peripheral devices are generally processed by chipsets, such as the north-south bridge chipset. , connected to the bus. The central processing unit generally does not directly control the details or individual functions of the peripheral devices. In this case, in order to make the peripheral devices work normally, most of the peripheral devices in the known technology have microcontrollers such as 8032 and Z80. When the central processing unit sends an instruction to the peripheral device, the instruction is received by the microcontroller on the peripheral device, and the microcontroller further controls each functional module of the peripheral device to realize the requirement of the instruction.

Since the peripheral devices in the known technology cannot be directly controlled by the central processing unit, but must include a microcontroller, so as to control the functions of the peripheral devices and make the peripheral devices can operate normally, in this case, each peripheral device is performing a module The installation of the microcontroller still needs to be considered when optimizing the design, which will lead to an increase in manufacturing costs.

Contents of the invention

The present invention provides a peripheral device control system, which can directly control a peripheral device by a processor in cooperation with a bridge device, instead of using a microcontroller inside the peripheral device to control the various functions of the peripheral device and make it available. working normally.

The peripheral device control system of the present invention mainly includes: a processor, a first bus, and a bridge device. The processor includes a set of control instructions, which are used and conform to the first bus protocol when transmitted on the first bus, so as to be transmitted to the bridge device. The bridge device communicates with the processor using the first bus protocol on the first bus, and communicates with the peripheral device using the second bus protocol on the second bus. Wherein, the control commands issued by the processor pass through the first bus to the bridging device, and the bridging device further converts the set of control commands and sends them to the peripheral device through the second bus. If the processor is used, the processor of the present invention can directly control the peripheral device to perform a specific function.

Compared with the known computer system, the peripheral device control system can directly control the peripheral device, so that the processor in the control system can directly control each functional module of the peripheral device, without additionally installing a microcomputer inside the peripheral device. Only the controller can realize the above purpose, so the manufacturing cost of the peripheral device can be reduced.

Description of drawings

FIG. 1 is a functional block diagram of the peripheral device control system of the present invention.

FIG. 2 is a functional block diagram of the bridge device in FIG. 1 .

FIG. 3 is a timing diagram of the peripheral device control system of the present invention.

FIG. 4 is a functional block diagram of the peripheral device and the bridge device in FIG. 1 .

FIG. 5 is a functional block diagram of another embodiment of the peripheral device control system of the present invention.

Description of reference symbols

10, 60: microcontroller device control system 12, 62: processor

14: First bus 16: Bridge device

18: Peripheral device 30: Data acquisition module

32: Bus protocol conversion module 40: Address data sharing pin

42: Data pin 44: First register

46: The second register 48: The first control pin

50: Second control pin 52: First pin

54: Second pin 64: Interface bus unit

66: Internal bus 68: Subprocessor

Detailed ways

Please refer to FIG. 1 . FIG. 1 is a functional block diagram of an embodiment of the peripheral device control system of the present invention. The peripheral device control system 10 includes a processor 12 , a first bus 14 , and a bridge device 16 . In the present embodiment, the first bus 14 can be an Advanced Micro-controller Bus Architecture Bus (Advanced Micro-controller Bus Architecture Bus, abbreviated as AMBA bus), and the AMBA bus is connected between the processor 12 and the bridge device 16, with the first bus protocol (or called AMBA bus protocol) and the bridge device 16 to transmit data or instructions. The bridge device 16 is further connected to the peripheral device 18 via the second bus 20 to transmit data. The content of the data may include a write command or a read command, so that the processor 12 can directly control the peripheral device 18 through the command.

Please refer to FIG. 2 , which is a functional block diagram of the bridging device 16 in FIG. 1 . The bridge device 16 has a data capture module 30 and a bus protocol conversion module 32 . The data retrieval module 30 is connected to the first bus 14 , judges according to the address information in the data transmitted on the first bus 14 , and retrieves relevant and appropriate information. The bus protocol conversion module 32 is used to convert the data captured by the data acquisition module 30 from the first bus protocol to a second bus protocol, so that the data or instructions can pass through the second bus 20 in a manner consistent with the second bus protocol. to the peripheral device 18.

In this embodiment, the processor 12 may be a reduced instruction set computer processor (Reduced Instruction Set Computer Processor, RISC Processor) commonly used in the industry such as ARM and MIPS. The processor 12 includes an addressing range, and the processor 12 controls the operation of the peripheral device 18 by sending address messages falling in the addressing range. When the control system 10 wants to request the peripheral device 18 to perform a specific peripheral operation or function, the processor 12 generates a set of control commands, the set of control commands includes an address message falling in the addressing range, and the set of control commands and The transmission takes place via the first bus 14 . Since the bridge device 16 is also connected to the first bus 14, when the data acquisition module 30 therein reads the address information contained in the control commands on the first bus 14 and correlates with it, it retrieves the contents of the group of control commands. To the bus protocol conversion module 32. Then the bus protocol conversion module 32 temporarily stores the content of the command, and then converts it with the second bus protocol and transmits the converted set of commands to the peripheral device 18, so that the processor 12 can directly control the peripheral device by means of the set of commands 18.

Please refer to FIG. 3 . FIG. 3 is a timing diagram of an embodiment of the peripheral device control system of the present invention. The following uses the timing diagram of FIG. 3 in conjunction with a specific embodiment to describe how the present invention uses the bridge device 16 to convert the message from the first bus 14 into the message of the second bus 20 to control the peripheral device 18 . In this embodiment, when the processor 12 intends to write data to the peripheral device 18 , the processor 12 will generate a set of control instructions for subsequently controlling the peripheral device 18 . The set of control commands includes an address message, a write message, a data message, and a data confirmation message. In general, the processor 12 will at first transmit the control command conforming to the AMBA bus protocol to the bridge device 16 through the first bus (AMBA bus) 14, and the bridge device 16 will perform necessary signal protocol conversion after receiving the control command, so that The control command is further transmitted to the peripheral device 18 .

The detailed description can be shown in FIG. 3 , the processor 12 first sends an address message and a write message to the bridge device 16 via the first bus 14, then sends a data message, and when the data message is sent, sends a data acknowledgment The message is sent to the bridge device 16. The message transmission of this part can be referred to as shown in the upper part of Figure 3 . After the first bus 14 completes the aforementioned message transmission, it returns to the idle state. At this time, the processor 12 can use the first bus 14 to communicate with other devices, so as to maximize the performance of the processor 12 . The data capture module 30 of the bridge device 16 will interpret the message transmitted on the first bus 14 to know whether the current message is related to the device it is in charge of, and if so, it must be further captured and processed. Therefore, when the data acquisition module 30 judges that the current address information on the first bus 14 points to the peripheral device 18, then the whole group of control commands on the first bus 14 are captured to the bus protocol conversion module 32, so that the first bus protocol Convert to the second bus protocol, and send the control command to the peripheral device 18 with the second bus protocol. The message transmission of this part can be referred to as shown in the lower part of Figure 3 . The bridge device 16 transmits the set of control commands to the peripheral device 18 in a time-sharing manner. That is to say, the bridge device 16 first sends an address message conforming to the second bus protocol to the peripheral device 18, and matches an address latch message, and then the bridge device 16 sends a data message to the peripheral device 18, and matches a write enter the message. In this way, the processor 12 can successfully write data to the peripheral device 18 via the first bus 14, the bridge device 16, and the second bus 20, without having to pass through the microcontroller inside the peripheral device as in the known technology. to complete.

The signal waveform on the second bus can also be referred to as shown in FIG. 3 . The control signals on the second bus are mainly composed of address information, data information, write information, read information and address latch information. The signals generated on the second bus usually belong to specific waveforms, such as asynchronous control signals for data transmission or signal generation, and to control the peripheral device 18, the working clock is usually only a few MHz to 30 MHz.

In this embodiment, the peripheral device 18 is a peripheral device of the MsC-51 series, especially a peripheral device of the MSC-518032. In addition, the peripheral device 18 can also be an optical disc drive (Optical Disc Drive), a writable optical disc drive (Recordable Optical Disc Drive), or a USB converter (USBTransceiver), GPIO controller, or any peripheral device independent of the IC, etc. wait. The commonality of such peripheral devices is that they usually only passively accept the control of other commands from the outside, and the sender of these commands can be the computer system connected to the peripheral devices, or the central processing unit CPU in the computer system. Moreover, as long as the peripheral device 18 can be controlled by an external microcontroller, for example: it can be controlled by an external microcontroller of a 51 series (MSC 51 family), the peripheral device 18 can not include a microcontroller, or include Microcontroller However, a microcontroller need not be utilized for the peripheral device control operations associated with the present invention.

That is to say, the peripheral devices of the MSC-518032 exemplified in this embodiment usually do not include a controller, but can be controlled by receiving control commands from the connected computer system. A control command corresponds to a series of continuous specific waveforms. The bridge device 16 proposed by the present invention is used to convert the control command to specific waveforms, replacing the role of the microcontroller in the prior art. If there is no bridging device 16 of the present invention, then the high-speed main control processor 12 in the front-end computer system must go to generate this waveform. In this way, it means that the processor 12 must reserve some system resources to carry out this work. , which affects the efficiency of the overall peripheral device control system 10 . In the MSC-51 series peripheral devices exemplified in this embodiment, if there is a microcontroller, it is usually a slow (<30MHz) microcontroller with few bits (8 or 16 bits), but it must be able to Accept instructions from the high-speed processor 12 controlled by the front end.

In the present invention, the processor 12 can directly transmit instructions to the peripheral device 18 via the first bus 14 and the bridge device 16 to control a specific function of the peripheral device 18. For example, the processor 12 can directly transmit instructions to instruct the optical drive respectively The pickup head moves to a specific position, the spindle motor is commanded to rotate, and the laser head is commanded to read data. Since the present invention can directly control the peripheral device 18, the controlled peripheral device 18 does not need to contain a microcontroller, as long as it can recognize and accept the instructions of the microcontroller, so that the manufacturing cost of the peripheral device can be reduced .

Please refer to FIG. 4 , which is a functional block diagram of the peripheral device 18 and the bridge device 16 in FIG. 1 . The peripheral device 18 is connected to the bridge device 16 in a pin-sharing manner. The bridge device 16 has an address data sharing pin 40 . The address data sharing pin 40 is simultaneously connected to the data pin 42 of the peripheral device 18 , a first register 44 and a second register 46 . In addition, the bridge device 16 has a first control pin 48 and a second control pin 50 connected to the first register 44 and the second register 46 respectively. The peripheral device 18 also has a first pin 52 and a second pin 54 connected to the first register 44 and the second register 46 respectively. The first pin 52 may be a high address pin of the peripheral device 18 and the second pin 52 may be a low address pin of the peripheral device 18 . The address-data sharing pin 40 of the bridge device 16 respectively transmits the first signal, the second signal, and the data signal to the first register 44 , the second register 46 , and the data pin 42 of the peripheral device 18 . The first register 44 temporarily stores the first signal, and the second register 46 temporarily stores the second signal. Afterwards, the first control pin 48 and the second control pin 50 of the bridge device 16 respectively transmit a control signal to control the first register 44 and the second register 46, so as to transmit the first signal and the second signal to the peripheral device 18 The first pin 52 and the second pin 54. Using the first register 44 , the first control pin 48 of the bridge device 16 can share the address data pin 40 of the bridge device 16 with the data pin 42 and the first pin 52 of the peripheral device 18 in a time-division manner. Similarly, by using the second register 46, the second control pin 50 of the bridge device 16 can time-divisionally make the data pin 42 and the second pin 54 of the peripheral device 18 share the address data sharing pin 40 of the bridge device 16. .

FIG. 5 is a functional block diagram of another embodiment of the peripheral device control system of the present invention. Under the architecture proposed by the present invention, if the processor itself does not use the AMBA bus, the present invention can still be applied. FIG. 5 shows a peripheral device control system 60 according to another embodiment of the present invention. In this system 60 , the processor 62 includes a sub-processor 68 and an internal bus 66 . That is to say, the processor 62 itself does not use the AMBA bus, but when using a dedicated internal bus 66 or a third bus. The signal of the processor 62 internal bus or the third bus is first converted into the signal specification of the first bus (AMBA bus) 14, and then the rest and the signal transmission part of the bridge device 16 and the peripheral device 18 are the same as described above, here No longer. In this way, even if the signal of the processor 62 itself uses its dedicated internal bus 66 , the present invention can still be applied.

In summary, the features and advantages of the peripheral device control system of the present invention can be summarized as follows:

1. The present invention mainly utilizes the processor to cooperate with the bridging device to directly control the peripheral device, and does not need to use the micro-controller inside the peripheral device to control the functions of the peripheral device and make it work normally as in the known technology. In the present invention, the peripheral device is mainly controlled by the bridge device through the second bus. In this case, it doesn't matter whether the peripheral control device contains or does not contain a microcontroller, as long as it can be controlled through the second bus. Control, and even the microcontroller inside the peripheral device can be omitted, so the present invention can save the manufacturing cost of the microcontroller without affecting the normal operation of the original system.

2. The bridge device proposed by the present invention can convert the control commands issued by the processor into specific waveforms to subsequently control various operations of the peripheral devices, and thus can replace the role of the microcontroller in the prior art. However, the internal circuit in the general microcontroller is much more complex than the bridge device proposed by the present invention. The microcontroller can be omitted and the bridge device can be used to achieve the purpose of controlling peripheral devices in the present invention. This is where the present invention can save manufacturing costs.

3. In addition to cost considerations, if there is no bridge device of the present invention, the processor in the peripheral device control system must generate waveforms for subsequent control of the peripheral devices. In this way, it means that the processor must reserve some system resources to perform this work, which will affect the efficiency of the overall peripheral device control system. With the bridging device of the present invention, the workload of the processor for controlling the peripheral devices can be largely shared, so that the processor can concentrate limited resources in the system to process the most core calculation work. In this way, the efficiency of the overall peripheral device control system can be improved.

4. Under the architecture proposed by the present invention, if the processor itself does not use the AMBA bus, the present invention can still be applied. In this case, the internal bus signal of the processor can be first converted into the signal specification of the AMBA bus by the known bus conversion technology in the industry, and then the present invention described in the preferred embodiment can be adopted. technology.

Through the above detailed description of the preferred embodiments, it is hoped that the characteristics and spirit of the present invention can be described more clearly, and the scope of the present invention is not limited by the preferred embodiments disclosed above. On the contrary, the intention is to cover various modifications and equivalent arrangements within the scope of the appended claims of the present invention.

Claims (14)

1. A control system for a peripheral device, the control system comprising: a processor capable of generating a set of control instructions; a first bus using a first bus protocol to transmit the set of control instructions generated by the processor; and a bridge device communicating with the first bus using the first bus protocol and communicating with the peripheral device using a second bus protocol; Wherein, the processor transmits the set of control instructions to the peripheral device through the first bus and the bridge device, so that the processor directly controls the peripheral device to perform a predetermined function. 2. The control system of claim 1, the bridging device comprising: a data acquisition module selectively receives the set of control commands from the first bus with the first bus protocol; and A bus protocol conversion module is connected to the data acquisition module, and transmits the received group of control commands to the peripheral device with the second bus protocol. 3. The control system according to claim 1, wherein the set of control commands comprises: an address message, an address latch message, a write message, a data message, and a data confirmation message. 4. The control system of claim 1, the peripheral device does not include a microcontroller. 5. The control system of claim 1, the peripheral device comprises a microcontroller. 6. The control system as claimed in claim 5, the microcontroller of the peripheral device is a 51 series microcontroller. 7. The control system of claim 1, the processor is a RISC processor. 8. The control system as claimed in claim 1, the first bus is an Advanced Microcontroller Bus Architecture bus. 9. The control system of claim 1, the processor comprising: a sub-processor; and a third bus connected to the sub-processor, the third bus using a third bus protocol; Wherein, the third bus of the processor connects the third bus to the first bus through an interface bus unit. 10. The control system as claimed in claim 9, the group of control instructions is transmitted to the interface bus unit by the sub-processor via the third bus and using the third bus protocol, and the interface bus unit receives the received The group control command is transmitted to the bridge device via the first bus using the first bus protocol. 11. The control system as claimed in claim 10, wherein the first bus is an Advanced Microcontroller Bus Architecture bus, the third bus is an internal bus, and the sub-processor is a RISC processor. 12. A computer system comprising: a peripheral device; a processor capable of generating a set of control instructions; a first bus using a first bus protocol to transmit the set of control instructions generated by the processor; and a bridge device communicating with the first bus using the first bus protocol and communicating with the peripheral device using a second bus protocol; Wherein, the processor transmits the set of control instructions to the peripheral device through the first bus and the bridge device, so that the processor directly controls the peripheral device to perform a predetermined function. 13. The computer system according to claim 12 , an address data sharing pin of the bridge device is connected to a data pin of the peripheral device, the address data sharing pin is connected to a first register, and the first register Further connected to a first pin of the peripheral device, a first control pin of the bridge device is connected to the first register, so that the data pin and the first pin share the bridge device's The address data share pin. 14. The computer system according to claim 13, the address data sharing pin of the bridge device is also connected to a second register, and the second register is further connected to a second pin of the peripheral device, the bridge device A second control pin is connected to the second register, so that the data pin and the second pin share the address data sharing pin of the bridge device in a time-division manner.

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