CN100416794C - A semiconductor back-end wiring method using fluorine-containing silicon glass as a dielectric - Google Patents

Abstract

The invention discloses a semiconductor back-end wiring method using fluorine-containing silicon glass as a dielectric. The present invention is a semiconductor back-end wiring method using fluorine-containing silicon glass as a dielectric. The first step is to form a metal line; the second step is to grow an oxide with a refractive index greater than 1.48 as a pad oxide layer; the third step , deposit FSG as a dielectric, and cover a layer of normal refractive index silicon oxide or tetraethoxysilane on the surface; the fourth step is to planarize the composite film composed of FSG, silicon oxide or tetraethoxysilane The fifth step is to grow a layer of oxide with a refractive index greater than 1.48 on the surface of the planarized silicon wafer as a covering layer; the sixth step is to open holes to form tungsten plugs; the seventh step is to remove excess tungsten and diffusion barrier layer; The eighth step is to deposit the next layer of metal. The invention is suitable for semiconductor wiring technology.

Description

A semiconductor back-end wiring method using fluorine-containing silicon glass as a dielectric

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor back-end wiring method using fluorine-containing silicon glass as a dielectric.

Background technique

With the further development of semiconductor technology, nanotechnology is becoming more and more important, which also puts forward new requirements for the integration of subsequent processes. In the case of nanometer technology, it is necessary to further reduce the circuit delay caused by the parasitic capacitance of the subsequent metal interconnection and dielectric. Therefore, in the prior art, a new low-resistance material copper and a low-permittivity dielectric material such as FSG, that is, fluorine-containing silicon glass, are used in the semiconductor back-end wiring process.

The flow diagrams of the semiconductor back-end wiring method using fluorine-containing silicon glass as the dielectric in the prior art are shown in FIGS. 1 and 3 . The first step is to form metal lines, see Figure 3a; the second step is to use normal refractive index silicon oxide or tetraethoxysilane grown in-situ in high-density plasma chemical vapor deposition equipment as the pad oxide layer, where the pad The refractive index of the lining oxide layer is about 1.46, see Figure 3b; the third step is to deposit FSG as a dielectric in the same equipment without breaking the vacuum, see Figure 3c; the fourth step is to grow Finally, the surface is covered with a layer of silicon oxide or tetraethoxysilane with normal refractive index, and it is planarized by chemical mechanical polishing, or it can be directly polished by chemical mechanical polishing without covering silicon oxide or tetraethoxysilane. The planarization, see Figure 3d. The fifth step is to form contact holes and tungsten plugs by means of photolithography, etching, physical and chemical vapor deposition, and remove excess tungsten and diffusion barrier layer by tungsten chemical mechanical polishing, see Figure 3e; the sixth step, Deposit the next layer of metal according to conventional procedures, generally titanium, titanium nitride, aluminum alloy, titanium and titanium nitride structure, and the direct contact with the dielectric layer is generally titanium, see Figure 3f.

However, the prior art process method has the following problems: firstly, as shown by the mark A in Fig. 3b, due to its poor conformality, the thickness of the liner oxide layer grown in situ is less than the nominal value at the corner of the line, which will cause The metal line integrity is severely compromised during the subsequent FSG deposition, as indicated by marker B in Figure 3c.

Secondly, in order to maintain the integrity of the metal lines, the pad oxide layer grown in-situ must exceed a certain thickness, but this will cause a decrease in filling performance and leave small voids between the metal lines, which will cause problems in the subsequent manufacturing process. Causes potential metal growth in between, causing leakage between metal lines, which greatly reduces the yield; in addition, due to its high dielectric constant relative to FSG, the parasitic capacitance between metal lines increases, reducing the speed of the final circuit.

Third, due to its low refractive index, the pad oxide layer grown in situ cannot well prevent the F element in the FSG from diffusing to reach the interface between the dielectric and the metal, resulting in electromigration failure and reliability problems.

Finally, during the sintering process of the alloy at about 400 degrees, there is no or only a layer of silicon oxide with a normal refractive index covering the FSG, which causes the F element in the FSG to diffuse upward from the FSG body to the interface with Ti, forming the fluorine of Ti Compounds reduce the bonding force and cause peeling between the dielectric material and the metal aluminum alloy lines, resulting in low yield and electromigration failure.

The methods in the prior art have problems such as incomplete metal lines, large parasitic capacitance, and peeling between the FSG and the film during the final high-temperature annealing, resulting in low product qualification rate and short electromigration life.

Contents of the invention

The technical problem to be solved by the present invention is to provide a semiconductor back-end wiring method using fluorine-containing silicon glass as a dielectric.

In order to solve the above technical problems, the present invention uses fluorine-containing silicon glass as a semiconductor back-end wiring method as a dielectric. The first step is to form metal lines; the second step is to use plasma enhanced chemical vapor deposition to grow the refractive index An oxide greater than 1.48 is used as a pad oxide layer; the third step is to deposit FSG as a dielectric by high-density plasma chemical vapor deposition, and cover the surface with a layer of normal refractive index silicon oxide or tetraethoxysilane ; The fourth step is to planarize the composite film composed of FSG, silicon oxide or tetraethoxysilane by chemical mechanical polishing; Grow a layer of oxide with a refractive index greater than 1.48 as a covering layer; the sixth step is to open holes to form tungsten plugs; the seventh step is to use tungsten chemical mechanical polishing to remove excess tungsten and the diffusion barrier layer; the eighth step is to deposit The next layer of metal.

As a preferred technical solution, the present invention provides a semiconductor back-end wiring method using fluorine-containing silicon glass as a dielectric, wherein the pad oxide layer grown in the second step is silicon oxide, silicon oxynitride, silicon nitride or a combination thereof, the film thickness of the pad oxide layer is greater than 12nm and less than 80nm.

As another preferred technical solution, the present invention uses fluorine-containing silicon glass as a semiconductor back-end connection method as a dielectric, and the oxide capping layer grown in the fifth step is silicon oxide, silicon oxynitride, silicon nitride Or a combination thereof, the thickness of the oxide capping layer is greater than 100nm and less than 4000nm.

Compared with the prior art, the present invention uses fluorine-containing silicon glass as a semiconductor back-end wiring method as a dielectric. Before FSG deposition, plasma-enhanced chemical vapor deposition (plasma-enhanced chemical vapor deposition, hereinafter referred to as PECVD) to grow a certain thickness of oxide with a refractive index greater than 1.48 as a pad oxide layer, and then use high-density plasma chemical vapor deposition to deposit FSG as a dielectric. After the growth of the dielectric, chemical It is flattened by mechanical polishing, and finally covered with a layer of oxide with a refractive index higher than 1.48 as a cover layer. Compared with the existing method, the method of the invention can make the integrity of the metal line good, the product qualification rate is high, and the electromigration life can be increased by an order of magnitude.

Description of drawings

The present invention will be further described below in conjunction with accompanying drawing and embodiment:

FIG. 1 is a flow chart of an existing semiconductor back-end connection process;

Fig. 2 is the flow chart of the semiconductor back-end wiring method using FSG as a dielectric in the present invention;

FIG. 3 is a schematic diagram of a cross-sectional flow chart of a semiconductor back-end wiring process in the prior art;

FIG. 4 is a schematic cross-sectional flow chart of a semiconductor back-end wiring method using FSG as a dielectric material according to the present invention.

Detailed ways

As shown in Figure 2 and Figure 4, firstly, metal lines are formed, see Figure 4a; secondly, oxides with a refractive index greater than 1.48 grown by plasma-enhanced chemical vapor deposition in PECVD equipment are used as pad oxide layers, see Figure 4b; wherein, the pad oxide layer is silicon oxide, silicon oxynitride, silicon nitride or a combination thereof, and the film thickness of the pad oxide layer is greater than 12 nm and less than 80 nm. The third step is to use high-density plasma chemical vapor deposition to grow FSG and deposit FSG as a dielectric, see Figure 4c; the fourth step is to cover the surface with a layer of normal refractive index silicon oxide after the growth of FSG dielectric Or tetraethoxysilane, and then planarize it with chemical mechanical polishing, see Figure 4d. In this step, it is also possible not to cover silicon oxide or tetraethoxysilane, and directly use chemical mechanical polishing to planarize it; the fifth step is to cover the surface with a layer of oxide with a refractive index greater than 1.48 as a covering layer, see Figure 4e. The grown oxide covering layer is silicon oxide, silicon oxynitride, silicon nitride or a combination thereof, and the thickness of the oxide covering layer is greater than 100nm and less than 4000nm; the sixth step is to use photolithography, etching, physical and chemical vapor deposition The method forms a contact hole and a tungsten plug, and removes excess tungsten and a diffusion barrier layer by chemical mechanical polishing of tungsten, see FIG. 4f; finally, deposits the next layer of metal, see FIG. 4g.

By using the method of the invention, the integrity of the metal lines can be improved, the qualified rate of products can be improved, and the life of electromigration can be increased.

Claims (3)

1. one kind with the semiconductor back-end bus connection method of fluorine silicon glass as dielectric medium, it is characterized in that the first step forms metal wire; Second step, using plasma strengthen chemical gaseous phase depositing process growth refractive index greater than 1.48 oxide as the pad oxide layer; The 3rd step, adopt high density plasma CVD method deposit FSG as dielectric medium, and at the silica or the tetraethoxysilane of surface coverage one deck normal refraction rate; In the 4th step, the composite membrane that the method for employing chemico-mechanical polishing is formed FSG, silica or tetraethoxysilane carries out planarization; The 5th step, using plasma strengthen the silicon chip surface growth one deck refractive index of chemical gaseous phase depositing process after planarization greater than 1.48 oxide as cover layer; In the 6th step, perforate forms the tungsten plug; In the 7th step, adopt the cmp method of tungsten to remove unnecessary tungsten and diffusion impervious layer; The 8th step, layer of metal under the deposit.

2. described a kind of with the semiconductor back-end bus connection method of fluorine silicon glass as dielectric medium as right 1, it is characterized in that, wherein the pad oxide layer of growth is silica, silicon oxynitride, silicon nitride or its combination in second step, and pad oxide layer film thickness is greater than 12nm, less than 80nm.

3. described a kind of with the semiconductor back-end bus connection method of fluorine silicon glass as dielectric medium as right 1, it is characterized in that, the grown oxide cover layer is silica, silicon oxynitride, silicon nitride or its combination in the 5th step, and oxide cover layer thickness is greater than 100nm, less than 4000nm.

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