CN100428641C - Mixer of direct conversion type radio frequency receiver - Google Patents

Abstract

A mixer of a direct conversion radio frequency receiver comprises a gain circuit, a load circuit and a conversion circuit. The gain circuit receives a differential type radio frequency signal to generate a first gain signal. The conversion circuit mixes the first gain signal with the local oscillation signal to directly down-convert to generate a modulation signal. The load circuit includes a pair of first transistors, a pair of second transistors, and a pair of impedance units. The impedance unit provides a gain parameter. The first transistor provides low impedance so that the modulation signal can be continuously input into a load circuit. The second transistor provides a high impedance to guide the modulation signal input to the load circuit to the impedance unit and outputs a second gain signal in accordance with the gain parameter. The second transistor is a direct npn type bipolar transistor parasitic by using a metal oxide semiconductor structure.

Description

Mixer for Direct Conversion RF Receiver

technical field

The present invention relates to a direct conversion (Direct Conversion or Homodyne) radio frequency receiver (Radio Frequency receiver, RF receiver), in particular to a mixer (Mixer) in the direct conversion radio frequency receiver.

Background technique

The RF receiver of traditional wireless electronic products is "heterodyne RF receiver" as the mainstream technology. Heterodyne RF receiver, also known as heterodyne receiver. This type of RF receiver has good performance. Other types of RF receivers, such as direct conversion (direct conversion) RF receivers, wideband IF (wideband IF) RF receivers or low IF (low IF) RF receivers It can also refer to the deformation technology or derivative technology of the heterodyne radio frequency receiver.

A heterodyne radio frequency receiver usually performs at least two down-frequency steps on the received radio frequency signal to obtain the required fundamental frequency electrical signal. For example, the high-frequency radio frequency signal is reduced to the intermediate frequency through the first frequency reduction step, and then reduced to the low-frequency electrical signal (close to DC frequency) that can be recognized and operated in electronic products by the second frequency reduction step.

Although the heterodyne radio frequency receiver has good performance, it must use some electronic components that are expensive and cannot be integrated in the integrated circuit chip, and its overall structure is relatively complicated. Therefore, in today's technology that requires single-chip integration Under the trend, the heterodyne radio frequency receiver has the disadvantages that it is not easy to realize and the production cost is too high.

In contrast, the direct-conversion RF receiver is more in line with the trend of single-chip integration. The direct-conversion RF receiver is also called Homodyne RF receiver, and since the direct-conversion RF receiver can be regarded as a heterodyne simplified structure with "the intermediate frequency is set at zero", it is also called It is a zero intermediate frequency (Zero IF) radio frequency receiver. Please refer to FIG. 1 , the direct-conversion radio frequency receiver 10 directly mixes the received radio frequency signal (usually at a high frequency) with a local oscillation signal (LO) in the same frequency range, and reduces the frequency by one step. Generate the desired low frequency electrical signal. Compared with the aforementioned heterodyne structure, the direct conversion structure is more direct and natural. Moreover, in the direct conversion RF receiver, the artifact signal caused by the image frequency (image frequency) does not exist, which is another advantage over the heterodyne RF receiver.

The front end circuit of a typical direct-conversion RF receiver 10 includes a low-noise amplifier (LNA) 14, and mixers (mixer) 16a and 16b; the rear-end circuit includes a baseband amplifier (baseband amplifiers) 22a and 22b, low-pass filters (LPF) 23a and 23b, analog-to-digital converters (ADC) 24a and 24b, and digital signal processor (DSP) 26. Among them, the mixer 16a, the baseband amplifier 22a, the low-pass filter 23a, and the analog-to-digital converter 24a belong to the I path, while another group of the same components (16b, 22b, 23b and 24b in the figure) belong to the I path. Q path.

In the known technology, sometimes a radio frequency front-end filter (preselection filter) 12 is further set before the low noise amplifier 14, so as to filter the signal received by the antenna 11, and the interference signal ( out-of band signal) to be filtered out; sometimes, the RF front-end filter 12 can also partially suppress the image frequency in the RF signal. The output end of the RF front-end filter 12 is coupled to a low noise amplifier 14 for signal amplification. Taking the IEEE 802.11b WLAN specification as an example, the received RF signal, the RF front-end filter 12 and the LNA 14 are all in the frequency range of 2.4GHz to 2.48GHz.

The output terminals of the low noise amplifier 14 are respectively coupled to the mixers 16a and 16b. The local oscillator 18 provides a local oscillator signal, and the quadrature phase generated by the frequency divider 15 is input to the mixers 16 a and 16 b on the I and Q paths respectively. Taking the IEEE 802.11b WLAN specification as an example, the local oscillator 18 operates at 2.4 GHz, so that high frequency radio frequency signals can be directly converted into low frequency electrical signals. The baseband amplifiers 19a and 19b are respectively coupled to the mixers 16a and 16b to amplify the electrical signals obtained by the mixers 16a and 16b. Afterwards, the low-pass filters 23a and 23b of the fundamental frequency are used to suppress interference signals outside the desired frequency band. In the direct-conversion radio frequency receiver 10, the low-pass filters 23a and 23b can be regarded as elements responsible for channel selection . Finally, the signal is digitized through the analog-to-digital converters 24a and 24b, and sent to the digital signal processor 26 to perform predetermined application operations related to the radio frequency signal.

The structure of the direct-conversion RF receiver has many advantages. For example, the components of the intermediate frequency circuit required by the heterodyne RF receiver are eliminated, so the overall circuit complexity can be reduced, and the research and development of the system application designer can be relieved. heavy burden. And because of the reduced complexity, the concept of single-chip integration can be implemented in the structure of a direct-conversion RF receiver. High integration, low cost, low power consumption and high bandwidth are its advantages.

However, although the direct-conversion RF receiver 10 can be integrated into a single chip, its performance is not as good as the traditional heterodyne RF receiver. Since the direct-conversion RF receiver 10 directly down-converts the signal to near direct current (DC), the mixers 16a and 16b therein are more sensitive to LO self-mixing and low-frequency performance. Also because of such characteristics, the direct conversion RF receiver 10 has disadvantages such as high noise figure (NF) , insufficient linearity, and DC-offsets.

noise figure

Since most of the amplification function in the direct conversion RF receiver 10 is placed on the circuit after the mixer 16a (and 16b), low-frequency noise becomes the focus of attention. In the baseband, even a weak noise with only a few microvolts (μV) is quite easy to be amplified in the subsequent circuit to cause considerable noise. If a radio frequency circuit with a higher gain is used to improve the noise problem of the baseband circuit, the linearity problem caused by the higher gain needs to be considered.

The main source of the above-mentioned baseband noise is flicker noise, or called inverse frequency noise (1/f noise). The magnitude of flicker noise is inversely proportional to the baseband DC frequency, therefore, the outputs of mixers 16a (and 16b) operating at low frequencies will have particularly high conversion gains. In the direct-conversion radio frequency receiver 10 of the complementary metal oxide semiconductor (CMOS) process, the MOS element will bring particularly high flicker noise. In the known technology, the size of the metal oxide semiconductor (MOS) element has been increased. However, this will increase its capacitance value and consume more energy of the local oscillator 18 or reduce the amplitude of the local oscillator in the high noise frequency band.

Linear performance

The linearity performance of the direct-conversion RF receiver 10 is mainly determined by the mixer 16a (and 16b ) of the front-end circuit. In terms of circuit implementation, the mixer 16a (and 16b ) can be divided into a switching stage and a loading stage. Among the common specifications, most of the mixers 16a (and 16b) have specifications for the multiplication slope of the second-order cut-off point (ie, the IIP2 parameter) and the multiplication slope of the third-order cut-off point (ie, the IIP3 parameter).

The IIP2 parameter and the IIP3 parameter have a great influence on the overall linearity performance. This is because the high-frequency signal is directly down-converted to the required baseband in the conversion circuit; the load circuit is responsible for the first gain after the signal is down-converted. Therefore, the design of these two parts will have a key impact on the overall linearity performance.

DC voltage offset

The DC voltage offset should be regarded as the most serious problem faced by the front-end circuit of the direct-conversion RF receiver 10 . It not only distorts the desired signal, but also may cause saturation of the subsequent stage circuit. Even setting aside common problems such as component mismatch or signal line asymmetry in CMOS processes, self-mixing of local oscillator signals or other large interfering signals in the baseband , will also cause a DC voltage offset.

Contents of the invention

Under the development trend of single-chip integration, the main purpose of the present invention is to improve the shortcomings of the known direct-conversion RF receivers.

Another object of the present invention is to provide a mixer for direct conversion RF receiver with low noise figure.

Another object of the present invention is to provide a mixer for direct conversion RF receiver with high linearity.

The invention provides a mixer of a direct conversion radio frequency receiver, which includes a gain circuit, a load circuit and a conversion circuit. The gain circuit receives the differential radio frequency signal to generate a first gain signal. The conversion circuit mixes the first gain signal with the local oscillation signal to generate a modulated signal by directly reducing the frequency. The load circuit includes a pair of first transistors, a pair of second transistors and a pair of impedance units. Impedance elements provide gain parameters. The first transistor provides low impedance so that the modulation signal continues to be input to the load circuit. The second transistor provides high impedance to guide the modulation signal input to the load circuit to the impedance unit and output a second gain signal conforming to the gain parameter.

The second transistor is a vertical (Vertical npn, Vnpn) type bipolar transistor parasitic when utilizing metal oxide semiconductor (MOS) manufacturing process, whereby the present invention effectively improves the direct conversion radio frequency receiver performance on the subject of noise index. In another embodiment, the first transistor is a lateral (Lateral pnp, Lpnp) type bipolar transistor parasitic by using a metal oxide semiconductor (MOS) structure, thereby improving the linearity of the direct conversion radio frequency receiver. degree of performance.

The advantages and spirit of the present invention can be further understood through the following detailed description of the invention and the accompanying drawings.

Description of drawings

Through the following detailed description combined with the accompanying drawings, the above content and many advantages of this invention can be easily understood, wherein:

Figure 1 shows a typical structure of a direct conversion RF receiver;

Fig. 2 is a front-end circuit diagram of a direct conversion radio frequency receiver according to an embodiment of the present invention;

3 is a side sectional view of the first transistor in FIG. 2 when it is implemented as a straight npn bipolar transistor;

Fig. 4 is another embodiment circuit diagram of the present invention;

FIG. 5A is a side sectional view of a typical pMOS device;

FIG. 5B is a side cross-sectional view of a lateral pnp bipolar transistor parasitic by using the pMOS element of FIG. 5A; and

Fig. 6 is a circuit diagram of another embodiment of the present invention.

[Description of main component labels]

Direct conversion radio frequency receiver 10, 30 Antenna 11

RF Front-End Filter 12 Low Noise Amplifier 14

Mixer 16a, 16b Baseband amplifier 22a, 22b

Low-pass filter 23a, 23b Analog-to-digital converter 24a, 24b

Digital signal processor 26 Receiver 301

Output terminal 303 Bias voltage 31

Gain circuit 32 Local oscillator 33

local oscillation signal 331 conversion circuit 34

Frequency divider 15, 35 Load circuit 36

First transistor 361 Second transistor 362

Part 1 36a Part 2 36b

Capacitor 365 Resistor 367, 368, 369

Current source 37 Feedback unit 38

RF signal 40 First gain signal 42

Modulation signal 44 Second gain signal 46

Collector 119, 298 N-type well 192

Shallow trench isolation structure 195 P-type doped region 197

N-type doped region 198 emitter 198', 298'

Base 191, 291 Gate 295

Gain Circuit Current Source 371

Detailed ways

The present invention provides a mixer of a direct-conversion radio frequency receiver manufactured by a complementary metal oxide semiconductor (CMOS) process. The mixer includes a gain circuit, a conversion circuit and a load circuit.

According to the structural diagram of FIG. 1 , the circuit provided by the present invention and the protection scope of the application belong to the mixer 16 a (or 16 b ) of FIG. 1 . It is particularly worth mentioning that, in the pre-stage circuit of the direct conversion radio frequency receiver 10, the circuit structure of the low noise amplifier 14 is similar to the gain circuit of the present invention, but the two are different.

Please refer to FIG. 2 , which is a circuit diagram of an embodiment of the present invention. As mentioned above, the mixer 30 includes a gain circuit 32 , a conversion circuit 34 and a load circuit 36 . The gain circuit 32 receives a differential type RF signal 40 to generate a first gain signal (first gain) 42 . The radio frequency signal 40 is received by the antenna, and before being sent to the receiving end 301 of the gain circuit 32, the radio frequency front-end filter (pre-selection filter, refer to the number 12 in Figure 1) can be used to convert the antenna (the number 11 in Figure 1) to The received signal is filtered to filter out the interference signal outside the frequency band to be used. Afterwards, the low noise amplifier (please refer to reference numeral 14 in FIG. 1 ) coupled to the front end of the mixer 30 can be used to amplify the signal and input it to the receiving end 301 . Wherein, the first gain signal 42 is a differential type.

Since the received radio frequency signal 40 is a differential type, the circuit design of the present invention should also be designed in a balanced circuit, wherein, no matter the gain circuit 32, the conversion circuit 34 or the load circuit 36 are all in a symmetrical manner set up.

The conversion circuit 34 is used for mixing the first gain signal 42 with the local oscillation signal 331 to generate a modulation signal 44 by direct down-converting. Of course, the modulation signal 44 is also of differential type. The local oscillator signal 331 is provided by a local oscillator (local oscillator) 33 , and its frequency is close to that of the radio frequency signal 40 and the first gain signal 42 . After the local oscillator signal 331 is mixed with the first gain signal 42 , since the frequencies of the two are similar, the frequency of the modulated signal 44 obtained is the difference between the frequencies of the two, which is close to the DC frequency. In practice, the conversion circuit 34 needs to be a well-balanced circuit, so as to avoid the offset of the differential signal.

It is worth mentioning that, since FIG. 2 only shows one mixer 30 in the direct conversion radio frequency receiver of the present invention, the mixer 30 shown can be applied to the I path, and the pre-stage circuit applied to the Q path can also be used. It should be symmetrical with it. For this structure, reference can be made to FIG. 1 and related descriptions. Therefore, the local oscillator 33 can be coupled to a quadrature differential output 35 to form the required phase difference between the I path and the Q path. In practice, the phase difference between the two is ninety degrees.

Please continue to refer to the right half of Figure 2. The load circuit 36 includes a pair of first transistors ( ^1st transistor) 361 , a pair of second transistors ( ^2nd transistor) 362 and a pair of impedance units (in this embodiment, each impedance unit refers to a resistor 368 ). The impedance unit provides a gain parameter for converting an AC current gain to an AC voltage gain.

The load circuit 36 is divided into a first part 36a and a second part 36b in parallel, which is a symmetrical circuit design for differential signals in the present invention.

The pair of first transistors 361 belong to the first part 36a and the second part 36b respectively; and the pair of second transistors 362 also belong to the first part 36a and the second part 36b respectively.

The above-mentioned pair of impedance units also belong to the first part 36a and the second part 36b respectively. For example, in this embodiment, a pair of capacitors 365 belong to the first part 36a and the second part 36b respectively, and a pair of resistors 368 belong to the first part 36a respectively. with the second part 36b.

Please refer to one of the first part 36 a or the second part 36 b separately: the first transistor 361 provides a low impedance relative to the high impedance of the current source 37 , so that the modulating signal 44 can continue to be input into the load circuit 36 .

The second transistor 362 provides high impedance to guide the modulation signal 44 input to the load circuit 36 to the impedance unit (referring to the resistor 368 and the capacitor 365 in this embodiment), and outputs the gain conforming to the impedance unit through the output terminal 303 A second gain signal 46 of parameters. The second gain signal 46 also corresponds to the RF signal at the input terminal 301 and is of a differential type. The second gain signal 46 is output from the output terminal 303 to the post-stage circuit of the direct-conversion RF receiver. For the post-stage circuit, please refer to the relevant description in Figure 1

In practice, the current source 37 provides the total current required by the conversion circuit 34 and the load circuit 36 , and the current input to the first transistor 361 is the difference between the current provided by the current source 37 and the current of the gain circuit current source 371 . The pair of first transistors 361 have a common gate, which can pass through a bias voltage (bias) 31 to the first transistor 361 . In practice, the two second transistors 362 of the first part 36a and the second part 36b provide the required high impedance to facilitate the modulation signal 44 to pass through the impedance units (365 and 368), generate the second gain signal 46 and pass through the output terminal 303 output. Wherein, the resistor 367 also has a high impedance value, so as to prevent the signal from passing through the resistor 367 .

The pair of second transistors 362 may have a common gate. The contact of the common gate can be coupled to the feedback unit (CMFB) 38 to detect the asymmetry of the signal and give feedback, so as to avoid the asymmetry of the output second gain signal 46, such as the leverage phenomenon of signal offset and so on. In another embodiment, the pair of second transistors 362 may have a common source, but instead of using the feedback unit 38, it is implemented by forming a current mirror, as shown in FIG. 4 . The above-mentioned embodiments are all for ensuring the balance relationship between the first part 36 a and the second part 36 b of the load circuit 36 , which can effectively eliminate the shortcoming of the DC voltage offset.

In this embodiment, the second transistor 362 providing high impedance is a vertical npn (Vnpn) type bipolar transistor formed parasitic by metal-oxide-semiconductor (MOS) process, please refer to FIG. 3 .

The present invention considers that under the Complementary Metal-Oxide-Semiconductor (CMOS) process of general direct-conversion radio frequency receivers, there is no bipolar transistor process, and the second transistor 362 shown in FIG. Metal-oxide-semiconductor (n-MOS) implementation, then the inverse frequency noise (1/f noise) of n-type metal-oxide-semiconductor (n-MOS) is relatively large, and will directly affect the second gain signal 46 output, so will have a large negative impact on the overall noise.

Based on the above considerations, the present invention changes the n-type metal oxide semiconductor (n-MOS) structure. After adding a deep N-well (deep N-well) as the collector (collector) 119, as shown in FIG. 3 As shown, the required bipolar transistor structure is formed by the collector 119, the base 191 and the emitter 198'. Wherein, reference numeral 195 is a shallow trench isolation structure (STI). The base 191 is mainly a p-well of an original n-type metal oxide semiconductor (n-MOS) structure. The emitter 198' is the source or drain in the original n-type metal oxide semiconductor (n-MOS) structure. The P-type doped region 197 coupled to both ends of the base 191 , and the N-type well 192 and N-type doped region 198 coupled to both ends of the collector 119 can reduce the impedance of the base 191 and the collector 119 .

With the above implementation, the noise-to-signal ratio of the direct-conversion radio frequency receiver can be effectively reduced. Because under the situation of low frequency (less than 10MHz), the noise source of mixer 30 is mainly frequency inverse ratio noise (1/f noise), and the direct npn (Vnpn) type bipolar transistor (as shown in the figure) provided by the present invention 3) The inverse frequency noise is about 100 times lower than that of n-MOS, so the performance of the mixer 30 of the present invention is greatly improved in terms of noise issues.

Please refer to FIG. 4 , which is a circuit diagram of another embodiment of the present invention. Wherein the first transistor 361 is a lateral pnp (Lpnp) type bipolar transistor formed by parasitic metal oxide semiconductor (MOS) structure. In this embodiment, the first transistor 361 in the load circuit 36 is implemented as a bipolar transistor. In this way, the linearity of the provided direct-conversion RF receiver is effectively improved. It has been recorded in many documents that the first p-type metal oxide semiconductor (p-MOS) element located in the load circuit 36 and superimposed after the conversion circuit 34 has a linearity performance for the load circuit 36 ( ie the IIP3 parameter) has a significant negative impact. Therefore, a bipolar transistor is used for the first transistor 361 to replace the conventional pMOS device. The bipolar transistor has a lower input impedance (Zm) and can generate a higher gain (gm). Therefore, as far as the current level is concerned, the modulating signal 44 can see a lower impedance at the first transistor 361 than in the known technology. In this way, the non-linear output generated by the first transistor 361 can be suppressed. The present invention is at IIP3 The performance on the parameters can thus be significantly improved.

However, as mentioned above, under the complementary metal oxide semiconductor (CMOS) process of the general direct-conversion RF receiver, there is no bipolar transistor process. However, if a vertical pnp (vertical pnp) structure is formed by parasitizing the pMOS device similarly to the above-mentioned embodiment, although it is feasible in concept, it is found that the performance is very low when actually put into production. This is because a straight pnp type bipolar transistor composed of a P-type doped region, an N-type well and a deep P-type well (from top to bottom, not shown in the figure) will not have an isolated terminal (isolated collector terminal), which means that the collector (collector) and the base (substrate) form a short circuit, which results in a too low β value (only 2.5), resulting in poor performance.

For this reason, the present invention is implemented by using a pMOS element to form a lateral pnp (Lpnp) type bipolar transistor by parasitic. Please refer to FIG. 5A and FIG. 5B. FIG. 5A is a typical pMOS device, and FIG. 5B is a lateral pnp (Lpnp) type bipolar transistor parasitic using the pMOS device in FIG. 5A. The collector 298, base 291 and emitter 298' form the desired bipolar transistor configuration as shown in FIG. 5B. Among them, the P-type doped region originally used as the source or drain in the pMOS device becomes the collector 298 or the emitter 298' in this embodiment; the N-type well in the original pMOS device is located in the collector The portion between the electrode 298 and the emitter 298 ′ serves as the base 291 . In operation, a reference potential (V _DD ) needs to be applied to the gate 295 of the original pMOS device, so as to turn off the pMOS and prevent signals from being routed through the gate 295 .

Through the above-mentioned implementation manner, for the pair of second transistors 362 shown in FIG. 4 to be implemented by using bipolar transistors, at least the IIP3 parameter can be maintained at the performance required by the specification, or even exceed the performance required by the specification. . Generally speaking, in the simulation test (simulation), if the second transistor 362 is a pMOS element, the linearity (IIP3 parameter) of the load circuit 36 will be degraded by 3-4dBm; if it is a bipolar transistor, then It can make the IIP3 parameters equal, and even have better linearity results. For example, under the CMOS process with a channel length of 0.3 microns (μm), the standard second transistor 362 needs to have a cut-off frequency (f _T ) higher than 10 MHz, and under the same process conditions, the second transistor 362 formed by the method of the present invention The lateral pnp (Lpnp) type bipolar transistor (as shown in FIG. 5B ) can easily surpass this standard.

Please refer to FIG. 6 , which is a circuit diagram of another embodiment of the present invention. In this embodiment, the advantages of the embodiment in FIG. 2 and the embodiment in FIG. 4 are combined, so that the first transistor 361 utilizes a pMOS element in a known complementary metal-oxide-semiconductor (CMOS) process technology to form a lateral pnp (Lpnp) parasitic ) type bipolar transistor; on the other hand, make the second transistor 362 among them, utilize nMOS element in the known complementary metal-oxide-semiconductor (CMOS) process technology to form parasitic direct npn (Vnpn) type bipolar transistor sex transistor. Through the above-mentioned embodiment, it is possible to provide the mixer 30 of the direct-conversion RF receiver with good linearity and low noise as shown in FIG. 6 . Moreover, in conjunction with the good balanced circuit design of the present invention, the present invention also has an excellent suppression effect on the problem of DC voltage offset. Another advantage of the present invention is that it can apply the existing complementary metal-oxide-semiconductor (CMOS) process, and only use minor changes in the layout of the integrated circuit without adding a photomask or changing the process. , so that the direct-conversion radio frequency receiver not only still conforms to the single-chip integration trend, but also has better performance. Based on the above, the present invention not only has significant technological advancement, but also can be integrated into current industries and equipment, which is of great help to the improvement of industrial competitiveness.

Although the present invention is described above with preferred examples, it is not intended to limit the spirit and inventive entities of the present invention to the above examples. Those skilled in the art can easily understand and utilize other elements or methods to produce the same effect. Therefore, modifications made without departing from the spirit and scope of the present invention should be included in the scope of the claims.

Claims (7)

1. mixer that utilizes the direct conversion hysteria radio frequency receiver that the complementary metal oxide semiconductors (CMOS) processing procedure makes comprises:

Gain circuitry receives the radiofrequency signal of differential pattern, to produce first gain signal;

Change-over circuit in order to this first gain signal is mixed with local oscillated signal, produces modulation signal with direct frequency reducing; And

Load circuit comprises a pair of the first transistor, a pair of transistor seconds and a pair of impedance unit,

Wherein, described a pair of the first transistor belong to respectively this load circuit the first and the second portion of parallel differentiation, described a pair of transistor seconds also belong to respectively this load circuit the first and the second portion of parallel differentiation,

Described a pair of the first transistor is to have a common gate, with this first that keeps this load circuit and the balance of this second portion,

Described a pair of transistor seconds is to have a common gate, with this first that keeps this load circuit and the balance of this second portion,

In first, an end of the drain electrode of the first transistor, the drain electrode of transistor seconds and impedance unit links to each other, and in second portion, an end of the drain electrode of the first transistor, the drain electrode of transistor seconds and impedance unit links to each other,

This provides gain parameter to impedance unit, this provides Low ESR to the first transistor, so that this modulation signal continues to input to this load circuit, this provides high impedance to transistor seconds, meet second gain signal of this gain parameter with lead this impedance unit and output of this modulation signal that will input to this load circuit

Wherein, this to transistor seconds be by utilize metal-oxide-semiconductor structure parasitism form directly to npn type bipolar transistor, by this, can reduce the noise ratio of this direct conversion hysteria radio frequency receiver.

2. the mixer of direct conversion hysteria radio frequency receiver according to claim 1, wherein this to the first transistor be by utilize metal-oxide-semiconductor structure the horizontal pnp type bipolar transistor that forms of parasitism, to promote the linearity of this direct conversion hysteria radio frequency receiver.

3. the mixer of direct conversion hysteria radio frequency receiver according to claim 1, wherein this first gain signal, this modulation signal and this second gain signal are all differential pattern.

4. the mixer of direct conversion hysteria radio frequency receiver according to claim 1, wherein this is to be selected from electric capacity, resistance or its combination in any to impedance unit.

5. the mixer of direct conversion hysteria radio frequency receiver according to claim 1, wherein this is coupled in resistance so that this high impedance to be provided to transistor seconds.

6. the mixer of direct conversion hysteria radio frequency receiver according to claim 1, wherein this is to form current mirror to transistor seconds.

7. the mixer of direct conversion hysteria radio frequency receiver according to claim 1, wherein this common gate contact to transistor seconds is to be coupled in feedback unit, is fed back with the asymmetric situation of detection signal.

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