CN100444226C - Display panel and display unit - Google Patents

Abstract

The invention discloses a display panel and a display unit. The display unit includes first to fourth switch components, a drive component, a storage capacitor and a light emitting component. The first switch component has an input terminal receiving a data signal and an output terminal coupled to the first node. The second switch component has an input terminal coupled to the first node and an output terminal coupled to the second node. The driving component has a control terminal coupled to the second node, a first terminal coupled to the third node, and a second terminal coupled to the fourth node. The storage capacitor is coupled between the first node and the third node. The third switch component has an input terminal coupled to the second node and an output terminal coupled to the fourth node. The fourth switch component has an input terminal coupled to the first voltage source and an output terminal coupled to the third node. The light emitting component is coupled between the fourth node and the second voltage source.

Description

Display panel and display unit

technical field

The invention relates to a display unit, in particular to a display unit which is suitable for a display panel and can improve the uniformity of a picture.

Background technique

FIG. 1 is a schematic diagram of a panel of a conventional organic light emitting display device. The panel 1 includes a data driver 11 , a scan driver 12 and a display array 13 . The data driver 11 controls several data lines DL ₁ to DL _n , and the scan driver 11 controls several scan lines SL ₁ to SL _m . The display array 13 is formed by interlaced data lines DL ₁ to DL _n and scan lines SL ₁ to SL _m , and each interleaved data line and scan line forms a display unit, for example, data line DL ₁ and scan line The line _SL1 forms the display unit 100 . As shown in the figure, the equivalent circuit of the display unit 100 (other display units are the same) includes a switching transistor T11, a storage capacitor Cs1, a driving transistor T12 and an organic light emitting diode D1, wherein the driving transistor T12 is a PMOS transistor.

The scan driver 11 sequentially sends scan signals to the scan lines SL ₁ to SL _m , so that only the switching transistors of all the display units in a certain column are turned on at the same moment, and the switching transistors of all the display units in other columns are turned off. The data driver 11 sends corresponding video signals (gray scale values) to a column of display units through the data lines DL ₁ to DL _n according to the image data to be displayed. For example, when the scan driver 12 sends a scan signal to the scan line _SL1 , the switching transistor T11 of the display unit 100 is turned on, and the data driver ₁₁ transmits the corresponding video signal to the display unit 100 through the data line DL1, and The voltage of the video signal is stored by the storage capacitor Cs1. The driving transistor T12 provides a driving current Id1 to drive the OLED D1 according to the voltage stored in the storage capacitor Cs1 .

Since the organic light emitting diode D1 is a current-driven component, the value of the driving current Id1 can determine the brightness of the light emitted by the organic light emitting diode D1. Wherein, the driving current Id1 is the drain current of the driving transistor T12, and the driving capability of the driving transistor T12 can be expressed by the following formula:

id1=k(vsg+vth) ²

Wherein, id1 represents the value of the driving current Id1, k represents the conduction parameter of the driving transistor T12, vsg represents the value of the source-gate voltage Vsg of the driving transistor T12, and vth represents the threshold voltage value of the driving transistor T12.

However, due to the technical factors of the thin film transistors, in the display array 13 , the driving transistors in each region are electrically different, that is, the threshold voltage values of the driving transistors are different. Therefore, when several display units in different regions receive video signals with the same voltage, due to differences in the threshold voltages of the driving transistors, the values of the driving currents provided to the OLEDs in these display units are inconsistent, resulting in organic The brightness emitted by the light emitting diodes is different, and the panel 1 will display uneven images.

In addition, referring to FIG. 2, since the driving transistor T12 is a PMOS transistor, the input port 21 of the power line on the panel 1 is coupled to the voltage source Vdd. Likewise, those skilled in the art know that when the driving transistor T12 of the display unit 100 is implemented by NMOS, the input port 21 of the power line is coupled to the voltage source Vss. According to the configuration of the power wires on the panel 1, the farther the display unit from the input port 21 corresponds to the larger equivalent impedance of the power wire, so that the brightness of the display unit closer to the input port 21 is brighter, and the farther the distance from the input port 21 is, the display unit is brighter. The brightness of near and far display units is relatively dark, resulting in uneven brightness.

Contents of the invention

The purpose of the present invention is to provide a display panel and a display unit to solve the problems such as uneven brightness in the above-mentioned known technologies.

In order to achieve the above object, the present invention provides a display panel, which includes several data lines, several first scan lines, several second scan lines and several display units. Several data lines are arranged in sequence, and transmit several data signals respectively. The plurality of first scan lines are arranged in sequence and intersected with the plurality of data lines, and transmit a plurality of first scan signals respectively. The plurality of second scan lines are arranged sequentially and interleaved with the plurality of data lines, and respectively transmit a plurality of second scan signals. The display units are arranged in rows and columns. Wherein, several display units in one row are coupled to the same first and second scan lines, and each display unit corresponds to a set of interlaced first and second scan lines and data lines.

In order to achieve the above object, the present invention provides a display unit including first to fourth switch components, a driving component, a storage capacitor and a light emitting component. The first switch component has an input terminal receiving a data signal and an output terminal coupled to the first node. The second switch component has an input terminal coupled to the first node and an output terminal coupled to the second node. The driving component has a control terminal coupled to the second node, a first terminal coupled to the third node, and a second terminal coupled to the fourth node. The storage capacitor is coupled between the first node and the third node. The third switch component has an input terminal coupled to the second node and an output terminal coupled to the fourth node. The fourth switch component has an input terminal coupled to the first voltage source and an output terminal coupled to the third node. The light emitting component is coupled between the fourth node and the second voltage source.

To sum up, compared with the conventional display panel, the present invention can avoid the uneven picture caused by the electrical difference of the driving components by virtue of the added switch components in the display unit and the control of the scan signal and the data signal. In addition, uneven brightness caused by the arrangement of the power supply wires is also avoided.

The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

Description of drawings

FIG. 1 is a schematic diagram of a panel of a known organic light emitting display device;

Fig. 2 is the configuration of power wires on the panel of Fig. 1;

Fig. 3 shows the display panel of the first embodiment of the present invention;

Fig. 4 shows the timing diagram of the first scanning signal and the second scanning signal of the first embodiment;

Figure 5a and Figure 5b show the equivalent circuit of the display unit of Figure 3 in different periods according to the first embodiment;

Fig. 6 shows the timing diagram of the first scan signal, the second scan signal and the data signal of the second embodiment;

Fig. 7 shows the schematic diagram of the display unit of the third embodiment;

FIG. 8 shows a timing diagram of the first scanning signal, the second scanning signal and the switching signal of the third embodiment;

Fig. 9 shows the display panel of another embodiment;

FIG. 10 shows another embodiment of a display unit whose driving components are implemented with NMOS transistors.

Among them, reference signs:

1 panel; 11 data drivers;

12 scan drivers; 13 display arrays;

100 display unit; Cs1 storage capacitor;

D1 organic light emitting diode; DL ₁ to DL _n data lines;

SL ₁ to SL _m scan lines; T11 switching transistor;

T12 drive transistor; Vdd, Vss voltage source;

21 input ports; 3 panels;

31 data driver; 32 scan driver;

33 display arrays; 300 display units;

Cs3 storage capacitor; D3 light-emitting component;

DL ₁ to DL _n data lines; DS ₁ to DS _n data signals;

Id3 drive current;

SL1 ₁ to SL1 _m , SL2 ₁ to SL2 _m scan lines;

SS1 ₁ to SS1 _m , SS2 ₁ to SS2 _m scanning signals;

SW31 to SW34 switch assemblies;

T3 drive components;

V1, V2, Vdd, Vss voltage sources;

SW35 switch assembly;

Vref reference voltage source;

9 panels;

91, 92 scan driver;

101 display unit;

Id5 driving current

Detailed ways

The first embodiment, FIG. 3 shows the display panel of the first embodiment of the present invention. Please refer to FIG. 3, the display panel 3 includes a data driver 31, a scan driver 32, a display array 33, sequentially arranged data lines DL ₁ to DL _n , sequentially arranged first scan lines SL1 ₁ to SL1 _m , and sequentially arranged Configured second scan lines SL2 ₁ to SL2 _m . The display array 33 is formed by data lines DL ₁ to DL _n interleaved in pairs, first scan lines SL1 ₁ to SL1 _m and second scan lines SL2 ₁ to SL2 _m , and each interleaved data line, the first scan line line and the second scan line form a display unit, for example, the data line DL ₁ , the first scan line SL1 ₂ , and the second scan line SL2 ₂ form the display unit 300 . As shown in the figure, the display units in one row are coupled to the same first and second scan lines, for example, several display units in the same row as the display unit 300 are all coupled to the first scan line _SL1-2 and the second scan line SL2 ₂ . The data driver 31 transmits the data signals DS ₁ to DS _n to the data lines DL ₁ to DL _n respectively. The scan driver 32 respectively transmits the first scan signals SS1 ₁ to SS1 _m to the first scan lines SL1 ₁ to SL1 _m and respectively transmits the second scan signals SS2 ₁ to SS2 _m to the second scan lines SL2 ₁ to SL2 _m .

Please refer to FIG. 3 , the equivalent circuit of the display unit 300 (other display units are the same) of the first embodiment includes first to fourth switch components SW31 to SW34 , storage capacitor Cs3 , driving component T3 and light emitting component D3 . In FIG. 3 , the driving component T3 is a PMOS transistor. The first to fourth switch components SW31 to SW34 may be NMOS or PMOS transistors.

As shown in FIG. 3 , in the display unit 300 , the control terminal of the first switch component SW31 is coupled to the first scan line SL1 ₂ , its input terminal is coupled to the data line DL ₁ , and its output terminal is coupled to the first node N31. A control terminal of the second switch component SW32 is coupled to the second scan line SL2 ₂ , an input terminal thereof is coupled to the first node N31, and an output terminal thereof is coupled to the second node N32. A control terminal of the third switch component SW33 is coupled to the first scan line SL1 ₂ , an input terminal thereof is coupled to the second node N32, and an output terminal thereof is coupled to the fourth node N34. A control terminal of the fourth switch component SW34 is coupled to the second scan line SL2 ₂ , an input terminal thereof is coupled to the first voltage source V 1 , and an input terminal thereof is coupled to the third node N33.

The storage capacitor Cs3 is coupled between the first node N31 and the third node N33. The gate (control terminal) of the driving component T3 is coupled to the second node N32 , the source (first terminal) thereof is coupled to the third node N33 , and the drain (second terminal) thereof is coupled to the fourth node N34 . The light emitting component D3 is coupled between the fourth node N34 and the second voltage source V2. In the embodiment of FIG. 3 , the first voltage source V1 is the voltage source Vdd, and the second voltage source V2 is the voltage source Vss.

FIG. 4 shows a timing diagram of the first scan signal and the second scan signal of the first embodiment. In FIG. 4 , the first scan signal SS1 ₂ and the second scan signal SS2 ₂ corresponding to the display unit 300 are taken as an example for illustration. In the first embodiment, the first to fourth switch components SW31 to 5W34 are NMOS transistors as an example. The first scan signal SS1 ₂ and the second scan signal SS2 ₂ are opposite to each other, and the enable pulse EP2 of the second scan signal SS2 ₂ is delayed by a predetermined period PT41 from the enable pulse EP1 of the first scan signal SS1 ₂ .

Referring to FIG. 4 , during the period PT41 , since the first scan signal SS1 ₂ and the second scan signal SS2 ₂ are both at high level, the first to fourth switch components SW31 to SW34 are all turned on. At this time, the storage capacitor Cs3 is charged by the voltage source Vdd, so that the storage capacitor Cs3 stores a predetermined voltage. Therefore, before the data signal DS ₁ is written, the storage capacitors in all display units are in a common state, so as to facilitate subsequent normal writing. In the period PT42 following the period PT41, the first scan signal _SS12 is maintained at a high level and the second scan signal _SS22 is changed to a low level, therefore, the first and third switches SW31 and SW33 are kept turned on, and The second and fourth switches SW32 and SW34 are turned off. At this time, the data signal _DS1 is written to the storage capacitor Cs3. The equivalent circuit of the display unit 300 in the period PT42 is shown in FIG. 5a, and the voltage across the storage capacitor Cs3 (ie, the voltage stored in the storage capacitor Cs3) is as follows:

Δvcs3＝[vss-(-vd3)-vth]-vds1 (Formula 1)

Wherein, Δvcs3 represents the voltage across the two ends of the storage capacitor Cs3, vss represents the voltage value of the voltage source Vss, vd3 represents the voltage across the light-emitting component D3, vth represents the critical voltage value of the driving component T3, and vds1 represents the voltage value of the data signal _DS1 .

During the period PT43 subsequent to the period PT42, the first scan signal _SS12 and the second scan signal _SS22 are at low level, so the first to fourth switch components SW31 to SW34 are all turned off. The data signal _DS1 stops writing to the storage capacitor Cs3. In the period PT44 following the period PT43, the first scan signal _SS12 is maintained at low level and the second scan signal _SS22 is changed to high level, therefore, the first and third switches SW31 and SW33 are kept closed, and the second The second and fourth switches SW32 and SW34 are turned on. At this time, the driving component T3 provides a driving current Id3 to drive the light emitting component D3 according to the voltage stored in the storage capacitor Cs3. The equivalent circuit of the display unit 300 during the period PT44 is shown in FIG. 5b. According to the principle of charge conservation, the voltage across the storage capacitor Cs3 in the period PT42 is equal to the voltage across the storage capacitor Cs3 in the period PT44, therefore, according to formula 1:

Δvcs3=[vss-(-vd3)-vth]-vds1=vsg (Formula 2)

Wherein, vsg represents the value of the source-gate voltage Vsg of the driving component T3.

Since the light-emitting element D3 is a current-driven element, the value of the driving current Id3 can determine the brightness of the light emitted by the light-emitting element D3. The driving current Id3 is the drain current of the driving component T3, so it can be obtained:

id3∝(vsg+vth) ² (Equation 3)

Wherein, id3 represents the value of the driving current Id3.

According to formula 2 and formula 3, we can get:

id3∝{[vss-(-vd3)-vth]-vds1+vth}＝(vss+vd3-vds1) (Formula 4)

According to Equation 4, it can be known that the driving current Id3 is not affected by the threshold voltage value of the driving component T3. In other words, the luminance of the light-emitting component D3 is not affected by the electrical difference of the driving component caused by the process factors of the thin film transistor. Therefore, it is avoided that the panel displays an uneven picture. In addition, according to Equation 4, it can also be known that the driving current Id3 is not affected by the voltage source Vdd, thereby avoiding uneven brightness caused by the configuration of the power supply wires.

The second embodiment, the second embodiment of the present invention is the same as the first embodiment, except for the timing of the first scan signal, the second scan signal and the data signal, the configuration and structure of the display panel and the display unit are the same. Therefore, the second embodiment will be described with reference to FIG. 3 . FIG. 6 shows a timing diagram of the first scan signal, the second scan signal and the data signal of the second embodiment. In FIG. 6 , the first scan signal SS1 ₂ , the second scan signal SS2 ₂ , and the data signal DS ₁ corresponding to the display unit 300 in FIG. 3 are taken as examples for illustration. In the second embodiment, the first to fourth switch components SW31 to SW34 are NMOS transistors as an example. The first scan signal SS1 ₂ and the second scan signal SS2 ₂ are opposite to each other.

Referring to FIG. 6, in the period PT61, the first scan signal _SS12 is high level and the second scan signal _SS22 is low level, therefore, the first and third switches SW31 and SW33 are turned on, and the second and third switches SW31 and SW33 are turned on, and the second and third switches The four switches SW32 and SW34 are closed. The equivalent circuit of the display unit 300 during the period PT61 is shown in FIG. 5a. At this time, the data signal _DS1 is written to the storage capacitor Cs3. It should be noted here that the voltage of the data signal DS ₁ is at the reference level LVref first, and then changes to the data level LVdata. When the voltage of the data signal _DS1 is at the reference level LVref, the storage capacitor Cs3 stores a voltage having the reference level LVref. Therefore, before the data signal _DS1 with the data level LVdata is written, the storage capacitors in all the display units are discharged according to the reference level LVref and are all in a common state, that is, all the storage capacitors store the voltage with the reference level LVref , to facilitate subsequent normal writing.

When the voltage of the data signal _DS1 changes to the data level LVdata, the storage capacitor Cs3 is charged according to the data level LVdata, and the final voltage across the two ends of the storage capacitor Cs3 during the period PT61 is as shown in Equation 1 above:

Δvcs3＝[vss-(-vd3)-vth]-vds1 (Formula 1)

In the period PT62 following the period PT61, the first scanning signal _SS12 becomes low level and the second scanning signal _SS22 becomes high level, therefore, the first and third switches SW31 and SW33 are closed, and the second And the fourth switches SW32 and SW34 are turned on. At this time, the driving component T3 provides a driving current Id3 to drive the light emitting component D3 according to the voltage stored in the storage capacitor Cs3. The equivalent circuit of the display unit 300 during the period PT62 is shown in FIG. 5b. According to the principle of charge conservation, the final cross-voltage of storage capacitor Cs3 in period PT61 is equal to the cross-voltage of storage capacitor Cs3 in period PT62. Therefore, according to formula 1, formula 2 can be obtained:

Δvcs3=[vss-(-vd3)-vth]-vds1=vsg (Formula 2)

Similarly, since the light-emitting component D3 is a current-driven component, the value of the driving current Id3 can determine the brightness of the light emitted by the light-emitting component D3. The driving current Id3 is the drain current of the driving component T3, so formula 3 can be obtained:

id3∝(vsg+vth) ² (Equation 3)

According to formula 2 and formula 3, formula 4 can be obtained:

id3∝{[vss-(-vd3)-vth]-vds1+vth}＝(vss+vd3-vds1) (Formula 4)

According to Equation 4, it can be known that the driving current Id3 is not affected by the threshold voltage value of the driving component T3. In other words, the luminance of the light-emitting component D3 is not affected by the electrical difference of the driving component caused by the process factors of the thin film transistor. Therefore, it is avoided that the panel displays an uneven picture. In addition, according to Equation 4, it can also be known that the driving current Id3 is not affected by the voltage source Vdd, thereby avoiding uneven brightness caused by the configuration of the power supply wires.

In the second embodiment, for all display units, since the voltage of the data signal DS ₁ is at the reference level LVref first, before the data signal DS ₁ with the data level LVdata is written, the storage capacitor is based on the reference level LVref while discharging. Therefore, the data driver 31 is configured with a pre-discharge function.

The third embodiment, according to the third embodiment of the present invention, the display unit 300 may further include a fifth switch SW35, as shown in FIG. 7 . The control terminal of the fifth switch SW35 receives the switch signal SWS, its input terminal is coupled to the first node N31 , and its output terminal is coupled to the reference voltage source Vref. FIG. 8 is a timing diagram of the first scanning signal, the second scanning signal and the switching signal of the third embodiment. In FIG. 8 , the first scan signal SS1 ₂ , the second scan signal SS2 ₂ and the switch signal SWS corresponding to the display unit 300 in FIG. 7 are taken as an example for illustration. In the third embodiment, the first to fifth switch components SW31 to SW35 are NMOS transistors as an example. The first scan signal SS1 ₂ and the second scan signal SS2 ₂ are opposite to each other.

Referring to FIG. 8, during the period PT81, the first scan signal _SS12 is at a low level, so that the first and third switches SW31 and SW33 are turned off. The second scan signal SS2 ₂ makes the second and fourth switches SW32 and SW34 turn on. The switch signal SWS is at a high level, that is, the enable pulse EP3 appears in the switch signal SWS, so that the fifth switch SW35 is turned on. The storage capacitor Cs3 is then discharged according to the voltage of the reference voltage source Vref. Therefore, before the data signal DS ₁ is written, the storage capacitors in all display units are in a common state, so as to facilitate subsequent normal writing.

During the period PT82 following the period PT81, the first scan signal _SS12 becomes high level, that is, the enable pulse _EP1 appears in the first scan signal SS12, so that the first and third switches SW31 and SW33 are turned on. The second scan signal _SS22 and the switch signal SWS become low level, so that the second, fourth, and fifth switches SW32, SW34, and SW35 are turned off. At this time, the data signal _DS1 is written to the storage capacitor Cs3. The equivalent circuit of the display unit 300 in the period PT82 is shown in FIG. 5a, and the voltage across the two ends of the storage capacitor Cs3 is shown in the above formula 1:

Δvcs3＝[vss-(-vd3)-vth]-vds1 (Formula 1)

During the period PT83 subsequent to the period PT82, the first scan signal _SS12 becomes low level, so that the first and third switches SW31 and SW33 are turned off. The second scan signal SS2 ₂ becomes high level, that is, the enable pulse EP2 appears in the second scan signal SS2 ₂ , so that the second and fourth switches SW32 and SW34 are turned on. The switch signal SWS maintains a low level. At this time, the driving component T3 provides a driving current Id3 to drive the light emitting component D3 according to the voltage stored in the storage capacitor Cs3. The equivalent circuit of the display unit 300 during the period PT83 is shown in FIG. 5b. According to the principle of charge conservation, the final voltage across the storage capacitor Cs3 in PT82 during the period is equal to the voltage across the storage capacitor Cs3 in PT83. Therefore, according to formula 1, formula 2 can be obtained:

Δvcs3=[vss-(-vd3)-vth]-vds1=vsg (Formula 2)

Similarly, since the light-emitting component D3 is a current-driven component, the value of the driving current Id3 can determine the brightness of the light emitted by the light-emitting component D3. The driving current Id3 is the drain current of the driving component T3, so formula 3 can be obtained:

id3∝(vsg+vth) ² (Equation 3)

According to formula 2 and formula 3, formula 4 can be obtained:

id3∝{[vss-(-vd3)-vth]-vds1+vth}=(vss+vd3-vds1) (Formula 4)

According to Equation 4, it can be known that the driving current Id3 is not affected by the threshold voltage value of the driving component T3. In other words, the brightness of the light-emitting component D3 is not affected by the electrical difference of the driving component caused by the process factor of the thin film transistor. Therefore, it is avoided that the panel displays an uneven picture. In addition, according to Equation 4, it can also be known that the driving current Id3 is not affected by the voltage source Vdd, thereby avoiding uneven brightness caused by the configuration of the power supply wires.

In the third embodiment, since the enable pulse EP1 of the first scan signal _SS12 is continuous with the enable pulse EP3 of the switch signal SWS, it can be known that the switch signal SWS may correspond to the display unit in the previous column of the display unit 300 The first scan signal SS1 ₁ . In other words, in the display unit 300 , the control terminal of the fifth switch SW35 can be coupled to the first scan line SL1 ₁ to receive the first scan signal SS1 ₁ .

Referring to FIG. 3 , according to the first to third embodiments of the present invention, the first scan signals SS1 ₁ to SS1 _m and the second scan signals SS2 ₁ to SS2 _m are provided by the scan driver 32 . In some embodiments, the first scan signals SS1 ₁ to SS1 _m and the second scan signals SS2 ₁ to SS2 _m may be respectively provided by two different scan drivers. Referring to FIG. 9 , the difference between the display panel 9 of FIG. 9 and the display panel 3 of FIG. 3 is that the display panel 9 includes two scan drivers 91 and 92 . Wherein, the scan driver 91 respectively transmits the first scan signals SS1 ₁ to SS1 _m to the first scan lines SL1 ₁ to SL1 _m , and the scan driver 92 respectively transmits the second scan signals SS2 ₁ to SS2 _m to the second scan lines SL2 ₁ to SL2 _m .

In addition, according to the first to third embodiments of the present invention, the driving component T3 of the display unit 300 is an example for illustration, but not limited thereto. Those skilled in the art know that the driving component T3 of the display unit 300 can also be implemented by NMOS transistors, as shown in FIG. 10 . The display unit 101 includes the same first to fourth switching components SW31 to SW34 , a storage capacitor Cs3 , and a light emitting component D3 as the display unit 300 except for the driving component T10 implemented in NMOS. Since the driving component T10 implemented with NMOS transistors replaces the driving component T3 implemented with PMOS transistors, the circuit configuration of the display unit 101 is correspondingly changed. In addition, in FIG. 10 , the first voltage source V1 is the voltage source Vss, and the second voltage source V2 is the voltage source Vdd.

When the signal timings of the first to third embodiments are applied to the display unit 101, the following can be obtained:

id5∝(vgs-vth)=(vds1-vdd+vd3) (Formula 5)

Among them, id5 represents the value of the driving current Id5, vgs represents the value of the gate-source voltage Vgs of the driving component T10, vth represents the critical voltage value of the driving component T10, and vds1 is the voltage value of the data signal _DS1 , vdd represents the voltage source The voltage value of Vdd, and vd3 represent the voltage across the light-emitting component D3.

According to Equation 5, it can be known that the driving current Id5 is not affected by the threshold voltage value of the driving component T10. In other words, the brightness of the light-emitting component D3 is not affected by the electrical difference of the driving component caused by the process factor of the thin film transistor. Therefore, it is avoided that the panel displays an uneven picture. In addition, according to Equation 5, it can also be known that the driving current Id5 is not affected by the voltage source Vss, thereby avoiding uneven brightness caused by the configuration of the power supply wires.

It should _be noted here _that when the signal timing diagram of the first embodiment in FIG. Therefore, the first to fourth switch components SW31 to SW34 are all turned on. At this time, the storage capacitor Cs3 is discharged by the voltage source Vss, so that the storage capacitor Cs3 stores a predetermined voltage.

To sum up, compared with the known display panel, according to the embodiment of the present invention, with the help of the added switch components in the display unit and the control of the scan signal and the data signal, it is possible to avoid the unfavorable electrical differences of the drive components. Uniform picture. In addition, uneven brightness caused by the arrangement of the power supply wires is also avoided.

Certainly, the present invention also can have other multiple embodiments, without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and deformations according to the present invention, but these corresponding changes All changes and modifications should belong to the scope of protection of the appended claims of the present invention.

Claims (25)

1. A display unit, characterized in that it comprises: A first switch component has an input terminal receiving a data signal and an output terminal coupled to a first node; a second switch element having an input terminal coupled to the first node and an output terminal coupled to a second node; a driving component having a control terminal coupled to the second node, a first terminal coupled to a third node, and a second terminal coupled to a fourth node; a storage capacitor coupled between the first node and the third node; a third switch element having an input terminal coupled to the second node and an output terminal coupled to the fourth node; a fourth switch element having an input terminal coupled to a first voltage source and an output terminal coupled to the third node; and A light emitting component is coupled between the fourth node and a second voltage source. 2. The display unit according to claim 1, wherein the first and third switch elements are controlled by a first signal, and the second and fourth switch elements are controlled by a second signal. 3. The display unit according to claim 2, wherein the first and second signals are opposite phases, and the enabling pulse of the second signal is delayed by a predetermined period of time from the enabling pulse of the first signal. 4. The display unit according to claim 2, further comprising a fifth switch component having a control terminal, an input terminal coupled to the first node, and an output terminal coupled to a reference voltage source . 5. The display unit according to claim 4, wherein before the first switch element is turned on according to the enable pulse of the first signal, the fifth switch is turned on, so that the storage capacitor is turned on according to the reference The voltage of the voltage source is discharged. 6. The display unit according to claim 4, wherein when the first switch component is turned on according to the enable pulse of the first signal, the storage capacitor is charged according to the data signal. 7. The display unit according to claim 4, wherein the fifth switch component is controlled by a switch signal, and the enable pulse of the first signal is followed by the enable pulse of the switch signal. 8. The display unit according to claim 1, wherein the first to fourth switch elements are simultaneously turned on within a predetermined time. 9. A display panel, characterized by comprising: Several data lines are arranged in sequence to transmit several data signals respectively; A plurality of first scan lines arranged in sequence and interleaved with the data line for respectively transmitting a plurality of first scan signals; Several second scanning lines are arranged sequentially and interleaved with the data line, for respectively transmitting several second scanning signals; A plurality of display units arranged in several rows and columns, wherein the display units of one row are coupled to the same first and second scanning lines, and each display unit corresponds to a group of interlaced first and second scanning lines and the data line, and each display unit includes: A first switch component, having a control end coupled to the corresponding first scan line, an input end coupled to the data line, and an output end coupled to a first node; a second switch component, having a control end coupled to the corresponding second scan line, an input end coupled to the first node, and an output end coupled to a second node; a driving component having a control terminal coupled to the second node, a first terminal coupled to a third node, and a second terminal coupled to a fourth node; a storage capacitor coupled between the first node and the third node; a third switch element, having a control end coupled to the corresponding first scan line, an input end coupled to the second node, and an output end coupled to the fourth node; a fourth switch element, having a control terminal coupled to the corresponding second scan line, an input terminal coupled to a first voltage source, and an output terminal coupled to the third node; and A light emitting component is coupled between the fourth node and a second voltage source. 10. The display panel according to claim 9, wherein, for the display units of one row, the first and second scanning signals are opposite to each other, and the enabling pulse of the second scanning signal is delayed by the first scanning signal. An enabling pulse of a scanning signal has a predetermined period. 11. The display panel according to claim 10, wherein for each of the display units, the storage capacitor is discharged within the predetermined period. 12. The display panel according to claim 9, wherein, for a row of the display units, the first and second scanning signals are opposite to each other. 13. The display panel according to claim 12, wherein, for each display unit, when the first switch element is turned on according to the first scanning signal, the storage capacitor is based on a reference of the data signal level to discharge. 14. The display panel according to claim 13, wherein for each display unit, after the storage capacitor is discharged, the storage capacitor is charged according to a data level of the data signal. 15. The display panel according to claim 9, wherein each display unit further comprises a fifth switch element having a control terminal, an input terminal coupled to the first node, and a reference voltage an output of the source. 16. The display panel according to claim 15, wherein, for a row of the display units, the first and second scanning signals are opposite to each other. 17. The display panel according to claim 15, wherein for each display unit, before the first switch component is turned on according to the enable pulse of the first scan signal, the fifth switch component is turned on is turned on so that the storage capacitor is discharged according to the voltage of the reference voltage source. 18. The display panel according to claim 17, wherein, for each of the display units, when the first switch element is turned on according to the enable pulse of the first scan signal, the storage capacitor according to the data signal to charge. 19. The display panel according to claim 15, wherein for each of the display units, the control terminal of the fifth switch component receives a switch signal, and the enable pulse of the first scanning signal is continuous with the Enable pulse for switching signal. 20. The display panel according to claim 19, wherein for each display unit, the switch signal is the first scan signal of the previous first scan line. 21. The display panel according to claim 15, wherein for each display unit, the control terminal of the fifth switch component is coupled to the previous first scan line. 22. The display panel according to claim 9, wherein, for each of the display units, the first to fourth switch components are simultaneously turned on within a predetermined period. 23. The display panel according to claim 22, wherein for each of the display units, the storage capacitor is charged/discharged within the predetermined period. 24. The display panel according to claim 19, further comprising: a data driver for providing the data signal to the data line; and A scan driver is used for providing the first scan signal to the first scan line and providing the second scan signal to the second scan line. 25. The display panel according to claim 19, further comprising: a data driver for providing the data signal to the data line; a first scan driver, used to provide the first scan signal to the first scan line; and A second scan driver is used for providing the second scan signal to the second scan line.

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