CN100449737C - Thin film transistor array substrate and method of manufacturing the same - Google Patents

Abstract

The invention relates to a thin film transistor array substrate and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: a thin film transistor is formed on the active area of the substrate and the contact pad is formed on the peripheral area of the substrate. An inorganic insulating layer and an organic insulating layer are sequentially formed to cover the thin film transistor and the contact pad. And patterning the organic insulating layer. And etching the inorganic insulating layer uncovered by the organic insulating layer with sulfur hexafluoride/oxygen to form a first contact window with a first inclined side wall on the peripheral region and a second contact window with a second inclined side wall on the active region, and leaving a part of the organic insulating layer on the peripheral region. Wherein the flow ratio of sulfur hexafluoride/oxygen is approximately between 0.33 and 0.42. A patterned conductor protection layer is formed on the contact window.

Description

Thin film transistor array substrate and manufacturing method thereof

technical field

The present invention relates to a thin film transistor and its manufacturing method, and in particular to a display panel using the thin film transistor array substrate.

Background technique

In recent years, optoelectronic-related technologies have been continuously introduced, coupled with the arrival of the digital age, which has further promoted the vigorous development of the liquid crystal display market. Liquid Crystal Display (LCD) is widely used in portable TVs, mobile phones, notebooks, etc. Consumer electronics or computer products such as computers, desktop monitors, and projection TVs have replaced cathode ray tubes (Cathode Ray Tube; CRT) as the mainstream of displays.

Generally, the main body of a liquid crystal display is a liquid crystal unit, which is mainly composed of two transparent substrates and a liquid crystal sealed between the substrates. At present, liquid crystal displays are mainly thin film transistor (Thin Film Transistor; TFT) liquid crystal displays, and the production of general thin film transistor liquid crystal displays can be roughly divided into thin film transistor array (TFT Array) technology, color filter (Color Filter) technology, liquid crystal Display unit assembly (LC Cell Assembly) process and liquid crystal display module (Liquid CrystalModule; LCM) process.

Among them, the liquid crystal display module assembly process is an assembly process in which a metal frame, a liquid crystal display panel and a backlight module (Backlight Module) are combined, and the manufacture of the entire liquid crystal display screen is completed after the combination. Commonly used module assembly technologies include Chip on Glass (COG), Chip on Film (COF) and Tape Automatic Bounding (TAB).

Please refer to FIG. 1 , which shows a top view of the structure of a known liquid crystal display. In FIG. 1 , the LCD has a lower glass 102 , an upper glass 104 , a liquid crystal display panel 106 , a data pad portion 108 and a gate pad portion 110 . Wherein, the liquid crystal display panel 106 has many liquid crystal cells (not shown), and each liquid crystal cell has a pixel electrode. It can be seen from FIG. 1 that the lower glass 102 does not overlap with the upper glass 104 at all, and the space reserved in the periphery of the lower glass 102 is used as the signal contact pad region 108 and the gate contact pad region 110 to electrically connect the integrated circuit (integrated circuit). circuits; IC).

Please refer to FIG. 2 , which is a schematic cross-sectional view of a contact pad in a peripheral region of a conventional liquid crystal display panel. In FIG. 2 , the contact pads 122 are located on the substrate 120 , and the inorganic insulating layer 124 and the organic protection layer 126 sequentially cover the substrate 120 and the contact pads 122 . There is a contact window 128 in the inorganic insulating layer 124 and the organic protective layer 126 on the contact pad 122, and the conductor protective layer 130 is located on the inorganic insulating layer 124 and the organic protective layer 126, in the contact window 128, to electrically connect the contact pad 122.

Generally, in the liquid crystal display module assembly process, the driver IC and the contact pad 122 located in the liquid crystal display panel are connected together using TAB technology, and a layer of anisotropic conductive film (anisotropic film) is attached between the contact pad 122 and the driver IC. conductive film, ACF), to electrically connect the contact pad 122 with the driving IC. Furthermore, in the assembly process of the liquid crystal display module, the driving IC and the contact pads 122 in the liquid crystal display panel can also be connected together by using COG (chip on glass) technology. However, when the above technique is implemented and the contact pad 122 cannot be accurately aligned with the driver IC, it is necessary to perform a rework process (IC Rework), first separating the driver IC from the contact pad 122 and then pasting it again. However, an organic solvent (such as acetone) will be used to separate the driver IC from the contact pad 122 in the rework process. It is inevitable that the organic solvent in the rework process will affect the stability of the organic protective layer 126, and due to the original inorganic The adhesion between the insulating layer 124 and the organic protection layer 126 is weak, so when the driver IC is removed from the contact pad 122, part of the organic protection layer 126 and the conductor protection layer 130 on the organic protection layer 126 will also be damaged. Removed together when recrafting. In this way, the organic protection layer 126 and the conductor protection layer 130 are damaged, thereby reducing the production yield and increasing the manufacturing cost.

In view of this, U.S. Patent No. 6,650,380 proposes a method to improve the above-mentioned shortcomings, which removes the organic protection layer on the contact pad after forming the contact window, so that the subsequently formed conductor protection layer directly covers the inorganic protection layer with better adhesion. layer. However, it can be seen from Figure 3A (the schematic cross-sectional structure diagram of the thin-film transistor array substrate in the known liquid crystal display panel along the AA', BB', and CC' section lines in Figure 3B) , the biggest difficulty of this method is that since the second contact window 216b above the source/drain electrodes 206a, 206b and the first contact window 216a, 216c above the contact pads 204, 208 are formed at the same time, if the contact pads 204, 208 When the organic protection layer 212 on the top is completely removed, the sidewalls of the organic protection layer 212 and the inorganic insulating layer 210 of the second contact window 216b above the etched source/drain electrodes 206a, 206b will present an approximately vertical profile ( profile), so when the subsequent deposition of the pixel electrode 214b covers the organic protective layer 212, there will be a problem of poor step coverage.

Therefore, it is necessary to provide a new method of manufacturing thin film transistors to solve the problem that the stability of the organic protective layer is affected by the use of organic solvents during the subsequent IC rework process, thereby causing the conductor protective layer on the contact pad to break. At the same time, the difficulty of step coverage during the formation of the conductor protection layer is reduced, so as to improve the product yield.

Contents of the invention

Therefore, the object of the present invention is to provide a thin film transistor array substrate and a manufacturing method thereof, which are used to reduce the difficulty of step coverage during the formation of the conductor protection layer.

Another object of the present invention is to provide a thin film transistor array substrate and its manufacturing method to solve the problem of swelling of the organic protective layer due to the use of organic solvents in the subsequent reworking process of driving ICs, which is easy to cause in the IC reworking process Problems with detachment causing cracking of the conductor shield on the contact pads.

Another object of the present invention is to provide a thin film transistor array substrate and a manufacturing method thereof, so as to improve product yield and reduce manufacturing cost.

According to the object of the present invention, a thin film transistor array substrate and a manufacturing method thereof are proposed. According to a preferred embodiment of the present invention, a substrate is provided, and thin film transistors and contact pads are respectively formed on the active region and the peripheral region on the substrate. The thin film transistor has a gate, a source and a drain. Next, an inorganic insulating layer and an organic insulating layer are sequentially formed on the thin film transistor and the contact pad. Wherein, the above-mentioned inorganic insulating layer has a thickness of 0.3 micrometers (μm), and the organic insulating layer has a thickness roughly between 5.3 micrometers (μm) and 5.6 micrometers (μm).

Expose and develop the organic insulating layer by using a half-tone mask to form at least one first contact window and at least one second contact window on the inorganic insulating layer on the substrate, and expose the inorganic insulating layer on the contact pad and the drain electrode respectively layer. wherein the thickness of the organic insulating layer on the peripheral region is smaller than the thickness of the organic insulating layer on the active region

Subsequently, the organic insulating layer and the inorganic insulating layer exposed by the contact window are etched with sulfur hexafluoride/oxygen until the contact pad and the drain are exposed. Wherein, the flow ratio of sulfur hexafluoride/oxygen is roughly between 0.33-0.42.

At this time, a first contact window with a first slanted sidewall and a second contact window with a second slanted sidewall are respectively formed above the contact pad and the source electrode, and a thinner organic insulating layer remains on the peripheral region. layer, and a thicker organic insulating layer remains on the active region. Wherein, the angle of the first contact window with the first inclined sidewall is smaller than the angle of the second contact window with the second inclined sidewall, and the angle of the first contact window with the first inclined sidewall is preferably between 20°～ The angle of the second contact window with the second inclined sidewall is preferably between 60° and 80°.

Finally, a patterned conductor protection layer is formed on the first contact window and the second contact window. Wherein, the thickness of the organic insulating layer remaining on the upper portion of the peripheral region is approximately between 0.3 micrometer (μm) and 0.5 micrometer (μm).

In a preferred embodiment of the present invention, in order to prevent the organic insulating layer on the peripheral region from remaining on the contact pads, the part of the inorganic insulating layer exposed by etching the organic insulating layer and the contact window with sulfur hexafluoride/oxygen can be further exposed. After the step of removing the contact pad and the drain electrode, the organic insulating layer is etched with oxygen as an etchant to ensure that no organic insulating layer remains on the contact pad.

From the above, it can be known that applying the method of the present invention can subsequently etch out relatively gentle contours on the sidewalls of the first contact window and the second contact window for forming the conductor protection layer, so as to reduce the step coverage during the formation of the conductor protection layer. difficulty. Moreover, the application of the method of the present invention can further solve the problem that the stability of the organic protective layer is affected by the use of organic solvents in the subsequent heavy-duty process of driving ICs, and the adhesion between the original inorganic insulating layer and the organic protective layer is relatively insufficient. , which in turn causes the problem of cracking of the conductor protection layer on the contact pad. In addition, the method of the present invention can improve product yield and reduce manufacturing cost at the same time.

Description of drawings

In order to make the above and other objects, features, advantages and embodiments of the present invention more comprehensible, the detailed description of the accompanying drawings is as follows:

FIG. 1 shows a top view of the structure of a known liquid crystal display.

FIG. 2 is a schematic cross-sectional view of a contact pad in a peripheral region of a conventional liquid crystal display panel.

Fig. 3A is a schematic cross-sectional structure diagram of a thin film transistor array substrate in a known liquid crystal display panel along the lines A-A', B-B', and C-C' in Fig. 3B.

FIG. 3B is a schematic top view of a conventional thin film transistor array substrate.

FIG. 4 is a schematic top view of a thin film transistor array substrate according to a preferred embodiment of the present invention.

Figures 5A to 5G are structural schematic diagrams of a process step for manufacturing a thin film transistor array substrate along the I-I', J-J', and K-K' section lines in Figure 4.

[Description of main component symbols]

10: Gate line 14: Gate contact pad area 20: Signal electrode

32: Gate contact pad 50, 60, 206a, 206b: Source/drain electrodes

70a, 70a', 216a, 216c: first contact windows

102: Lower glass 106: Liquid crystal display panel

110: Gate contact pad area 122, 204, 208: Contact pads

126: Organic protective layer 130, 214a, 214c, 42a, 42b: Conductor protective layer

202, 302: insulating layer 306: ohmic contact layer 312: half-tone mask

320: First sloped side wall 322: Second sloped side wall

12: Image display area 15: Contact pad area

16: Signal contact pad area 30: Gate

40, 214b: pixel electrode 52: signal contact pad

70b, 70b', 216b: second contact window

104: Upper glass 108: Signal contact pad area

120, 200: Substrate 124, 210, 308: Inorganic insulating layer

128: Contact window 206: Inorganic protective layer

300: substrate 304: semiconductor layer

212, 310, 310a, 310b, 310c, 310a', 310b', 310c': organic insulating layer

A-A', B-B', C-C', I-I', J-J', K-K': hatching

Detailed ways

Please refer to FIG. 4 , which shows a schematic top view of a thin film transistor array substrate according to a preferred embodiment of the present invention. In FIG. 4 , the TFT array substrate includes an image display area 12 and a contact pad area 15 . Wherein, the contact pad region 15 includes a gate contact pad region 14 and a signal contact pad region 16 . The gate contact pad region 14 and the signal contact pad region 16 are electrically connected to a driving IC (not shown).

The image display area 12 has thin film transistors (thin film transistors; TFTs), pixel electrodes 40 , gate lines (scanning lines) 10 and signal lines or signal electrodes (data lines) 20 . Wherein, the thin film transistor further includes a gate 30 , source/drain electrodes 50 and 60 . The pixel electrode 40 is electrically connected to the drain electrode 60 through the second contact window 70b.

The gate contact pad region 14 is located at the end of the gate line 10 for electrically connecting to a driving IC (not shown). And the gate contact pad region 14 includes a gate contact pad 32 and a conductor protection layer 42b. Wherein, the gate contact pad 32 is connected to the gate line 10 , and the conductor protection layer 42 b is connected to the gate driving IC (not shown).

The signal contact pad area 16 is located at the end of the signal line 20 for electrically connecting to a driver IC (not shown). And the signal contact pad area 16 includes a signal contact pad 52 and a conductor protection layer 42a. Wherein, the signal contact pad 52 is connected to the signal line 20 , and the conductor protection layer 42 a is connected to the signal driving IC (not shown).

Please refer to Figures 5A-5G, which are schematic structural diagrams of a process step for manufacturing a thin film transistor array substrate along the I-I', J-J', and K-K' section lines in Figure 4. In Figures 5A to 5G, II' shows the schematic cross-sectional structure of the gate contact pad on the peripheral region, J-J' shows the schematic cross-sectional structure of the thin film transistor in the active region, and K-K' Shown is a schematic cross-sectional structure diagram of the signal contact pads on the peripheral area.

In FIG. 5A, a conductive layer (not shown) is first deposited on the substrate 300, and then the conductive layer is defined by the first photomask process, and the gate 30 and the gate contact are respectively formed on the active area and the peripheral area of the gate. Pad 32. Wherein, the substrate 300 is preferably a glass substrate, a silicon substrate, a ceramic substrate, a plastic substrate or a flexible substrate. The preferred material of the conductor layer is molybdenum, aluminum, copper, chromium, titanium, silver or any combination of the above materials, and the conductor layer can be a single-layer or multi-layer structure formed of the above materials.

In FIG. 5B , an insulating layer 302 , a semiconductor layer 304 and an ohmic contact layer 306 are sequentially formed on the substrate 300 , the gate 30 and the gate contact pad 32 . Next, the semiconductor layer 304 and the ohmic contact layer 306 are lithographically etched until the insulating layer 302 on the peripheral area and other parts of the insulating layer 302 above the gate 30 on the active area are exposed. Among them, the preferred material of the insulating layer 302 is silicon nitride, silicon oxynitride, silicon oxide or a single-layer or multi-layer structure formed of the above-mentioned materials. A preferred material of the semiconductor layer 304 is amorphous silicon, polycrystalline silicon, microcrystalline silicon or a group formed by any combination thereof. The preferred doping material of the aforementioned ohmic contact layer 306 may be N-type doping or P-type doping.

Next, as shown in FIG. 5C, a metal layer (not shown) is deposited on the substrate 300, and then the metal layer and the Ohm contact layer 306 are defined by a lithographic etching process to form the source electrode 50, the drain electrode 60 and the The channel area 54 is on the active area, and the signal contact pad 52 is formed on the signal peripheral area. Among them, the preferred material of the above metal layer is molybdenum, aluminum, copper, chromium, titanium, silver or any combination of the above materials formed alloys or a group consisting of multi-layer metal layers.

As shown in FIG. 5D, an inorganic insulating layer 308 and an organic insulating layer 310 are sequentially deposited on the substrate 300, and then a half-tone mask 312 is provided for subsequent exposure and development of the organic insulating layer 310, which is formed after multi-level exposure. Patterned organic insulating layer 310 with different thicknesses. The above-mentioned inorganic insulating layer 308 is made of silicon nitride, silicon oxide, silicon oxynitride or any combination thereof, and the thickness of the inorganic insulating layer 308 is preferably 0.3 microns (μm). The above-mentioned material of the organic insulating layer 310 includes a photosensitive material, and the thickness of the organic insulating layer 310 is preferably between 5.3 micrometers (μm) and 5.6 micrometers (μm).

Next, as shown in FIG. 5E , the organic insulating layer 310 is exposed and developed by using the half tone mask 312 to form a patterned organic insulating layer 310 on the inorganic insulating layer 308 on the substrate 300 . At this time, the first contact window 70a and the second contact window 70b are respectively formed in the patterned organic insulating layer 310 on the substrate 300 above the gate contact pad 32/signal contact pad 52 and the drain electrode 60, and the gate contact is exposed. The portion of the inorganic insulating layer 308 above the pad 32 /signal contact pad 52 and the drain electrode 60 . Since the photomask 312 is a half-tone photomask, the organic insulating layer 310 after development will have different thicknesses in different regions due to the different exposure levels of each region. The thickness of the organic insulating layers 310a and 310c on the peripheral area may be smaller than the thickness of the organic insulating layer 310b on the active area. Wherein, in a preferred embodiment, the thickness of the organic insulating layers 310a and 310c on the peripheral region is approximately between 0.9 micrometers (μm) and 1.4 micrometers (μm), while the thickness of the organic insulating layer 310b on the active region Roughly between 4.6 microns (μm) and 4.9 microns (μm).

In order to solve the problem that the conductor protective layer on the contact pad is broken due to the use of organic solvents in the IC rework process, and can simultaneously reduce the problem of poor step coverage during the formation of the conductor protective layer, a preferred embodiment of the present invention uses By changing the etching conditions, inclined sidewalls are formed on the sidewalls of the first contact window and the second contact window where the conductor protection layer will be formed later. Please refer to Figure 5F. In Figure 5F, the organic insulating layers 310a, 310b, and 310c are used as masks, and the etching process is performed using sulfur hexafluoride/oxygen as an etchant, and the inorganic insulating layers not covered by the organic insulating layers 310a, 310b, and 310c are etched. layer 308 until a portion of the gate contact pad 32 , the signal contact pad 52 and the drain electrode 60 are exposed.

As shown in Figure 5F, since the flow ratio of sulfur hexafluoride/oxygen is controlled between 0.33-0.42, the first contact window 70a' and the second contact window 70a' formed on the peripheral area and the active area after etching The contact window 70b' has a first inclined sidewall 320 and a second inclined sidewall 322 respectively. At this time, part of the organic insulating layers 310a' and 310c' will remain on the peripheral area, and a relatively thick organic insulating layer 310b' will remain on the active area, and there are no more on the gate contact pad 32 and the signal contact pad 52. The organic insulating layers 310a' and 310c'.

Wherein, the first included angle formed between the first inclined sidewall 320 and the gate contact pad 32 /signal contact pad 52 is smaller than the second included angle formed between the second inclined sidewall 322 and the drain electrode 60 . The first included angle on the peripheral area is preferably between 20°-50°, and the second included angle on the active area is preferably between 60°-80°. The thickness of the organic insulating layers 310a' and 310c' remaining on the peripheral region is preferably between 0.3 micrometer (μm) and 0.5 micrometer (μm).

Finally, as shown in FIG. 5G, a conductive protection layer (not shown) is formed on the organic insulating layers 310a', 310b' and 310c', and fills the first contact window 70a' and the first contact window 70a' on the peripheral area and the active area. The second contact window 70b'. Then, a photomask process is performed on the conductive protection layer to form a patterned conductive protection layer, and the pixel electrode 40 and the conductive protection layers 42a, 42b are defined on the active area and the peripheral area respectively. Wherein, the material of the above-mentioned conductor protection layer is preferably indium tin oxide, aluminum zinc oxide, indium zinc oxide, indium oxide, tin oxide or a conductor protection layer formed by any combination of the above.

In a preferred embodiment of the present invention, in order to prevent the organic insulating layers 310a' and 310c' on the peripheral region from remaining on the gate contact pad 32 and the signal contact pad 52, the part can be etched with sulfur hexafluoride/oxygen After the step of using the organic insulating layer 310a, 310b and 310c of the exposed part of the inorganic insulating layer 308 above the AND gate contact pad 32, the signal contact pad 52 and the drain electrode 60, the organic insulating layer 310a' and the organic insulating layer 310a' are etched with oxygen as an etchant. 310c′ to ensure that the organic insulating layers 310a′ and 310c′ do not remain on the gate contact pad 32 and the signal contact pad 52 . Among them, the above-mentioned flow rate of oxygen is preferably 500 sccm.

From the above, it can be known that applying the method of the present invention can utilize the adjustment of the etching conditions of sulfur hexafluoride/oxygen to etch out a relatively gentle layer on the sidewalls of the first contact window and the second contact window that will form the conductor protection layer later. profile to reduce the difficulty of step coverage during the formation of the conductor protective layer. Moreover, the application of the method of the present invention can further solve the problem that the stability of the organic protective layer is affected by the use of organic solvents in the subsequent heavy-duty process of driving ICs, and the adhesion between the original inorganic insulating layer and the organic protective layer is relatively insufficient. , which in turn causes the problem of cracking of the conductor protection layer on the contact pad. In addition, the method of the present invention can improve product yield and reduce manufacturing cost at the same time.

Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make various modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the claims.

Claims (23)

1. A method for manufacturing a thin film transistor array substrate, comprising: forming at least one thin film transistor on the active area of the substrate and at least one contact pad on the peripheral area of the substrate, and the thin film transistor has a gate, a source and a drain; forming an inorganic insulating layer covering the thin film transistor and the contact pad; forming an organic insulating layer on the inorganic insulating layer; patterning the organic insulating layer to form at least one first contact window and at least one second contact window, and respectively exposing the inorganic insulating layer on the contact pad and the source/drain, and on the peripheral region The thickness of the organic insulating layer is smaller than the thickness of the organic insulating layer on the active region; Etching the organic insulating layer and the inorganic insulating layer exposed by the first and second contact windows with sulfur hexafluoride/oxygen until the contact pad and the source/drain are exposed, so that the first contact forming a first inclined sidewall on the sidewall of the window and forming a second inclined sidewall on the sidewall of the second contact window, and leaving part of the organic insulating layer on the peripheral region, wherein the sulfur hexafluoride/oxygen The flow ratio is between 0.33 and 0.42; and A patterned conductor protection layer is formed on the first and second contact windows. 2. The method of claim 1, wherein the contact pad is formed simultaneously with the gate. 3. The method of claim 1, wherein the contact pad is formed simultaneously with the source and the drain. 4. The method of claim 1, wherein the thickness of the inorganic insulating layer is 0.3 microns. 5. The method of claim 1, wherein the organic insulating layer has a thickness ranging from 5.3 microns to 5.6 microns. 6. The method of claim 1, wherein the thickness of the organic insulating layer on the peripheral region is between 0.9 μm and 1.4 μm. 7. The method of claim 1, wherein the thickness of the organic insulating layer on the active region is between 4.6 microns and 4.9 microns. 8. The method of claim 1, wherein the organic insulating layer and the inorganic insulating layer exposed by the first and second contact windows are etched with sulfur hexafluoride/oxygen to expose the contact pad and the source/the After the drain step, further include: The organic insulating layer is etched with oxygen to ensure that the organic insulating layer does not remain on the contact pad, and the oxygen flow rate is 500 sccm. 9. The method of claim 8, wherein the thickness of the organic insulating layer remaining on the peripheral region is between 0.3 μm and 0.5 μm. 10. The method of claim 1, wherein the material of the inorganic insulating layer comprises silicon nitride, silicon oxide, silicon oxynitride or a group formed by any combination thereof. 11. The method of claim 1, wherein a material of the organic insulating layer comprises a photosensitive material. 12. The method of claim 1, wherein the material of the patterned conductor protection layer comprises indium tin oxide, aluminum zinc oxide, indium zinc oxide, indium oxide, tin oxide or a group formed by any combination thereof. 13. The method of claim 1, wherein an angle between the first sloped sidewall of the first contact and the contact pad is smaller than that between the second sloped sidewall of the second contact and the source/drain angle between. 14. The method of claim 13, wherein an angle of the first contact window having a first inclined sidewall is between 20°˜50°. 15. The method of claim 13, wherein an angle of the second contact window having a second sloped sidewall is between 60° and 80°. 16. A thin film transistor array substrate, comprising: At least one thin film transistor is disposed on the active area of the substrate, and the thin film transistor has a gate, a source and a drain; at least one contact pad disposed on the peripheral area of the substrate; an inorganic insulating layer disposed on the thin film transistor and the contact pad; The organic insulating layer is disposed on the inorganic insulating layer, and the inorganic insulating layer and the organic insulating layer have at least one first contact window to expose the contact pad and at least one second contact window to expose the drain/ For the source, a first angle is formed between the sidewall of the first contact window and the contact pad, and a second angle is formed between the sidewall of the second contact window and the drain/source, wherein, The thickness of the organic insulating layer on the peripheral region is smaller than the thickness of the organic insulating layer on the active region, and the first included angle is smaller than the second included angle; and The conductor protection layer is arranged on the first and second contact windows. 17. The thin film transistor array substrate of claim 16, wherein the thickness of the organic insulating layer on the peripheral region is between 0.3 microns and 0.5 microns. 18. The thin film transistor array substrate according to claim 16, wherein the thickness of the inorganic insulating layer is 0.3 microns. 19. The thin film transistor array substrate of claim 16, wherein the angle range of the first included angle is between 20°-50°. 20. The thin film transistor array substrate as claimed in claim 16, wherein the angle range of the second included angle is between 60°-80°. 21. The thin film transistor array substrate according to claim 16, wherein the material of the inorganic insulating layer comprises silicon nitride, silicon oxide, silicon oxynitride or a group formed by any combination thereof. 22. The thin film transistor array substrate as claimed in claim 16, wherein the material of the organic insulating layer comprises a photosensitive material. 23. The thin film transistor array substrate according to claim 16, wherein the material of the conductor protection layer comprises indium tin oxide, aluminum zinc oxide, indium zinc oxide, indium oxide, tin oxide or a group formed by any combination thereof.

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