CN100440737C - High structural LDPC coding and decoding method and coder and decoder - Google Patents
High structural LDPC coding and decoding method and coder and decoder Download PDFInfo
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Abstract
The present invention provides a high structural LDPC coding and decoding method. The coding method comprises that a check matrix generation unit of a coder is used for generating a parity check matrix according to the code rate, the line weight and the row weight of HS-LDPC codes which are set in advance; a generated result is inputted into a code synthesizing unit of the coder; the code synthesizing unit synthesizes and computes inputted data information and the parity check matrix for outputting the data information merged by a parity check information bit and the bit of the inputted data information; the decoding method comprises that a variable node unit of the coder is preset according to the need of a parity check code; the number of check joint units and connection units corresponds to that of connection structures; the variable node unit and a check node unit together complete the band superposing decoding process of the HS-LDPC codes. The method can largely reduce the execution complexity of whole decoder hardware and is easy to compromise between hardware realization complexity and speed according to various applied needs.
Description
Technical field
The invention belongs to communication channel encoding and decoding technique field, particularly relate to a kind of highly structural parity check code coding method and the coding/decoding method and encoder thereof of correcting error of information channel fast and effectively of adopting.
Background technology
Data cause various mistakes through regular meeting in storage and transmission course.The reason that produces this mistake has synchronization loss, the multipath fading in the wireless transmission, the reasons such as magnetic track loss in the magnetic storage in random noise, the demodulating process.Because the existence of these mistakes, the rate of information throughput under the specific broadband and the quality of transmission have been limited greatly.Particularly in wireless multimedia transmission system, because lot of data will and be subjected at limited bandwidth keeping very high reliability in the Channel Transmission of various bursty interference, this problem becomes more outstanding.
In order to solve the integrity problem of data in transmission and storage, adopt the method for chnnel coding usually.In present existing coding method, low density parity check code (LDPC) causes very big attention because of its remarkable performance, and is widely regarded as one of up-and-coming error correction/encoding method in many telecommunications and the magnetic memory applications.The LDPC sign indicating number and the Turbo code of long code piece have similar performance, and one of their main difference is that the decoding of LDPC sign indicating number is easier, is more suitable in parallel processing in essence.This character is added its outstanding error-correcting performance makes it become coded system desirable in the high-speed wideband system applies.In addition, the interleaver that carries among the LDPC has avoided carrying out extra interleaving treatment between channel encoder and modulator.
C.Howland and A.Blanksby two people are at " Parallel decoding architectures forlow density parity check ", in Proc.of 2001IEEE Int.Symp.On Circuits andSystems, Sydney has designed a parallel fully decoder architecture and has reached high decoding speed among the May 2001.Yet along with the increase of LDPC code length, owing to calculate and the too complexity of communicating by letter, its hardware realizes that complexity is high.Therefore, in most practical application, this parallel fully design all is not suitable for, and also is like this even only adopt under the situation of short code (code word size is less than 10000 bits).E.Boutillon, J.Castura, with people such as F.R.Kschischang at " Decoder-first code design ", in Proceedings of the 2ndInternational Symposium on Turbo Codes and Related Topics, pp.459-462, Brest, France, the decoder architecture that has proposed a kind of part parallel among the Sept.2000 also designs has in view of the above realized decoder.But this decoder has comprised in a large number code generator immediately, has caused the complexity increase in actual applications, makes that decoder global design and hardware implementation are further complicated.Recently, Tong Zhang and Keshab K.Parihi " Joint (and 3; k)-Regular LDPC Code and Decoder/Encoder Design ", among the toappear IEEE Transactions on Signal Process a kind of more structurized LDPC decoder has been proposed again, they have proposed a kind of simpler design, do not re-use randomizer (random number generator).But, utilized the very complicated internet of change immediately (shuffle network) in this design, because higher route cost still can cause hardware to carry out (FPGA/ASIC) decreased performance.In addition, these encoding schemes are difficult to satisfy the needed high data transmission rate request of many high-speed applications eventually.
Summary of the invention
The present invention has overcome the deficiencies in the prior art part, and a purpose of the present invention is the coding method and the coding/decoding method of the LDPC sign indicating number (following table is shown the HS-LDPC sign indicating number) that proposed a kind of highly structural.This method has following several big advantage, makes it most suitable in practical application.Do not have the complicated network of change immediately in this method, can greatly reduce the complexity that entire decoder hardware is carried out; Secondly, this method is a highly structural, is easy to trade off between hardware implementation complexity and speed according to the needs of types of applications.In addition, the potential decoding process of in a decoder core, realizing different code checks of this method.Systematized HS-LDPC encoder has lower hardware complexity in this method, can reach the data throughout up to 100Mbits/s.
The LDPC sign indicating number is a kind of linear error correction sign indicating number, and the linear error correction sign indicating number adopts a generator matrix G, the information s={s1 that will send, and s2 ..., sm} converts the code word t={t1 that is output to, t2 ..., tn}, n＞m.Corresponding with generator matrix G is a check matrix H, and H satisfies Ht=0.The LDPC sign indicating number is that code length is the code word of n, and L is 1 the very low matrix of density in its check matrix H.In check matrix H, the number of each row 1 is column weight j, and the number of each row 1 is the heavy k of row, and (j, code check k) are (k-j)/k to the LDPC sign indicating number, and above-mentioned description is a content well known in the prior art usually.
HS-LDPC sign indicating number of the present invention is based on the code Design of the highly structural that on the basis of LDPC sign indicating number check matrix H is carried out, its coding method is: step 1, check matrix generation unit in the encoder is according to code check, the column weight of the HS-LDPC sign indicating number that sets in advance and heavily value generation one parity matrix of going, and the result that will generate imports a composite coding unit; Step 2, described composite coding unit carries out compose operation with the data message and the described parity matrix of input, obtains a data message with parity check code information; Step 3 is with the described data message output that is merged by parity information bit and input data information bit.
The preferred steps that described check matrix generation unit generates parity matrix is as follows:
Wherein, described composite coding unit comprises that a multiplication unit, first resolves the unit, and second resolves a unit and a merge cells.Its concrete composite coding computing is, described multiplication unit carries out multiplying with the data message Xs of an input and the parity matrix information of described check matrix generation unit generation, with its as a result z be input to first and resolve the unit and resolve according to first unit solving equation U y=z (U multiply by y and equals z), wherein y is the solving result of this unit, will resolve information y input second and resolve the unit and resolve; Described second resolves the unit resolves equation L Xp=y according to Unit second, wherein U and L be on/lower triangular matrix, Xp is the data that have parity information, also is the solving result of this unit.At last, merge cells will have the data Xp of parity matrix information and the bit of input information Xs merges, and with its result's output.
Another object of the present invention has provided the coding/decoding method of a kind of HS-LDPC of being used for, its concrete method is as follows: according to the structure of parity matrix, preestablish the variable node unit of encoder, check-node unit and number that is connected the variable node unit and corresponding syndeton, because decoder is in the process of carrying out decoding, the sub matrix in the same column and the work of treatment of submatrix are responsible in each variable node unit, the work of treatment of sub matrix and submatrix in being responsible for going together mutually in each check-node unit, so the variable node unit in the described encoder and the number of check-node unit are to be consistent with the structure of described parity matrix with being connected, described variable node unit heavily is worth according to the row of parity matrix and is provided with, and described check-node unit is provided with according to the column weight value of described parity check square.Described linkage unit is responsible for the interconnected of variable node unit and check-node unit, and it is that structure by parity matrix is determined, promptly is the matrix sequence of non-zero word in each row in the parity matrix.It is to be noted that these connections are also all fixed because fix when the MATRIX CHECK-UP sign indicating number.Wherein said variable node unit comprises a plurality of memory cell again, is used for storing the exchange message between variable node unit and the check-node unit.In decode procedure, what described variable node unit and check-node unit were finished the HS-LDPC sign indicating number jointly repeatedly is with decode procedure, and its processing procedure is according to the Log-BP algorithm, and this algorithm is conventional existing algorithm.
Wherein, described HS-LDPC coding/decoding method can be taked diverse ways according to following situation, when needs provide the situation of higher data transfer rate, can according to the actual needs described variable node unit and described check-node unit be divided, be divided into littler variable node unit and check-node unit, all variable node unit and check-node unit can the parallel processing data in decode procedure, increased the processing unit of more parallel running like this.When needs reduced the situation of complexity of hardware, the mode that described variable node unit and described check-node unit can be shared according to the simple time can and become a processing unit, thereby exchanges the reduction of hardware complexity for speed.According to different needs, can take all factors into consideration above-mentioned situation.
A further object of the present invention provides a kind of HS-LDPC encoder, and wherein said encoder is made up of check matrix generation unit and composite coding unit.A grow as required parity matrix and the result is input to the coding synthesis unit of described check matrix generation unit.Described composite coding unit comprises that a multiplication unit, first resolves unit, second and resolves a unit and a merge cells.The parity matrix information that the data message Xs of one input and described check matrix generation unit generate is input in the described multiplication unit, described multiplication unit carries out multiplying to above-mentioned information, and its result is input to described first resolves the unit, described first resolve the unit according to first resolve equation to the input information settle accounts, it will resolve result of information and import described second and resolve the unit, described second resolve the unit according to its second resolve equation to the input information resolve, this moment, the result that resolves of output was the data with parity check code information, described second resolves the result that will resolve the unit is input to described merge cells, described merge cells merges the bit of the data Xp that will have parity check code information and input information Xs, and with its result's output.
A further object of the present invention provides a kind of HS-LDPC decoder, and wherein said decoder is by a variable node unit, and check-node unit and the linkage unit that connects between changing cell and the verification unit are formed.Wherein said variable node unit comprises a plurality of memory cell again, is used for storing the exchange message between changing cell and the verification unit.Described linkage unit is used for variable node unit and check-node unit interconnected, and it is determined by the parity matrix structure.Described each variable node unit is used for the calculating to same column sub matrix and submatrix, and each verification unit is used for the calculating of colleague's sub matrix and submatrix mutually.The number of wherein said variable node unit is heavy relevant with the row of MATRIX CHECK-UP sign indicating number, and the number of described check-node unit is relevant with the column weight of MATRIX CHECK-UP sign indicating number.
Description of drawings
Fig. 1 is the structure chart of the parity check matrix H in the HS-LDPC coding method of the present invention;
Fig. 2 is that a code check being used for HS-LDPC coding method of the present invention is 1/2 HS-LDPC decoder;
Fig. 3 is that a code check being used for HS-LDPC coding method of the present invention is 5/8 HS-LDPC decoder;
Fig. 4 is the encoder that is used for HS-LDPC coding method of the present invention;
Fig. 5 is the matrix P displacement table of first embodiment of HS-LDPC coding method of the present invention;
Fig. 6 is the matrix S displacement table of first embodiment of HS-LDPC coding method of the present invention;
Fig. 7 is the matrix P displacement table of second embodiment of HS-LDPC coding method of the present invention;
Fig. 8 is the matrix S displacement table of second embodiment of HS-LDPC coding method of the present invention;
Fig. 9 is the table of comparisons of systematic function and simulated effect under the system of HS-LDPC coding method of the present invention and the DVB-T system;
Figure 10 is the error rate (BER) the simulation result figure of HS-LDPC sign indicating number that adopts 1/2 code check of QPSK in the HS-LDPC coding method of the present invention in different channels;
Figure 11 is the error rate BER simulation result figure of HS-LDPC sign indicating number that adopts 3/4 code check of 16QAW in the HS-LDPC coding method of the present invention in different channels;
Figure 12 is the HS-LDPC code check BER simulation result figure that adopts 8/9 code check of 64QAW in the HS-LDPC coding method of the present invention in different channels.
Embodiment
Now embodiments of the invention are described in detail in conjunction with concrete accompanying drawing.Embodiment one is to be that 1/2 long code is carried out HS-LDPC coding method of the present invention and coding/decoding method with encoding rate.
For example to be 9036 HS-LDPC (3 to code check 1/2, code length, 6) sign indicating number is encoded, the encoder of HS-LDPC of the present invention as shown in Figure 4, at first, the check matrix generation unit of described encoder is according to the HS-LDPC (3 that will encode, 6) Ma code length 9036, column weight j is 3, it is generated sub matrix is H
0, H
1, H
2Check matrix H, as shown in Figure 1, according to the heavy k of row of HS-LDPC (3,6) be 6 and its code length be 9036 so code length 9036 can be weighed 6 divided by row, with the H of the sub matrix of described check matrix
0, H
1, H
2Further generate 1506 submatrix A again
0, A
1... A
k, B
0, B
1... B
k, C
0, C
1... C
k, because 1 code length is 1, so the code length of sub matrix can be considered 1506, as shown in Figure 1, divided by the heavy k value 6 of row, and then the number of generation unit matrix I is 251 and then can obtains I by unit matrix at the code length that utilizes sub matrix
(i, j), be the unit matrix of 251X251.Unit matrix P among the H1
(i, j)Be according to corresponding I
(i, j)The unit matrix cyclic shift obtains, and represents the operator of right cyclic shift with T, Tu (i) representative circulate to the right mobile u row, P so
(i, j)=Tu (i).For example,
Here, u is 2.
Equally, H
2In unit matrix S
(i, j)Also be according to corresponding I
(i, j)The random rotation displacement of unit matrix.Provide each P that chooses as Fig. 5
(i, j)Number of shift bits.Fig. 6 has listed S
(i, j)The number of shift bits of choosing according to Performance Evaluation in the overall random number.At last, by obtaining a parity check matrix H after the cyclic shift, it is to have three sub matrixs and a parity matrix of the highly structural that is made of 1506 submatrixs that the unit matrix of 251X251 carries out forming after the cyclic shift.Described check matrix generation unit is with this information input composite coding unit.As shown in Figure 4, the multiplication unit of described composite coding unit carries out multiplying with the data message Xs and the described parity matrix information of an input, with its as a result z be input to first and resolve the unit, first resolves the unit resolves according to first unit solving equation U y=z (U multiply by y and equals z), wherein y is the solving result of this unit, to resolve information y input second and resolve the unit, second resolves the unit according to the second unit solving equation L Xp=y, resolve, wherein U and L be on/lower triangular matrix, Xp is the data that have parity information, also is the solving result of this unit.At last, merge cells will have the data Xp of parity check code information and the bit of input information Xs merges, and with its result's output.
The code check that the present invention as shown in Figure 2 is used for the HS-LDPC coding method is 1/2 HS-LDPC decoder, its structure be connected that the structure that is the parity check matrix H that generates according to above-mentioned check matrix generation unit sets, each variable node unit is to the calculating of sub matrix in the same column and submatrix, and each check-node unit is used for the calculating of colleague's sub matrix and submatrix mutually.So the variable node unit in the described encoder and the number of check-node unit are to be consistent with the structure of described parity matrix with being connected, described variable node unit heavily is worth according to the row of parity matrix and is provided with, and described check-node unit is provided with according to the column weight value of described parity matrix.Described linkage unit is responsible for the interconnected of variable node unit and check-node unit, and it is that structure by parity matrix is determined, promptly is the matrix sequence of non-zero word in each row in the MATRIX CHECK-UP sign indicating number.Here, can obtain described encoder by resulting parity check matrix H and have 36 parallel variable node VNU, the check-node unit CNU of 18 parallel runnings is connected with CNU with VNU with 3 linkage units, as shown in Figure 2.Wherein said variable node unit comprises a plurality of memory cell again, is used for storing the exchange message between variable node unit and the check-node unit.In decode procedure, what described variable node unit and check-node unit were finished the HS-LDPC sign indicating number jointly repeatedly is with decode procedure, and its processing procedure realizes according to the Log-BP algorithm.
Embodiment two is to be that 5/8 long code is carried out HS-LDPC coding method of the present invention and coding/decoding method with encoding rate.It only is that with embodiment one difference the structure of the decoder that check matrix parity check matrix H that generation unit generates in the described encoder is different and relevant with the H structure changes, other Code And Decode process and embodiment one are basic identical, just no longer repeat here.
Described check matrix generation unit according to HS-LDPC sign indicating number (3,8) as can be known its column weight j be 3, can generate sub matrix is H
0, H
1, H
2Parity check matrix H, again according to its row heavy k be 8 because and code length be 9472 thus can with code length 9472 divided by the row weigh 8, generate 1184 described verification sub matrix H
0, H
1, H
2The syndrome matrix A
0, A
1... A
k, B
0, B
1... B
k, C
0, C
1... C
k,,, be 148 divided by the number of the heavy k value of row 8 generation unit matrix I and then can obtain I by unit matrix at the code length that utilizes sub matrix so the code length of sub matrix can be considered 1184 because 1 code length is 1
(i, j), the unit matrix of 148X148.H
1In unit matrix P
(i, j)Be according to corresponding I
(i, j)The unit matrix cyclic shift obtains, and the algorithm here is identical with embodiment one, i.e. P
(i, j)=Tu (i).Unit matrix S among the H2
(i, j)Also be according to corresponding I
(i, j)The random rotation displacement of unit matrix.Provided each P as Fig. 6 and Fig. 7
(i, j)And S
(i, j)Number of shift bits u.At last, by obtaining a parity check matrix H after the cyclic shift, it is to have three sub matrixs and carry out 1148 submatrixs that form after the cyclic shift and a parity matrix of the highly structural that constitutes by the unit matrix of 148X148.Described check matrix generation unit is with this information input synthesis unit.
The code check that the present invention as shown in Figure 3 is used for the HS-LDPC coding method is 5/8 HS-LDPC decoder, its structure be connected that the structure that is the parity check matrix H that generates according to above-mentioned check matrix generation unit sets, each variable node unit is to the calculating of sub matrix in the same column and submatrix, and each check-node unit is used for the calculating of colleague's sub matrix and submatrix mutually.So the variable node unit in the described encoder and the quantity of check-node unit are to be consistent with the structure of described parity matrix with being connected, described variable node unit heavily is worth according to the row of parity matrix and is provided with, and described check-node unit is provided with according to the column weight value of described parity matrix.Described linkage unit is responsible for the interconnected of variable node unit and check-node unit, and it is that structure by parity matrix is determined.Here, described encoder has 32 parallel variable node VNU, and the check-node unit CNU of 12 parallel runnings is connected with CNU with VNU with 3 linkage units.Wherein said variable node unit comprises a plurality of memory cell again, is used for storing the exchange message between variable node unit and the check-node unit.According to the needs of parity check matrix H, realize fixedly connected between VNU and the CNU with three routers in the drawings.In order to reduce hard-wired complexity, the VNU of this decoder and CNU have adopted shared mode of time, and each VNU is responsible for facing mutually the work of treatment of submatrix in two row, and each CNU is responsible for facing mutually the evaluation work of submatrix in two row.The contrast code check be 1/2 LDPC the decoder block diagram as can be seen, the structure of two decoders is closely similar, and this structurized just H matrix is determined.In decode procedure, what described variable node unit and check-node unit were finished the HS-LDPC sign indicating number jointly repeatedly is with decode procedure, and its processing procedure realizes according to the Log-BP algorithm.
The present invention is that example describes HS-LDPC decoding method of the present invention with 1/2 code check and 5/8 code check only, and HS-LDPC coding method of the present invention is not limited only to the foregoing description also can be also to be applicable to different code checks.
Utilize HS-LDPC Code And Decode method involved in the present invention to make data when transmission, when particularly data-signal transmits on different logic channels, can adopt modulation/coding configuration flexibly, can grasp as required and flexibly on digit rate transmission rate and hardware complexity, this gives needs the bigger multi-medium data transmission in broadband to bring bigger facility.The effect of HS-LDPC Code And Decode of the present invention with and performance in whole system also have obvious superiority, as shown in Figure 9, the table of comparisons of systematic function and simulated effect under employing HS-LDPC coding method and DVB-T system, wherein under same code rate, at low data rate, under the situation of middle data transfer rate and High Data Rate, adopt the data transfer rate that transmits in the DVB-T system all to be lower than the data transfer rate that adopts the HS-LDPC system, and adopt the threshold value in the DVB-T system all to be higher than the needed threshold value of HS-LDPC system, that is to say that the needed hardware complexity of HS-LDPC system significantly is lower than the needed hardware complexity of DVB-T system.That Figure 10 is extremely shown in Figure 12 is the error rate under the different amplitude modulation is adopted in coding method of the present invention in different channels simulated effect figure, and it illustrates that clearly coding method of the present invention has superior error-correcting performance.
Those of ordinary skills can carry out multiple different modification to the present invention in spirit of the present invention and viewpoint.All equal variation and modifications of being done according to claims scope of the present invention are all the scope that the present invention protects.
Claims (19)
1. the coding method of the LDPC of a highly structural, it comprises the steps:
Step 1, the check matrix generation unit by an encoder is according to heavy value generation one parity matrix of code check, column weight and the row of the LDPC sign indicating number of the highly structural that sets in advance, and the result that will generate imports a composite coding unit of an encoder;
Step 2, described composite coding unit carries out compose operation with the data message and the described parity matrix of input, obtains a data message with parity matrix information;
Step 3 is with the described data message output that is merged by parity information bit and input data information bit.
2. the coding method of the LDPC of highly structural as claimed in claim 1, the step that wherein said check matrix generation unit generates parity matrix is:
Step 1, the check matrix generation unit is 3 according to the column weight assessment of the LDPC sign indicating number of highly structural, generates the check matrix with three verification sub matrixs;
Step 2, heavy according to the row in the LDPC sign indicating number of the code length of the LDPC sign indicating number of highly structural and highly structural, described verification sub matrix is generated some block check submatrixs;
Step 3 heavily is worth divided by the row in the LDPC sign indicating number of described highly structural according to the code length of described syndrome matrix and obtains a verification unit matrix;
Step 4, described verification unit matrix carried out cyclic shift in all verification sub matrixs after, obtain a parity matrix;
Step 5 is input to a resulting parity matrix information composite coding unit of encoder.
3. the coding method of the LDPC of highly structural as claimed in claim 1 or 2, wherein, the column weight j of described parity matrix is fixed as 3, and the heavy k of row changes according to different code checks.
4. the coding method of the LDPC of highly structural as claimed in claim 3, wherein said parity matrix is by three verification sub matrix H
0, H
1, H
2Constitute.
5. the coding method of the LDPC of highly structural as claimed in claim 4, wherein, described verification sub matrix H0 is by unit matrix I
(i, j)Cyclic shift constitutes, and described sub matrix H1 is by unit matrix P
(i, j)Cyclic shift constitutes, and described sub matrix H2 is by unit matrix S
(i, j)Cyclic shift constitutes.
6. the coding method of the LDPC of highly structural as claimed in claim 5, wherein, described cyclic shift is the displacement P that carries out according to following formula
(i, j)=Tu (i), T represents the operator of right cyclic shift, Tu (i) represents the mobile u row that circulate to the right.
7. the coding method of the LDPC of highly structural as claimed in claim 5, wherein, described cyclic shift is the displacement S that carries out according to following formula
(i, j)=Tu (i), T represents the operator of right cyclic shift, Tu (i) represents the mobile u row that circulate to the right.
8. the coding method of the LDPC of highly structural as claimed in claim 1, wherein, the composite coding algorithm of described composite coding unit is,
Step 1, a multiplication unit carries out multiplying with the data message and the described parity matrix information of described input, with its as a result z be input to first and resolve the unit and resolve;
Step 2, described first resolves unit, base area, unit resolves equation Uy=z, and wherein y is the solving result of this unit, will resolve information y input second and resolve the unit and resolve;
Step 3, described second resolves the unit resolves equation L Xp=y according to Unit second, wherein U and L be on/lower triangular matrix, Xp is the data that have parity information, also is that the solving result of this unit is imported a merge cells;
Step 4, described merge cells will have the data Xp of parity matrix information and the bit of input information Xs merges, and with its result's output.
9. the LDPC encoder of a highly structural, wherein, described encoder is made up of a check matrix generation unit and a composite coding unit, wherein,
Described check matrix generation unit is according to the code check of the HS-LDPC sign indicating number that sets in advance, and column weight and row heavily value generate a parity matrix, and the result that will generate imports described composite coding unit;
It is used for described composite coding unit the data message and the described parity matrix of input are carried out compose operation, obtain a data message with parity matrix information, and the data message of described parity information bit and the merging of input data information bit is exported.
10. the LDPC encoder of highly structural as claimed in claim 9, wherein said composite coding unit resolves the unit by a multiplication unit, first, second resolves unit and merge cells composition, and the information bit Xs that described multiplication unit is used for importing carries out multiplying and obtains signal z and the unit is resolved in this signal input first;
Described first resolves the unit is used for resolving equation according to first and resolves, and will resolve and obtain one and resolve information y input second and resolve the unit;
Described second resolves the unit is used for resolving equation according to second and will resolves once more from the first information y that resolve unit output, obtains having the data of parity information and these data Xp being input to merge cells;
Described merge cells is used for merging having the data Xp of parity check code information and the bit of input information Xs, and with its result's output.
11. the LDPC coding/decoding method of a highly structural, it comprises the steps:
Step 1 according to the structure of parity matrix, preestablishes the variable node unit of encoder, the number of check-node unit and linkage unit and corresponding syndeton;
Step 2, in the process of carrying out decoding, the sub matrix in the same column of parity matrix and the work of treatment of submatrix are responsible in each variable node unit, the work of treatment of sub matrix and submatrix among the colleague mutually of parity matrix is responsible in each check-node unit, described linkage unit is responsible for the interconnected of variable node unit and check-node unit, wherein said variable node unit comprises a plurality of memory cell again, is used for storing the exchange message between variable node unit and the check-node unit;
Step 3, described variable node unit and check-node unit are finished the iterative decoding process of HS-LDPC sign indicating number jointly.
12. the LDPC coding/decoding method of highly structural as claimed in claim 11, variable node unit in the wherein said encoder and the quantity of check-node unit are to be consistent with the structure of described MATRIX CHECK-UP sign indicating number with being connected, described variable node unit heavily is worth according to the row of parity matrix check code and is provided with, described check-node unit is provided with according to the column weight value of described parity matrix verification, and described linkage unit is determined by the matrix sequence of non-zero word in each row in the MATRIX CHECK-UP sign indicating number of parity matrix.
13. as the LDPC coding/decoding method of claim 11 or 12 described highly structurals, wherein said linkage unit is different for different check matrixes.
14. as the LDPC coding/decoding method of claim 11 or 12 described highly structurals, wherein said linkage unit is a router.
15. as the LDPC coding/decoding method of claim 11 or 12 described highly structurals, wherein said iterative decoding algorithm is to adopt the Log-BP algorithm.
16. LDPC coding/decoding method as claim 11 or 12 described highly structurals, wherein when the situation of higher data transfer rate need be provided, can according to the actual needs described variable node unit and described check-node unit be divided, be divided into littler variable node unit and check-node unit, variable node unit and check-node unit all in decode procedure can the parallel processing data.
17. LDPC coding/decoding method as claim 11 or 12 described highly structurals, wherein when the situation of the complexity that need to reduce hardware, the mode that described variable node unit and described check-node unit can be shared according to the simple time be merged into a processing unit.
18. LDPC coding/decoding method as claim 11 or 12 described highly structurals, wherein can be according to actual conditions, take variable node unit that described variable node unit and described check-node dividing elements is littler and check-node unit and the mode that described variable node unit and described check-node unit were shared according to the simple time is merged into the mode that a processing unit combines.
19. the LDPC decoder of a highly structural, described decoder are by a variable node unit, check-node unit and the linkage unit that connects between changing cell and the verification unit are formed;
Wherein said each variable node unit is used for the same column sub matrix of parity matrix and the calculating of submatrix, the number of variable node unit is according to heavy setting of row of MATRIX CHECK-UP sign indicating number, and it is connected with described check-node unit by described linkage unit;
Wherein said each check-node unit is used for the colleague's sub matrix mutually of parity matrix and the calculating of submatrix, the number of check-node unit is provided with according to the column weight of its number MATRIX CHECK-UP sign indicating number, and it is connected with described changing cell by described linkage unit;
Wherein said variable node unit comprises a plurality of memory cell again, is used for storing the exchange message between changing cell and the verification unit;
Described linkage unit is used for variable node unit and check-node unit interconnected, and it is that structure by the MATRIX CHECK-UP sign indicating number is determined.
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| CN100425017C (en) * | 2005-12-08 | 2008-10-08 | 西安电子科技大学 | Encoder and Fast Encoding Method of Parallel Convolutional LDPC Codes Based on Precoding |
| CN100544212C (en) * | 2006-01-23 | 2009-09-23 | 南京大学 | High-speed LDPC decoder with reduced memory requirements |
| CN101034892B (en) * | 2006-03-06 | 2011-11-23 | 西门子（中国）有限公司 | LDPC code generation method and device using the LDPC code |
| CN100499378C (en) * | 2006-05-26 | 2009-06-10 | 清华大学 | Low-density odd-parity check-code decoding method adopting uniform quantizing variable range |
| CN101340262B (en) * | 2006-06-14 | 2012-05-30 | 北京新岸线移动通信技术有限公司 | Implementing method and device for low-density parity check code |
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| CN102868483A (en) * | 2011-07-06 | 2013-01-09 | 北京新岸线无线技术有限公司 | Method and device for data transmission |
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