CN100442507C - Symmetrical inductance element - Google Patents
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Abstract
Description
技术领域 technical field
本发明有关于一种半导体装置,特别是有关于一种差动型操作(differential operation)的对称电感元件。The present invention relates to a semiconductor device, and more particularly to a symmetrical inductive element with differential operation.
背景技术 Background technique
许多数字及模拟部件及电路已成功地运用于半导体集成电路。上述部件包含了被动元件,例如电阻、电容或电感等。典型的半导体集成电路包含一硅基底。一层以上的介电层设置于基底上,且一层以上的金属层设置于介电层中。这些金属层可通过现行的半导体制程技术而形成芯片内建部件,例如芯片内建电感元件(on-chip inductor)。Many digital and analog components and circuits have been successfully used in semiconductor integrated circuits. The above components include passive components such as resistors, capacitors or inductors. A typical semiconductor integrated circuit includes a silicon substrate. More than one dielectric layer is disposed on the base, and more than one metal layer is disposed in the dielectric layer. These metal layers can be used to form on-chip components, such as on-chip inductors, through current semiconductor process technology.
传统上,芯片内建电感形成于基底上且运用于射频频带(radio frequency band)集成电路设计。请参照图1,其中图1绘示出一已知具有平面螺旋结构的芯片内建电感元件平面示意图。芯片内建电感元件形成于一基底100上方的绝缘层104中,其包括一螺旋金属层103及一内连线结构。螺旋金属层103嵌入于绝缘层104中。内连线结构包括嵌入下层绝缘层(未绘示)中的导电插塞105及109及金属层107与嵌入于绝缘层104中的金属层111。螺旋金属层103通过导电插塞105及109及金属层107及111而形成一电流路径,以与芯片外部或内部电路电性连接。Traditionally, on-chip inductors are formed on a substrate and used in radio frequency band IC designs. Please refer to FIG. 1 , wherein FIG. 1 shows a schematic plan view of a known on-chip inductor with a planar spiral structure. The on-chip inductor is formed in an
平面型螺旋电感元件的优点在于可通过减少位于芯片外建的电路元件数量及其所需的复杂内连线而增加电路的集成度。再者,平面型螺旋电感可避免芯片内建电路与芯片外建(off-chip)电路之间接合垫(bond pad)或接线(bond wire)所产生的寄生效应。The advantage of the planar spiral inductor is that it can increase the integration level of the circuit by reducing the number of circuit components built outside the chip and the required complex interconnection. Furthermore, the planar spiral inductor can avoid the parasitic effect produced by the bond pad or the bond wire between the on-chip circuit and the off-chip circuit.
上述平面型螺旋电感的品质因数(quality factor/Q value)低且面积大。为了进一步改善电感的Q值并减少面积,有人提出增加螺旋金属层103的厚度及缩小螺旋金属层103的内圈与外圈之间的线距(trace space)S。The aforementioned planar spiral inductor has a low quality factor (Q value) and a large area. In order to further improve the Q value of the inductor and reduce the area, it is proposed to increase the thickness of the
然而,越来越多的无线通讯设计使用差动电路以降低共模(common mode)噪声,而运用于上述差动电路的电感需为对称式来防止共模噪声产生。亦即,电感从任一端点观看皆具有相同结构。图1中的平面型螺旋电感并非为对称式,若应用于差动电路则无法有效隔绝噪声。However, more and more wireless communication designs use differential circuits to reduce common mode noise, and the inductors used in the above differential circuits need to be symmetrical to prevent common mode noise. That is, the inductor has the same structure viewed from any end point. The planar spiral inductor in Figure 1 is not symmetrical, and it cannot effectively isolate noise if it is applied to a differential circuit.
发明内容 Contents of the invention
有鉴于此,本发明提供一种对称电感元件,以防止共模噪声产生。同时,通过改变电感中线圈(coil)的线距,以增加电感元件可用的频率范围。In view of this, the present invention provides a symmetrical inductance element to prevent generation of common mode noise. At the same time, the available frequency range of the inductance element is increased by changing the pitch of the coil in the inductor.
根据上述的目的,本发明提供一种对称电感元件,包括:绝缘层、第一绕线部及第二绕线部及耦接部。绝缘层设置于基底上。第一绕线部及第二绕线部相互对称设置于绝缘层内。每一绕线部包括由内而外同心排列的第一半圈形导线层、第二半圈形导线层及第三半圈形导线层。每一个半圈形导线层具有第一端及第二端,其中第一半圈形导线层的第一端相互耦接。耦接部设置于第一绕线部与第二绕线部之间的绝缘层内,包括:第一对连接层及第二对连接层。第一对连接层交错连接两绕线部的第二半圈形导线层及第三半圈形导线层的第一端。第二对连接层交错连接两绕线部的第一半圈形导线层及第二半圈形导线层的第二端。每一个绕线部中相邻的半圈形导线层之间具有线距,且位于外侧的线距大于位于内侧的线距。According to the above objective, the present invention provides a symmetrical inductance element, comprising: an insulating layer, a first winding portion, a second winding portion, and a coupling portion. The insulating layer is disposed on the base. The first winding part and the second winding part are symmetrically arranged in the insulating layer. Each winding part includes a first semi-circular wire layer, a second semi-circular wire layer and a third semi-circular wire layer concentrically arranged from inside to outside. Each semi-circular wire layer has a first end and a second end, wherein the first ends of the first semi-circular wire layers are coupled to each other. The coupling part is disposed in the insulating layer between the first winding part and the second winding part, and includes: a first pair of connecting layers and a second pair of connecting layers. The first pair of connection layers are alternately connected to the first ends of the second semi-circular conductor layer and the third semi-circular conductor layer of the two winding parts. The second pair of connecting layers is alternately connected to the second ends of the first semi-circular conductor layer and the second semi-circular conductor layer of the two winding parts. There is a line distance between adjacent half-circle wire layers in each winding part, and the line distance on the outer side is larger than the line space on the inner side.
根据上述的目的,本发明提供一种对称电感元件,包括绝缘层、多个半圈形导线层、至少一个第一对连接层及至少一个第二对连接层,而其中相邻的二个该半圈形导线层之间具有线距,且位于外侧的线距大于位于内侧的线距。此外,多个半圈形导线层由内而外同心排列于该绝缘层内,且每一个半圈形导线层具有第一端及第二端,其中位于最内侧的二个半圈形导线层的所述第一端相互耦接。第一对连接层连接所述多个半圈形导线层的所述第一端,以及第二对连接层,连接所述多个半圈形导线层的所述第二端。According to the above purpose, the present invention provides a symmetrical inductive element, which includes an insulating layer, a plurality of semi-circular wire layers, at least one first pair of connection layers and at least one second pair of connection layers, and the two adjacent There is a line distance between the semi-circular wire layers, and the line space on the outer side is larger than the line space on the inner side. In addition, a plurality of semi-circular conductor layers are concentrically arranged in the insulating layer from inside to outside, and each semi-circular conductor layer has a first end and a second end, wherein the two semi-circular conductor layers located at the innermost The first ends are coupled to each other. A first pair of connection layers connects the first ends of the plurality of semi-circular wire layers, and a second pair of connection layers connects the second ends of the plurality of semi-circular wire layers.
根据上述的目的,本发明提供一种对称电感元件,包括绝缘层、第一绕线部、第二绕线部及二个半圈形导线层,其中第一绕线部是置于绝缘层内,具有多个导线层,而第二绕线部是置于绝缘层内,且对称于该第一绕线部,并具有多个导线层。此外,该二个半圈形导线层和与其相邻的绕线部之间具有线距,且此线距大于位于该绕线部内相邻的二个该导线层之间的线距。该二个半圈形导线层是置于绝缘层内,并分别位于该第一绕线部及该第二绕线部的外侧,分别电性连接于该第一绕线部及该第二绕线部。According to the above purpose, the present invention provides a symmetrical inductance element, including an insulating layer, a first winding part, a second winding part and two semi-circular wire layers, wherein the first winding part is placed in the insulating layer , has a plurality of wire layers, and the second winding part is placed in the insulating layer, and is symmetrical to the first winding part, and has a plurality of wire layers. In addition, there is a wire distance between the two semi-circular wire layers and the adjacent winding portion, and the wire distance is greater than the wire distance between the two adjacent wire layers in the winding portion. The two semi-circular wire layers are placed in the insulating layer, and are respectively located outside the first winding part and the second winding part, and are electrically connected to the first winding part and the second winding part respectively. line department.
本发明所提供的对称电感元件,于差动信号操作时,可降低寄生电容效应,增加电感元件可用的频率范围。The symmetrical inductance element provided by the present invention can reduce the parasitic capacitance effect and increase the usable frequency range of the inductance element when the differential signal is operated.
附图说明 Description of drawings
图1是绘示出已知具有平面螺旋结构的芯片内建电感元件平面示意图。FIG. 1 is a schematic plan view of a known on-chip inductor with a planar spiral structure.
图2是绘示出一根据本发明实施例的三匝对称电感元件平面示意图。FIG. 2 is a schematic plan view illustrating a three-turn symmetrical inductor element according to an embodiment of the present invention.
图3是绘示出一根据本发明实施例的四匝对称电感元件平面示意图。FIG. 3 is a schematic plan view illustrating a four-turn symmetrical inductor element according to an embodiment of the present invention.
图4是绘示出一根据本发明实施例的四匝对称电感元件平面示意图。FIG. 4 is a schematic plan view illustrating a four-turn symmetrical inductor element according to an embodiment of the present invention.
图5是绘示出一根据本发明实施例的四匝对称电感元件平面示意图。FIG. 5 is a schematic plan view illustrating a four-turn symmetrical inductor element according to an embodiment of the present invention.
具体实施方式 Detailed ways
以下配合图2说明本发明实施例的三匝对称电感元件的平面示意图。对称电感元件包括:一绝缘层210、第一绕线部及第二绕线部以及一耦接部。绝缘层210设置于一基底200上。基底200包括一硅基底或其他已知的半导体基底。基底200中可包含各种不同的元件,例如晶体管、电阻及其他常用的半导体元件。再者,基底200亦可包含其他导电层(例如,铜、铝或其合金)以及绝缘层(例如,氧化硅层、氮化硅层或低介电材料层)。此处为了简化图式,仅以一平整基底来表示。另外,绝缘层210可为一单层低介电材料层或是多层介电结构。在本实施例中,绝缘层210可包括氧化硅层、氮化硅层或低介电材料层。A schematic plan view of a three-turn symmetrical inductance element according to an embodiment of the present invention will be described below with reference to FIG. 2 . The symmetrical inductance element includes: an
第一绕线部设置于绝缘层210内,且位于虚线2的一第一侧。第一绕线部包括由内而外同心排列的第一半圈形导线层201、第二半圈形导线层203及第三半圈形导线层205。第二绕线部设置于绝缘层210内,且位于虚线2的一相对于第一侧的第二侧。第二绕线部包括由内而外同心排列的第一半圈形导线层202、第二半圈形导线层204及第三半圈形导线层206。第二绕线部以虚线2为对称轴而对称于第一绕线部。The first winding portion is disposed in the
第一绕线部及第二绕线部可构成大体为圆形、矩形、六边形、八边形或多边形的外形。此处,为简化图式,是以八边形作为范例说明。再者,第一绕线部及第二绕线部的材质可由铜、铝或其合金所构成。在本实施例中,第一绕线部的第一半圈形导线层201、第二半圈形导线层203及第三半圈形导线层205与第二绕线部的第一半圈形导线层202、第二半圈形导线层204及第三半圈形导线层206可具有相同的线宽W。The first wire winding part and the second wire winding part can form a substantially circular, rectangular, hexagonal, octagonal or polygonal shape. Here, to simplify the diagram, an octagon is used as an example for illustration. Furthermore, the material of the first winding part and the second winding part can be made of copper, aluminum or alloys thereof. In this embodiment, the first
每一半圈形导线层具有一第一端10及一第二端20。在本实施例中,第一绕线部的第一半圈形导线层201的第一端10与第二绕线部的第一半圈形导线层202的第一端10相互耦接。再者,第一绕线部及第二绕线部的第三半圈形导线层205及206的第二端20具有一侧向延伸部30及40,用以作为信号输入/输出端,用以输入差动信号。Each semicircular wire layer has a
在本实施例中,为了维持电感元件几何对称性(geometricsymmetry),将耦接部设置于第一绕线部与第二绕线部之间的绝缘层210内,其包括第一对连接层及第二对连接层。第一对连接层交错连接两绕线部的第二半圈形导线层203及204与第三半圈形导线层205及206的第一端10。再者,第二对连接层交错连接两绕线部的第一半圈形导线层201及202与第二半圈形导线层203及204的第二端20。举例而言,第一对连接层包括一上跨接层215耦接第二半圈形导线层203及第三半圈形导线层206的第一端10,以及一下跨接层217耦接第二半圈形导线层204及第三半圈形导线层205的第一端10。第二对连接层包括一上跨接层213耦接第一半圈形导线层201及第二半圈形导线层204的第二端20,以及一下跨接层211耦接第一半圈形导线层202及第二半圈形导线层203的第二端20。In this embodiment, in order to maintain the geometric symmetry of the inductance element, the coupling part is disposed in the insulating
一般而言,由于单端信号操作(single-ended signaloperation)的电感元件中相邻的金属绕线层(winding)会通过相同相位的信号,故不用考虑相邻的金属绕线层之间的寄生电容效应(parasitic capacitance effect)。因此,金属绕线层之间的线距必须尽可能的缩小,以提高电感元件的效能。然而,不同于单端信号操作的电感元件,差动信号操作的电感元件中相邻的绕线层会通过具有180度相差的信号,因此需考虑相邻的金属绕线层之间的寄生电容效应,特别是位于最外侧的金属绕线层之间所产生的寄生电容效应。当最外侧的金属绕线层之间的寄生电容增加时,峰值品质因素频率(peak Q-factor frequency)会下降并增加电感偏差(inductance value deviation),因而限制了电感元件可用的频率范围。Generally speaking, since the adjacent metal winding layers (winding) in the single-ended signal operation (single-ended signal operation) inductance element will pass the signal of the same phase, there is no need to consider the parasitic between adjacent metal winding layers. Capacitive effect (parasitic capacitance effect). Therefore, the wire spacing between the metal winding layers must be reduced as much as possible to improve the performance of the inductance element. However, unlike inductive elements operated with single-ended signals, adjacent winding layers in an inductive element operated with differential signals will pass signals with a phase difference of 180 degrees, so the parasitic capacitance between adjacent metal winding layers needs to be considered Effect, especially the parasitic capacitance effect generated between the outermost metal winding layers. When the parasitic capacitance between the outermost metal winding layers increases, the peak Q-factor frequency (peak Q-factor frequency) will drop and increase the inductance value deviation (inductance value deviation), thereby limiting the usable frequency range of the inductive component.
因此,在本实施例的对称电感元件中,每一绕线部中相邻的半圈形导线层之间具有一线距,且至少一相对外侧的线距大于至少一相对内侧的线距。举例而言,第二半圈形导线层203及204与第三半圈形导线层205及206之间的线距S2大于第二半圈形导线层203及204与第一半圈形导线层201及202之间的线距S1(即,S2>S1)。如此一来,根据本发明的对称电感元件,由于最外侧的线距S2增加,使得对称电感元件于差动信号操作时,可降低寄生电容效应,而增加电感元件可用的频率范围。Therefore, in the symmetrical inductive element of this embodiment, there is a pitch between adjacent semi-circular wire layers in each winding portion, and at least one relatively outer pitch is greater than at least one relatively inner pitch. For example, the line distance S2 between the second semicircular conductor layers 203 and 204 and the third semicircular conductor layers 205 and 206 is greater than that between the second semicircular conductor layers 203 and 204 and the first semicircular conductor layer The line distance S1 between 201 and 202 (ie, S2>S1). In this way, according to the symmetrical inductive element of the present invention, since the outermost line spacing S2 is increased, the parasitic capacitance effect can be reduced when the symmetrical inductive element operates with differential signals, and the usable frequency range of the inductive element can be increased.
以下配合图3说明本发明其他实施例的四匝对称电感元件,其中相同于图2中的部件是使用相同的标号并省略其说明。在图3中,第一绕线部及第二绕线部更包括第四半圈形导线层207及208,其分别位于第三半圈形导线层205及206的外侧。同样地,第四半圈形导线层207及208可具有相同的线宽W。再者,耦接部更包括一第三对连接层,交错连接两绕线部的第三半圈形导线层205及206及第四半圈形导线层207及208的第二端20。举例而言,第三对连接层包括一上跨接层219耦接第三半圈形导线层205及第四半圈形导线层208的第二端20,以及一下跨接层221耦接第三半圈形导线层206及第四半圈形导线层207的第二端20。再者,第一绕线部及第二绕线部的第四半圈形导线层207及208的第一端10具有一侧向延伸部30及40,用以作为信号输入/输出端,用以输入差动信号。The four-turn symmetrical inductance element of other embodiments of the present invention will be described below with reference to FIG. 3 , wherein the components that are the same as those in FIG. 2 use the same reference numerals and their descriptions are omitted. In FIG. 3 , the first winding part and the second winding part further include fourth semi-circular wire layers 207 and 208 , which are respectively located outside the third semi-circular
在本实施例中,由内而外的线距逐渐增加。举例而言,第三半圈形导线层205及206与第四半圈形导线层207及208之间的线距S3大于第二半圈形导线层203及204与第三半圈形导线层205及206之间的线距S2。再者,第二半圈形导线层203及204与第三半圈形导线层205及206之间的线距S2大于第二半圈形导线层203及204与第一半圈形导线层201及202之间的线距S1(即,S3>S2>S1)。In this embodiment, the line spacing gradually increases from the inside to the outside. For example, the distance S3 between the third semicircular conductor layers 205 and 206 and the fourth semicircular conductor layers 207 and 208 is greater than that between the second semicircular conductor layers 203 and 204 and the third semicircular conductor layer Line distance S2 between 205 and 206 . Furthermore, the line spacing S2 between the second semicircular conductor layers 203 and 204 and the third semicircular conductor layers 205 and 206 is larger than the second semicircular conductor layers 203 and 204 and the first
在其他实施例中,线距S3可大体相同于线距S2且大于线距S1(即,S3=S2>S1),如图4所示。又,在其他实施例中,线距S2可大体相同于线距S1且小于线距S3(即,S3>S2=S1),如图5所示。如此一来,由于最外侧相邻的绕线层具有最大的线距,使得对称电感元件于差动信号操作时,可降低寄生电容效应,而增加电感元件可用的频率范围。另外,本领域技术人员可轻易了解到本发明运用于其他四匝以上的对称电感元件中亦具有相同的优点。In other embodiments, the line distance S3 may be substantially the same as the line distance S2 and larger than the line distance S1 (ie, S3 = S2 > S1 ), as shown in FIG. 4 . Also, in other embodiments, the line distance S2 may be substantially the same as the line distance S1 and smaller than the line distance S3 (ie, S3>S2=S1), as shown in FIG. 5 . In this way, since the outermost adjacent winding layer has the largest pitch, the symmetrical inductance element can reduce the parasitic capacitance effect and increase the usable frequency range of the inductance element when the differential signal operation is performed. In addition, those skilled in the art can easily understand that the present invention also has the same advantages when applied to other symmetrical inductance elements with more than four turns.
以上所述仅为本发明较佳实施例,然其并非用以限定本发明的范围,任何熟悉本项技术的人员,在不脱离本发明的精神和范围内,可在此基础上做进一步的改进和变化,因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。The above description is only a preferred embodiment of the present invention, but it is not intended to limit the scope of the present invention. Any person familiar with this technology can make further improvements on this basis without departing from the spirit and scope of the present invention. Improvements and changes, so the protection scope of the present invention should be defined by the claims of the present application.
附图中符号的简单说明如下:A brief description of the symbols in the drawings is as follows:
100:基底100: base
103:螺旋金属层103: Spiral metal layer
104:绝缘层104: insulation layer
105、109:导电插塞105, 109: Conductive plug
107、111:金属层107, 111: metal layer
S:线距S: line spacing
2:虚线2: dotted line
10:第一端10: First end
20:第二端20: Second End
30、40:侧向延伸部30, 40: Lateral extension
200:基底200: base
201、202:第一半圈形导线层201, 202: the first semi-circular wire layer
203、204:第二半圈形导线层203, 204: the second semi-circular wire layer
205、206:第三半圈形导线层205, 206: the third semi-circular wire layer
207、208:第四半圈形导线层207, 208: the fourth semi-circular wire layer
210:绝缘层210: insulating layer
211、217、221:下跨接层211, 217, 221: lower bridging layer
213、215、219:上跨接层213, 215, 219: upper bridging layer
S1、S2、S3:线距S1, S2, S3: line spacing
W:线宽W: line width
Claims (10)
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| CN101145435B (en) * | 2007-08-23 | 2010-08-25 | 威盛电子股份有限公司 | Inductive structure |
| CN100565875C (en) * | 2007-10-26 | 2009-12-02 | 威盛电子股份有限公司 | Symmetrical inductance element |
| US20150340148A1 (en) * | 2014-05-23 | 2015-11-26 | Infineon Technologies Ag | Inductor and method of forming an inductor |
| CN106876379B (en) * | 2016-07-07 | 2019-10-08 | 威盛电子股份有限公司 | Semiconductor device with a plurality of semiconductor chips |
| CN112838859A (en) * | 2019-11-22 | 2021-05-25 | 瑞昱半导体股份有限公司 | Inductor Capacitor Oscillator and Common Mode Resonant Cavity |
| CN111462979B (en) * | 2020-04-01 | 2024-10-29 | 博流智能科技(南京)有限公司 | Inductance winding method for improving self-resonant frequency and inductance |
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| CN1606127A (en) * | 2004-10-28 | 2005-04-13 | 复旦大学 | Method for designing low parasitic capacity differential driving symmetrical inductance through standard integrated circuit process |
| CN1723513A (en) * | 2002-12-13 | 2006-01-18 | 皇家飞利浦电子股份有限公司 | Planar inductive element and integrated circuit comprising planar inductive element |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1723513A (en) * | 2002-12-13 | 2006-01-18 | 皇家飞利浦电子股份有限公司 | Planar inductive element and integrated circuit comprising planar inductive element |
| CN1606127A (en) * | 2004-10-28 | 2005-04-13 | 复旦大学 | Method for designing low parasitic capacity differential driving symmetrical inductance through standard integrated circuit process |
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