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CN100454553C - Thin film semiconductor device and method of manufacturing the same, electro-optical device, and electronic apparatus - Google Patents

Thin film semiconductor device and method of manufacturing the same, electro-optical device, and electronic apparatus Download PDF

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CN100454553C
CN100454553C CNB2005100860668A CN200510086066A CN100454553C CN 100454553 C CN100454553 C CN 100454553C CN B2005100860668 A CNB2005100860668 A CN B2005100860668A CN 200510086066 A CN200510086066 A CN 200510086066A CN 100454553 C CN100454553 C CN 100454553C
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CN1725500A (en
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江口司
松本友孝
藤田伸
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Seiko Epson Corp
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Abstract

在具备基体及形成于该基体上的半导体膜的薄膜半导体装置中,在所述基体上设有内部电路(主电路部)(17),保护电路部(18)、端子部(19)。在所述保护电路部(18)上,设有保护电路元件(181,182),其具有所述半导体膜的PIN二极管,以及介于该PIN二极管的I层和绝缘膜对向配置的浮置电极。能够提供一种可构成可对内部电路良好保护免受浪涌电压影响的保护电路,对于因过大电压而被破坏时电路结构不产生故障,且具有优良的可靠性的电路元件的薄膜半导体装置。

Figure 200510086066

In a thin film semiconductor device including a base and a semiconductor film formed on the base, an internal circuit (main circuit portion) (17), a protection circuit portion (18), and a terminal portion (19) are provided on the base. On the protection circuit part (18), there are protection circuit elements (181, 182), which have a PIN diode of the semiconductor film, and a floating diode arranged oppositely between the I layer and the insulating film of the PIN diode. electrode. It is possible to provide a thin-film semiconductor device capable of constituting a protection circuit that can well protect internal circuits from surge voltages, and that does not cause failure in the circuit structure when it is destroyed by excessive voltage, and that has excellent reliability as a circuit element .

Figure 200510086066

Description

薄膜半导体装置及其制造方法、电光学装置、电子机器 Thin film semiconductor device and manufacturing method thereof, electro-optical device, electronic device

技术领域 technical field

本发明涉及薄膜半导体装置及其制造方法、电光学装置、电子机器。The present invention relates to a thin film semiconductor device, a manufacturing method thereof, an electro-optical device, and an electronic device.

背景技术 Background technique

以往,在半导体集成电路装置和有源矩阵方式的电光学装置中,设有用于保护内部电路免受静电的保护电路。例如,在电光学装置中,在像素开关元件和驱动电路等内部电路与取出电极用的焊盘之间设有保护电路。半导体集成电路装置中使用作为保护电路的二极管,电光学装置使用连接有二极管的薄膜晶体管(TFT)。其理由为,在电光学装置中形成使用形成于绝缘板上的薄膜半导体层的TFT,以及在薄膜半导体层上形成二极管的PN结,是困难的(例如,参照专利文献1。)。Conventionally, semiconductor integrated circuit devices and active matrix electro-optical devices are provided with protection circuits for protecting internal circuits from static electricity. For example, in an electro-optical device, a protection circuit is provided between internal circuits such as a pixel switching element and a drive circuit, and pads for extraction electrodes. A diode is used as a protection circuit in a semiconductor integrated circuit device, and a thin film transistor (TFT) connected to a diode is used in an electro-optical device. The reason is that it is difficult to form a TFT using a thin film semiconductor layer formed on an insulating plate and a PN junction of a diode on the thin film semiconductor layer in an electro-optical device (for example, refer to Patent Document 1).

专利文献:特开平6-51346号公报。Patent document: Japanese Patent Application Laid-Open No. 6-51346.

图9(a)是表示利用二极管连接TFT的保护电路的电路结构图,(b)是同一二极管连接TFT的概略剖视图。如图9(a)所示,连接焊盘219和内部电路217之间插入2个电阻元件R1、R2,并且在这些电阻元件R1和R2的中间,与连接焊盘219b(Vdd)和219c(Vss)连接的线路中,分别插入一个二极管连接TFT30D。参见图9(b)所示的剖面结构,二极管连接TFT30D包括:形成于基板211上的半导体膜201,和该半导体膜201介于栅极绝缘膜212相对的栅极电极213a、通过贯通设置于绝缘膜212和216的连接孔的内部和半导体膜201连接的源极电极208,以及漏极电极209。因此,使通过贯通设置于绝缘膜216的连接孔与栅极213a连接的连接电极213d和漏极电极209之间短路,构成二极管连接结构的TFT。9( a ) is a circuit configuration diagram showing a protection circuit using a diode-connected TFT, and ( b ) is a schematic cross-sectional view of the same diode-connected TFT. As shown in FIG. 9( a), two resistance elements R1, R2 are inserted between the connection pad 219 and the internal circuit 217, and in the middle of these resistance elements R1 and R2, the connection pads 219b (Vdd) and 219c ( Vss) connected to the line, respectively insert a diode connected to TFT30D. Referring to the cross-sectional structure shown in FIG. 9( b ), the diode connection TFT 30D includes: a semiconductor film 201 formed on a substrate 211 , and a gate electrode 213 a opposite to the gate insulating film 212 of the semiconductor film 201 ; The inside of the connection hole of the insulating films 212 and 216 is connected to the source electrode 208 and the drain electrode 209 of the semiconductor film 201 . Therefore, the connection electrode 213d connected to the gate 213a through the connection hole provided through the insulating film 216 and the drain electrode 209 are short-circuited to form a diode-connected TFT.

在这样的结构的基础上,若从连接焊盘219a输入正的浪涌电压时,在二极管连接TFT30D中有电流i流过,不能防止向内部电路217流入过大的电流。With such a structure, when a positive surge voltage is input from the connection pad 219a, a current i flows through the diode connection TFT 30D, and an excessive current flow into the internal circuit 217 cannot be prevented.

在如上述结构的保护电路中,若在保护电路中用二极管连接TFT时,具有能够利用构成内部电路的TFT的工序形成保护电路的优点。然而,在这种结构中,如图9(b)所示,若导入超过二极管连接TFT30D的耐压的浪涌电压,二极管连接TFT30D中,因电荷贯通是薄层绝缘膜的栅极绝缘膜212而形成短路线路bd。若形成这种短路状态,从半导体膜201的源极区域201b通过短路线路bd和栅极电极213a导通。结果,和栅极电极213a连接的漏极电极209和源极电极208成为导通状态。于是,如图9(a)所示的连接焊盘219和其他连接焊盘219b乃至219c成为导通,由于连接焊盘219a不能正常发挥功能,半导体装置自身会产生故障。In the protection circuit configured as above, if TFTs are connected with diodes in the protection circuit, there is an advantage that the protection circuit can be formed by utilizing the steps of TFTs constituting the internal circuit. However, in such a structure, as shown in FIG. 9(b), if a surge voltage exceeding the withstand voltage of the diode connection TFT 30D is introduced, the diode connection TFT 30D will be charged through the gate insulating film 212 which is a thin insulating film. And a short-circuit line bd is formed. When such a short-circuit state is formed, conduction is conducted from the source region 201b of the semiconductor film 201 through the short-circuit line bd and the gate electrode 213a. As a result, the drain electrode 209 and the source electrode 208 connected to the gate electrode 213a are turned on. Then, the connection pad 219 shown in FIG. 9( a ) becomes conductive with other connection pads 219b to 219c, and the connection pad 219a does not function normally, and the semiconductor device itself malfunctions.

发明内容 Contents of the invention

本发明是针对上述现有技术的问题而作出的,其目的为提供一种薄膜半导体装置及其制造方法,所述薄膜半导体装置具有可对内部电路良好保护免受浪涌电压影响的保护电路,对于因过大电压而被破坏的情况电路结构中不会产生故障,且具有优良可靠性的电路元件。The present invention is made in view of the above-mentioned problems of the prior art, and an object thereof is to provide a thin film semiconductor device having a protection circuit capable of well protecting an internal circuit from a surge voltage, and a method of manufacturing the same. A circuit element with excellent reliability that will not cause failure in the circuit structure when it is destroyed by excessive voltage.

为解决上述问题,本发明提供一种薄膜半导体装置,包括基体和该基体上形成的半导体膜,其特征在于,在所述基体上设置具有半导体元件的主电路部、由该主电路部延伸出的端子部、插入所述主电路部和端子部之间的保护电路部,所述保护电路部设置有保护电路元件,所述保护电路元件包括:具有所述半导体膜的PIN二极管,以及介于绝缘膜和该二极管的I层对向配置的浮置电极。In order to solve the above problems, the present invention provides a thin film semiconductor device, which includes a substrate and a semiconductor film formed on the substrate, and is characterized in that a main circuit part having a semiconductor element is provided on the substrate, and the main circuit part extends from the main circuit part. The terminal portion of the main circuit portion and the protection circuit portion inserted between the main circuit portion and the terminal portion, the protection circuit portion is provided with a protection circuit element, the protection circuit element includes: a PIN diode having the semiconductor film, and a The insulating film and the floating electrode arranged opposite to the I layer of the diode.

所述PIN二极管是具有划分为如周知的P层(P型半导体层)、I层(本征或微量浓度地导入杂质的半导体层)和N层(N型半导体层)的半导体膜的二极管。另外,浮置电极和其他电控制的导电膜或半导体层的构成部件不连接,成为电“浮置”的状态的电极。The PIN diode is a diode having a semiconductor film divided into a well-known P layer (P-type semiconductor layer), I layer (semiconductor layer into which impurities are intrinsically or at a slight concentration) and N layer (N-type semiconductor layer). In addition, the floating electrode is an electrode in an electrically "floating" state without being connected to other electrically controlled conductive films or constituent members of the semiconductor layer.

在本发明的薄膜半导体装置具备的保护电路元件中,由于具备PIN二极管以及与其I层对向配置的浮置电极,因而对于过大的电流流过保护电路元件,栅极绝缘膜被破坏而电贯通的场合,PIN二极管的P层(或N层)和浮置电极成为短络结构。然而,由于浮置电极与其他受电控制的导电层或半导体层不连接,即使保护电路元件被破坏后也能够确保PIN二极管的绝缘性。因此,若构成使用上述保护电路元件构成保护电路,可以提供一种薄膜半导体装置,其能够构成良好地旁路因静电引起的浪涌电压的静电保护电路,且输入足以破坏保护电路元件的浪涌电压后仍能工作。Since the protection circuit element included in the thin film semiconductor device of the present invention includes a PIN diode and a floating electrode disposed opposite to its I layer, if an excessive current flows through the protection circuit element, the gate insulating film is destroyed and the electric current is damaged. In the case of penetration, the P layer (or N layer) and the floating electrode of the PIN diode form a short-circuit structure. However, since the floating electrode is not connected to other electrically controlled conductive layers or semiconductor layers, the insulation of the PIN diode can be ensured even after the protection circuit element is destroyed. Therefore, if a protection circuit is constructed using the above-mentioned protection circuit elements, a thin film semiconductor device can be provided that can constitute an electrostatic protection circuit that can well bypass surge voltage caused by static electricity, and input a surge sufficient to destroy the protection circuit elements. It can still work after voltage.

另外,对于设置上述浮置电极和不设上述浮置电极的场合,可得到逆方向的保护性能差别很大。如此良好的半导体层那样没有浮置电极的状态,甚至对对应于击穿电压的电压也不能有保护性能,通过设置浮置电极,也会发生稍许的电流泄漏。即使对于由此引起的即便是轻微的对TFT装置带来的负面影响的逆向浪涌电压,也能够具有保护功能。In addition, there is a large difference in protection performance in the reverse direction between the case where the above-mentioned floating electrode is provided and the case where the above-mentioned floating electrode is not provided. Such a good semiconductor layer does not have a state of floating electrodes, and cannot have protection performance even against a voltage corresponding to the breakdown voltage, and a slight current leakage occurs by providing floating electrodes. It is possible to have a protection function even against the reverse surge voltage which is caused by this even slightly and which negatively affects the TFT device.

所述保护电路元件,即使对于过大电流流过而被破坏的场合,也能确保本体的绝缘性。为此,若设置具备这种保护电路元件的保护电路部,由端子部导入过大浪涌电流,即使因该电流而使保护电路元件被破坏,与以往的由二极管连接TFT构成的保护电路元件不同,连接端子部和主电路部的电路结构也不会发生变化。因此,通过本发明能够提供一种导入足以破坏保护电路元件的浪涌电压后也能正常工作、高可靠性和长寿命的薄膜半导体装置。The protection circuit element can ensure the insulation of the main body even if it is broken due to excessive current flow. For this reason, if a protective circuit unit including such a protective circuit element is provided, even if an excessive surge current is introduced from the terminal portion, and the protective circuit element is destroyed due to the current, it is different from the conventional protective circuit element composed of a diode-connected TFT. Differently, the circuit structure of the connection terminal part and the main circuit part does not change. Therefore, according to the present invention, it is possible to provide a thin film semiconductor device capable of normal operation even after a surge voltage sufficient to destroy a protection circuit element is introduced, and has high reliability and long life.

本发明的薄膜半导体装置中,优选为构成所述PIN二极管的半导体膜和构成所述主电路部的半导体元件的半导体膜是在所述基体上的同一层形成的半导体膜。若做成这种结构,由于主电路部的半导体元件和PIN二极管可在同一工序中形成,可实现提高薄膜半导体装置的可靠性而不受制造工序变化的影响。In the thin film semiconductor device according to the present invention, it is preferable that the semiconductor film constituting the PIN diode and the semiconductor film constituting the semiconductor element of the main circuit portion are formed in the same layer on the base. With such a structure, since the semiconductor element and the PIN diode of the main circuit portion can be formed in the same process, the reliability of the thin film semiconductor device can be improved without being affected by changes in the manufacturing process.

在本发明的薄膜半导体装置中,设置于所述主电路部的所述半导体元件是薄膜晶体管、构成所述浮置电极的导电膜和构成所述薄膜晶体管的栅极电极的导电膜优选为做成在所述基体上同一层形成的结构。通过这种结构,可以得到主电路部的薄膜晶体管和保护电路元件可在同一工序中形成的优点。In the thin film semiconductor device of the present invention, the semiconductor element provided in the main circuit part is a thin film transistor, and the conductive film constituting the floating electrode and the conductive film constituting the gate electrode of the thin film transistor are preferably made of into a structure formed in the same layer on the substrate. With this structure, there is an advantage that the thin film transistors of the main circuit portion and the protection circuit elements can be formed in the same process.

在本发明的薄膜的半导体装置中,优选为所述浮置电极和所述PIN二极管的I层在俯视时的大略同一位置形成。通过该结构,将所述浮置电极用作掩模掩模通过向半导体膜中导入杂质,由于能够自匹配地形成PIN晶体管的I层,因此成为可用简单工序制造的保护电路元件。在相关的结构中,若在主电路部中设有薄膜晶体管,由于能够在将薄膜晶体管的栅极作为掩模掩模,用自匹配地形成沟道区域的工序中同时形成所述PIN晶体管的I层,因而能够成为制造效率更加优良的薄膜半导体装置。In the thin-film semiconductor device of the present invention, it is preferable that the floating electrode and the I layer of the PIN diode are formed at substantially the same position in plan view. With this structure, since the I layer of the PIN transistor can be self-matched by introducing impurities into the semiconductor film using the floating electrode as a mask mask, it becomes a protection circuit element that can be manufactured with a simple process. In the related structure, if a thin film transistor is provided in the main circuit part, since the gate of the thin film transistor is used as a mask mask, the process of forming the channel region by self-matching can be simultaneously formed. I layer, and thus can become a thin film semiconductor device with better manufacturing efficiency.

本发明的薄膜半导体装置中,也可以是,在所述PIN二极管是在其P层和I层或N层和I层之间具有比该P层或N层杂质浓度低的低浓度杂质区域的结构。同通常的半导体装置一样,在设于薄膜半导体装置的薄膜晶体管中,为防止由热载流子引起的电气特性的劣化,多采用LDD(LightlyDoped Drain)结构。因此,若采用本结构相关的PIN二极管,对于同上述LDD结构的薄膜晶体管同时形成所述保护电路元件的情况,可以有效地寻求制造工序的通用化。能够提供电气特性更好的,可进一步提高PIN二极管的耐压的、可靠性高的保护电路元件。In the thin film semiconductor device of the present invention, the PIN diode may have a low-concentration impurity region between the P layer and the I layer or between the N layer and the I layer, which is lower in impurity concentration than the P layer or the N layer. structure. Like ordinary semiconductor devices, in thin film transistors provided in thin film semiconductor devices, in order to prevent the deterioration of electrical characteristics caused by hot carriers, LDD (Lightly Doped Drain) structure is often used. Therefore, if the PIN diode related to this structure is used, it is possible to effectively seek generalization of the manufacturing process for the case where the protective circuit element is formed at the same time as the thin film transistor having the LDD structure. The invention can provide a protective circuit element with better electrical characteristics, which can further improve the withstand voltage of the PIN diode and has high reliability.

在本发明的薄膜半导体装置中,所述低浓度杂质区域可以是在与所述浮置电极平面上重合的区域形成的结构。若做成这样的结构,主电路部的薄膜晶体管是具有GOLDD(Gate Overlapped Lightly Doped Drain)结构的器件,可以共通化制造工序,且能够进一步提高PIN二极管的耐压。In the thin film semiconductor device of the present invention, the low-concentration impurity region may be a structure formed in a region overlapping with the plane of the floating electrode. With such a structure, the thin-film transistor in the main circuit part is a device with a GOLDD (Gate Overlapped Lightly Doped Drain) structure, and the manufacturing process can be shared, and the withstand voltage of the PIN diode can be further improved.

本发明的薄膜半导体装置中,介于绝缘膜和所述PIN二极管的I层对向配置的浮置电极也可以是具有与所述PIN二极管的P层或N层的一部分平面上重合的部分的结构。In the thin film semiconductor device of the present invention, the floating electrode disposed opposite to the I layer of the PIN diode between the insulating film and the PIN diode may have a part that overlaps with a part of the P layer or the N layer of the PIN diode on the plane. structure.

若做成这样的结构,不必要局限于将与半导体膜一部分平面上重合地配置的浮置电极用作掩模对半导体膜进行杂质导入而所谓的自匹配地形成沟道区域的方法。因此,也可以用在通常的绝缘膜上图案形成的光刻胶作为掩模进行向半导体膜中导入杂质,在那样的场合中,能够提高制造工序的自由度。即,可以用共通的制造工序制造主电路和保护电路元件,也可以用其他的工序制造。即使对应于这种状况的制造工序不同,所得到的保护电路元件的电气特性可按照前述的再现,但也不能说没有变化。Such a structure is not necessarily limited to the method of forming a channel region by so-called self-matching by using a floating electrode arranged to overlap a part of the semiconductor film on a plane as a mask to introduce impurities into the semiconductor film. Therefore, it is also possible to introduce impurities into the semiconductor film using a photoresist patterned on an ordinary insulating film as a mask, and in such a case, the degree of freedom in the manufacturing process can be increased. That is, the main circuit and the protection circuit element may be manufactured in a common manufacturing process, or may be manufactured in another process. Even if the manufacturing process corresponding to this situation is different, the electrical characteristics of the obtained protective circuit element can be reproduced as described above, but it cannot be said that there is no change.

本发明的薄膜半导体装置中,所述保护电路元件优选为直接连接在所述端子部。In the thin film semiconductor device of the present invention, it is preferable that the protection circuit element is directly connected to the terminal portion.

如图9所示,用以往的二极管连接TFT用作保护电路元件的保护电路中,在连接焊盘219a和二极管连接TFT30D之间设有电阻元件R1。该电阻元件R1是由通常的N型或P型半导体层形成的元件,可起到抑制由从连接焊盘219a导入的浪涌引起的急剧电压上升的功能,是保护二极管连接TFT30D的器件。即使二极管连接TFT30D被破坏而导通时,起到避免电源线Vdd或Vss和连接焊盘219a直接短路的作用。与此相反,本发明涉及的薄膜半导体装置中,即使如先前记载的保护电路元件被破坏,由于焊盘219a也不会和电源线Vdd或Vss直接短路,因而能够确保端子部和主短路部的导通。可是相反,若在保护电路元件和端子部之间插入电阻元件,在所输入的浪涌电压过大的情况下,该电阻元件被破坏,由于端子部和内部电路部之间断线,薄膜半导体装置变得不能正常工作。因此,采用如本结构的保护电路元件和端子部直接连接的结构,成为即使导入足以破坏保护电路部的元件的电压也确保主电路部的正常工作的薄膜半导体装置。As shown in FIG. 9, in a protection circuit using a conventional diode connection TFT as a protection circuit element, a resistance element R1 is provided between the connection pad 219a and the diode connection TFT 30D. The resistive element R1 is an element formed of a normal N-type or P-type semiconductor layer, functions to suppress a sudden voltage rise caused by a surge introduced from the connection pad 219a, and protects the diode-connected TFT 30D. Even if the diode connection TFT 30D is broken and turned on, it serves to avoid direct short-circuiting between the power supply line Vdd or Vss and the connection pad 219a. On the contrary, in the thin film semiconductor device according to the present invention, even if the protection circuit element as described above is destroyed, since the pad 219a is not directly short-circuited with the power line Vdd or Vss, the connection between the terminal portion and the main short-circuit portion can be ensured. conduction. But on the contrary, if a resistance element is inserted between the protection circuit element and the terminal part, the resistance element will be destroyed when the input surge voltage is too large, and the thin film semiconductor device will be damaged due to a disconnection between the terminal part and the internal circuit part. become non-functional. Therefore, by directly connecting the protective circuit element and the terminal portion as in this configuration, it becomes a thin film semiconductor device that ensures normal operation of the main circuit portion even if a voltage sufficient to destroy the element of the protective circuit portion is introduced.

本发明的薄膜半导体装置的制造方法,是具有基体和形成于该基体上的半导体膜的薄膜半导体装置的制造方法,其特征在于,所述薄膜半导体装置在基体上设有具有半导体元件主电路部、由该主电路部延伸出的端子部、插入所述主电路部和端子部的保护电路部,形成所述保护电路部的工序包括保护电路元件形成工序,所述保护电路元件形成工序包括:在基体上形成半导体膜的工序、在所述半导体膜上形成绝缘膜的工序、通过在所述绝缘膜上图案形成导电膜而形成与所述半导体膜平面上重合的浮置电极的工序、通过以所述浮置电极为掩模在所述半导体膜中导入杂质形成在该半导体膜上形成P层、N层和I层的PIN二极管的工序。通过该制造方法,由于以所述浮置电极用作掩模向半导体膜导入杂质形成PIN二极管的各层,因而能够形成效率高、可靠性优良的保护电路元件,并且能够容易而高效地制造高可靠性的薄膜半导体装置。The method for manufacturing a thin film semiconductor device of the present invention is a method for manufacturing a thin film semiconductor device having a substrate and a semiconductor film formed on the substrate, wherein the thin film semiconductor device is provided with a main circuit portion having a semiconductor element on the substrate. , a terminal part extending from the main circuit part, a protection circuit part inserted into the main circuit part and the terminal part, the process of forming the protection circuit part includes a protection circuit element forming process, and the protection circuit element forming process includes: A step of forming a semiconductor film on a substrate, a step of forming an insulating film on the semiconductor film, a step of forming a floating electrode planarly overlapping the semiconductor film by patterning a conductive film on the insulating film, A step of introducing impurities into the semiconductor film by using the floating electrode as a mask to form a PIN diode on which a P layer, an N layer, and an I layer are formed. With this manufacturing method, since the layers of the PIN diode are formed by introducing impurities into the semiconductor film using the floating electrode as a mask, it is possible to form a protective circuit element with high efficiency and excellent reliability, and it is possible to easily and efficiently manufacture high Reliable thin film semiconductor devices.

通过该制造方法,因而能够容易而高效地制造具有外部连接电子的薄膜半导体装置,可良好地保护主电路部免受由端子部导入的浪涌电压影响的薄膜半导体装置。According to this manufacturing method, it is possible to easily and efficiently manufacture a thin-film semiconductor device having externally connected electrons and a thin-film semiconductor device capable of well protecting the main circuit part from surge voltage introduced from the terminal part.

本发明的薄膜半导体装置的制造方法,能够做成如下方法:所述主电路部含有包括半导体膜以及与所述半导体膜介于绝缘膜对向的栅极电极的薄膜晶体管,构成所述薄膜晶体管的半导体膜和构成所述保护电路元件的半导体膜在同一工序中形成,并且构成所述薄膜晶体管的栅极电极和构成所述保护电路元件的浮置电极在同一工序中形成。另外,在本发明的薄膜半导体装置的制造方法中,优选为所述薄膜晶体管的源极或漏极和所述PIN二极管的P层或N层,通过同一杂质导入工序形成。The method for manufacturing a thin film semiconductor device according to the present invention can be such that the main circuit part includes a thin film transistor including a semiconductor film and a gate electrode facing the semiconductor film with an insulating film interposed therebetween, and the thin film transistor is constituted. The semiconductor film and the semiconductor film constituting the protection circuit element are formed in the same process, and the gate electrode constituting the thin film transistor and the floating electrode constituting the protection circuit element are formed in the same process. In addition, in the manufacturing method of the thin film semiconductor device of the present invention, it is preferable that the source or drain of the thin film transistor and the P layer or N layer of the PIN diode are formed by the same impurity introducing step.

通过该制造方法,能够使构成所述主电路部的薄膜晶体管和保护电路元件以同一工序制造,能够制造不受对以往制造工序的变更影响的高可靠性的优良的薄膜半导体装置。According to this manufacturing method, the thin film transistors and protective circuit elements constituting the main circuit portion can be manufactured in the same process, and a highly reliable and excellent thin film semiconductor device that is not affected by changes in the conventional manufacturing process can be manufactured.

本发明的薄膜半导体装置的制造方法中,在所述杂质导入工序中,所述薄膜晶体管的半导体膜和所述保护电路元件的半导体膜,能够形成比邻接的杂质导入区域低杂质浓度的低浓度杂质领域。通过相关的制造方法,具备LDD结构的薄膜晶体管和具有所述PIN二极管以上的耐压的结构的保护电路元件能够在相同的工序中形成。In the method for manufacturing a thin film semiconductor device according to the present invention, in the impurity introducing step, the semiconductor film of the thin film transistor and the semiconductor film of the protective circuit element can be formed at a low impurity concentration lower than that of the adjacent impurity introduction region. Impurities field. According to the related manufacturing method, a thin film transistor having an LDD structure and a protection circuit element having a structure having a withstand voltage higher than that of the PIN diode can be formed in the same process.

本发明的电光学装置中,其特征在于,含有先前所述的薄膜半导体装置。先前的本发明相关的薄膜半导体装置,能够用作有源矩阵方式的电光学装置的TFT阵列基板。在相关的TFT阵列基板中,作为构成图像显示区域的像素的开关元件使用TFT,另外,设置于边缘区域的驱动电路中也形成使用TFT的反相器等。另外,也设置作为外部连接端子的端子部。因此,本发明的结构若适用于相关的TFT阵列基板,能够通过保护电路部良好地保护构成内部电路的上述图像显示区域的开关元件和驱动电路,能够构成可靠性优良寿命长的电光学装置。The electro-optical device of the present invention is characterized by including the aforementioned thin-film semiconductor device. The thin-film semiconductor device according to the previous invention can be used as a TFT array substrate of an active matrix electro-optical device. In the related TFT array substrate, TFTs are used as switching elements constituting pixels in the image display area, and inverters using TFTs are also formed in the drive circuits provided in the edge area. In addition, a terminal portion serving as an external connection terminal is also provided. Therefore, if the structure of the present invention is applied to the related TFT array substrate, the switching element and the driving circuit in the above-mentioned image display area constituting the internal circuit can be well protected by the protection circuit section, and an electro-optical device with excellent reliability and long life can be constructed.

接下来,本发明的电子机器,其特征在于,具有先前所记载的本发明的电光学装置。通过该结构,能够提供具有可对内部电路良好保护免受浪涌电压等过大电压影响的保护电路,以及具有可靠性优良、寿命长的显示部的电子机器。Next, the electronic device of the present invention is characterized by having the electro-optical device of the present invention described above. With this configuration, it is possible to provide an electronic device having a protection circuit capable of well protecting the internal circuit from excessive voltage such as a surge voltage, and a display unit having excellent reliability and a long life.

附图说明 Description of drawings

图1本发明第一实施方式相关的薄膜半导体装置的保护电路结构图。FIG. 1 is a configuration diagram of a protection circuit of a thin film semiconductor device according to the first embodiment of the present invention.

图2本发明第一实施方式相关的保护电路元件的平面结构图及剖视结构图。2 is a plan view and a cross-sectional view of a protective circuit element according to the first embodiment of the present invention.

图3表示本发明的实施方式相关的液晶显示装置的图。FIG. 3 is a diagram showing a liquid crystal display device according to an embodiment of the present invention.

图4本发明的液晶显示装置电路结构图及薄膜晶体管(TFT)剖视图。4 is a circuit structure diagram of a liquid crystal display device of the present invention and a cross-sectional view of a thin film transistor (TFT).

图5本发明的第二实施方式相关的保护电路元件的概略剖视图。5 is a schematic cross-sectional view of a protection circuit element according to a second embodiment of the present invention.

图6本发明的第三实施方式相关的保护电路元件的概略剖视图。6 is a schematic cross-sectional view of a protection circuit element according to a third embodiment of the present invention.

图7本发明的第四实施方式相关的保护电路元件的概略剖视图。7 is a schematic cross-sectional view of a protection circuit element according to a fourth embodiment of the present invention.

图8表示电子机器的一个例子的立体结构图。FIG. 8 is a perspective view showing an example of an electronic device.

图9表示以往的薄膜半导体装置的保护电路的图。FIG. 9 is a diagram showing a protection circuit of a conventional thin film semiconductor device.

图10表示比较有、无本发明相关的浮置电极的PIN二极管的TLP特性的图。FIG. 10 is a graph comparing the TLP characteristics of PIN diodes with and without the floating electrodes according to the present invention.

图11本发明相关的其他薄膜半导体装置的保护电路结构图。FIG. 11 is a structural diagram of protection circuits of other thin film semiconductor devices related to the present invention.

图12表示比较有、无本发明相关的低浓度区域的PIN二极管的电气特性的图。Fig. 12 is a graph comparing the electrical characteristics of PIN diodes with and without the low-concentration region related to the present invention.

图中:11-基板(基体),2-第1绝缘膜(栅极绝缘膜),6-第2绝缘膜(层间绝缘膜),181a-PIN二极管,118p-p层,118n-N层,118i-I层,118s-半导体膜,118g-浮置电极,181、182、281、381、481-保护电路元件(薄膜半导体元件),218n、318n-低浓度杂质领域。In the figure: 11-substrate (base body), 2-first insulating film (gate insulating film), 6-second insulating film (interlayer insulating film), 181a-PIN diode, 118p-p layer, 118n-N layer , 118i-I layer, 118s-semiconductor film, 118g-floating electrode, 181, 182, 281, 381, 481-protection circuit elements (thin film semiconductor elements), 218n, 318n-low-concentration impurity regions.

具体实施方式 Detailed ways

[第一实施方式][first embodiment]

以下参照附图说明本发明的实施方式。本实施方式示例性地说明本发明相关的薄膜半导体装置的基本结构和安装有薄膜半导体装置的电光元件。Embodiments of the present invention will be described below with reference to the drawings. This embodiment mode exemplifies the basic structure of the thin-film semiconductor device according to the present invention and an electro-optical element in which the thin-film semiconductor device is mounted.

(薄膜半导体装置)(thin film semiconductor device)

图1是表示本发明相关的薄膜半导体装置的电路构成的概略结构图。如图1所示,本实施方式的薄膜半导体装置包括内部电路(主电路部)17、保护电路部18和端子部19。端子部19上设有多个连接焊盘19a~19c。在这些连接焊盘19a~19c和内部电路17之间插入保护电路部18。连接焊盘19b、9c是电源输入终端(Vdd,Vss)。FIG. 1 is a schematic configuration diagram showing a circuit configuration of a thin film semiconductor device according to the present invention. As shown in FIG. 1 , the thin film semiconductor device of this embodiment includes an internal circuit (main circuit portion) 17 , a protection circuit portion 18 , and a terminal portion 19 . A plurality of connection pads 19 a to 19 c are provided on the terminal portion 19 . A protection circuit unit 18 is interposed between these connection pads 19 a to 19 c and the internal circuit 17 . The connection pads 19b, 9c are power input terminals (Vdd, Vss).

保护电路部18包括串联连接的多个保护电路元件181、182。从所述连接焊盘19a延伸出的信号布线23通过电阻元件18b连接在两个保护电路元件181、182之间。另一方面,由内部电路17延伸出的信号布线24通过电阻元件18c同保护电路元件181、182和信号布线23连接。The protection circuit unit 18 includes a plurality of protection circuit elements 181 and 182 connected in series. The signal wiring 23 extending from the connection pad 19a is connected between the two protection circuit elements 181, 182 through the resistance element 18b. On the other hand, the signal wiring 24 extending from the internal circuit 17 is connected to the protection circuit elements 181 and 182 and the signal wiring 23 through the resistance element 18c.

另外,保护电路元件181的一端(阴极侧)通过信号布线与作为电源输入端子的连接焊盘19b(Vdd)连接。保护电路元件182的一端(阳极侧)通过信号布线与连接焊盘19c(Vss)连接。In addition, one end (cathode side) of the protection circuit element 181 is connected to the connection pad 19b (Vdd) which is a power supply input terminal through a signal wiring. One end (anode side) of the protection circuit element 182 is connected to the connection pad 19c (Vss) through a signal wiring.

图2(a)是表示图1所示的181的具体结构例的平面结构图,图2(b)是图2(a)的沿A-A线的剖面结构图。FIG. 2(a) is a plan view showing a specific structural example of 181 shown in FIG. 1, and FIG. 2(b) is a cross-sectional view along line A-A of FIG. 2(a).

另外,在图2中,仅示出了保护电路部181的主要部分,省略了连接在相同元件上的布线等。另外,另一方的保护电路元件182也具有同保护电路元件181相同的结构。In addition, in FIG. 2, only the main part of the protection circuit part 181 is shown, and the wiring etc. connected to the same element are omitted. In addition, the other protection circuit element 182 also has the same structure as the protection circuit element 181 .

如图2所示,本实施方式相关的保护电路元件181包括PIN二极管181a以及与该PIN二极管181a的一部分平面上地重合配置的浮置电极118g。PIN二极管181a包括半导体膜118s以及与半导体膜118s连接的多个(图中所示为4个)阳极电极118a和多个(图中所示为4个)阴极电极118c。在半导体膜118s上,形成有P层118p、N层118n、和配置于它们之间的I层118i,阳极电极118a导电连接在P层118p上,阴极电极118c导电连接在N层118n上。而且,浮置电极118g被相对配置在PIN二极管181a的I层118i中。As shown in FIG. 2 , the protection circuit element 181 according to this embodiment includes a PIN diode 181 a and a floating electrode 118 g arranged to overlap a part of the PIN diode 181 a planarly. The PIN diode 181a includes a semiconductor film 118s, and a plurality of (four shown in the drawing) anode electrodes 118a and a plurality of (four shown in the drawing) cathode electrodes 118c connected to the semiconductor film 118s. On the semiconductor film 118s, a P layer 118p, an N layer 118n, and an I layer 118i disposed therebetween are formed, the anode electrode 118a is electrically connected to the P layer 118p, and the cathode electrode 118c is electrically connected to the N layer 118n. Furthermore, the floating electrode 118g is disposed opposite to the I layer 118i of the PIN diode 181a.

参见图2(b)截面结构,在基板11上形成有诸如多晶硅膜形成的半导体膜118s,形成有覆盖半导体膜118s的诸如氧化硅形成的第1绝缘膜2。在第1绝缘膜2上形成由诸如铝、钽、钼、多晶硅等形成的浮置电极118g,形成覆盖浮置电极118g的第2绝缘膜6。因此,在到达贯通第2绝缘膜6和第1绝缘膜2的半导体膜118s的连接孔中,埋置有阳极电极118a和阴极电极118c,并分别与P层118p和N层118n电连接。Referring to the cross-sectional structure of FIG. 2(b), a semiconductor film 118s such as polysilicon film is formed on the substrate 11, and a first insulating film 2 such as silicon oxide is formed covering the semiconductor film 118s. A floating electrode 118g made of, for example, aluminum, tantalum, molybdenum, polysilicon, etc. is formed on the first insulating film 2, and a second insulating film 6 covering the floating electrode 118g is formed. Therefore, the anode electrode 118a and the cathode electrode 118c are embedded in the connection hole reaching the semiconductor film 118s penetrating the second insulating film 6 and the first insulating film 2, and are electrically connected to the P layer 118p and the N layer 118n, respectively.

所述保护电路元件181所包括的浮置电极118g,如图2(b)所示,由埋设在第1绝缘膜2和第2绝缘膜6之间的导电膜形成,不和其他元件连接,也不接地,取得任意电位的电极。The floating electrode 118g included in the protection circuit element 181 is formed of a conductive film buried between the first insulating film 2 and the second insulating film 6 as shown in FIG. An electrode of any potential is obtained without being grounded.

另外,图1所示的内部电路17,同保护电路部18一样,含有利用形成于基板之上的薄膜半导体膜形成的半导体元件,是含有诸如TFT(薄膜晶体管)的结构。In addition, the internal circuit 17 shown in FIG. 1, like the protection circuit unit 18, includes a semiconductor element formed of a thin film semiconductor film formed on a substrate, and has a structure such as a TFT (Thin Film Transistor).

若借助具有上述结构的本实施方式的薄膜半导体装置,通过具备保护电路元件181的保护电路部18,能够良好地保护内部电路17免受通过诸如焊盘19a导入的静电等正的浪涌电压的影响。也就是说,如果从连接焊盘19a导入浪涌电压,PIN二极管181和182之间流过电流,浪涌电流被旁路到电源输入端子侧,阻止内部电路17侧流过过大电流。According to the thin film semiconductor device of this embodiment having the above-mentioned structure, the internal circuit 17 can be well protected from positive surge voltage such as static electricity introduced through the pad 19a by the protection circuit portion 18 provided with the protection circuit element 181. Influence. That is, when a surge voltage is introduced from the connection pad 19a, a current flows between the PIN diodes 181 and 182, and the surge current is bypassed to the power input terminal side, preventing excessive current from flowing to the internal circuit 17 side.

另外,本实施方式的薄膜半导体装置即使对于保护电路元件181、182被超过耐压的浪涌电压破坏的情况,内部电路17和连接焊盘19a之间的电连接也不会产生不正常。这在用以往的二极管连接TFT的保护电路中是不可能得到的优点。In addition, in the thin film semiconductor device of this embodiment, even when the protection circuit elements 181 and 182 are destroyed by a surge voltage exceeding the breakdown voltage, the electrical connection between the internal circuit 17 and the connection pad 19a does not malfunction. This is an advantage that could not be obtained in the protection circuit of conventional diode-connected TFTs.

若通过图2所示的保护电路元件181具体地说明,对于具有浮置电极118g的保护电路元件181被破坏的情况,同图9所示的二极管连接电极TFT30D一样,由薄层绝缘膜形成的第1绝缘膜2因贯通电荷而劣化,PIN二极管181a的P层118p(或N层118n)和浮置电极118g之间成为短路状态的情况较多。并且,在这种短路状态中,与以往的二极管连接TFT30D成为导通状态相对应,本实施方式涉及的保护电路元件118中P层118p和浮置电极118g之间的成为短路,由于浮置电极118g和其他结构器件之间没有电连接,PIN二极管181a的阳极电极118a和阴极电极118c之间不会产生短路。因此,破坏后的保护电路元件181作为单纯的绝缘体工作。从而,保持焊盘19a和内部电路19之间电路连接的结构,即使超过保护电路的耐压的浪涌电压导入后,薄膜半导体装置也能够不产生故障而正常地工作。If the protection circuit element 181 shown in FIG. 2 is used to describe specifically, for the case where the protection circuit element 181 having the floating electrode 118g is destroyed, like the diode connection electrode TFT 30D shown in FIG. The first insulating film 2 is degraded by the through charge, and the P layer 118p (or N layer 118n) of the PIN diode 181a and the floating electrode 118g are often short-circuited. In addition, in this short-circuit state, corresponding to the conduction state of the conventional diode-connected TFT 30D, in the protection circuit element 118 according to the present embodiment, the short circuit between the P layer 118p and the floating electrode 118g is formed, and since the floating electrode There is no electrical connection between 118g and other structural devices, and there is no short circuit between the anode electrode 118a and the cathode electrode 118c of the PIN diode 181a. Therefore, the destroyed protective circuit element 181 functions as a simple insulator. Therefore, by maintaining the circuit connection between the pad 19a and the internal circuit 19, even if a surge voltage exceeding the withstand voltage of the protection circuit is introduced, the thin film semiconductor device can operate normally without failure.

另外,本实施方式的保护电路元件,即使对于相反方向的浪涌电压,也会产生同样的效果。图10是有无浮置电极的PIN二极管的TLP(transmission line pulse)测定结果。横轴表示向相反方向的保护电路元件的负荷电压。纵轴表示此时流过保护电路元件的电流。另外,图中实线是有浮置电极的情况,虚线是没有浮置电极的情况。从该图可以明白,在负荷电压超过20V的区域,具有浮置电极的二极管的曲线的斜率变大。也就是说,本实施方式即使对相反方向的电压,也具有低负荷电压区域的电流特性。因此,利用本实施方式的保护元件,对于不论是正方向的还是反方向的低浪涌电压均能组成形成旁路的保护电路。通过本发明,能够发挥双极性保护元件的保护性能。In addition, the protection circuit element of the present embodiment produces the same effect even against a surge voltage in the opposite direction. Figure 10 shows the TLP (transmission line pulse) measurement results of PIN diodes with and without floating electrodes. The horizontal axis represents the load voltage of the protection circuit element in the opposite direction. The vertical axis represents the current flowing through the protection circuit element at this time. In addition, the solid line in the figure is the case where there is a floating electrode, and the dotted line is the case where there is no floating electrode. As can be seen from this figure, the slope of the curve of the diode having a floating electrode becomes larger in a region where the load voltage exceeds 20V. In other words, the present embodiment has current characteristics in the low load voltage region even for voltages in opposite directions. Therefore, with the protection element of this embodiment, it is possible to constitute a protection circuit that bypasses low surge voltage regardless of whether it is in the forward direction or in the reverse direction. According to the present invention, the protection performance of the bipolar protection element can be exhibited.

另外,具有能够达到上述作用效果的保护电路部18的薄膜半导体装置,如图11所示,也可以不设置图1所示的电阻元件18b而构成,做成保护电路元件181、182和连接焊盘19a之间通过布线23直接连接的结构。电阻元件18b,对于从焊盘19a导入浪涌电压时,抑制电路中电压的急剧上升,起到保护电路的作用,对于导入过大的浪涌电压的情况,甚至电阻元件18b也被破坏,有时产生断线。因此,若这样的电阻元件18b断线,连接焊盘19a和内部电路17断开,对薄膜半导体的工作带来故障。对此,若做成设置保护电路元件181、182,而不设置电阻元件18b的结构,即使对于因过大的浪涌电压导入而使保护电路元件被破坏的场合,由于连接焊盘19a和内部电路17确保导通,因此不会因保护电路部18的破坏而引起薄膜半导体装置自身无法工作,能够延长薄膜半导体装置的寿命。In addition, the thin film semiconductor device having the protective circuit portion 18 that can achieve the above-mentioned effects, as shown in FIG. 11, may also be configured without the resistor element 18b shown in FIG. A structure in which pads 19a are directly connected by wires 23 . The resistance element 18b, when the surge voltage is introduced from the pad 19a, suppresses the sharp rise of the voltage in the circuit, and plays a role in protecting the circuit. For the situation of introducing an excessive surge voltage, even the resistance element 18b is also destroyed, sometimes A disconnection occurs. Therefore, if such a resistance element 18b is disconnected, the connection pad 19a and the internal circuit 17 are disconnected, which causes trouble in the operation of the thin film semiconductor. In this regard, if the protection circuit elements 181, 182 are provided without the structure of the resistance element 18b, even if the protection circuit elements are damaged due to the introduction of excessive surge voltage, due to the connection between the pad 19a and the internal Since the electric circuit 17 ensures continuity, the thin-film semiconductor device itself does not fail to operate due to damage to the protection circuit unit 18, and the lifetime of the thin-film semiconductor device can be extended.

(电光学装置)(electro-optical device)

上述的本发明相关的半导体装置中,能够构成有源矩阵型(active-matrix-type)装置。以下,作为含有图1所示的薄膜半导体装置的电光学装置的一个例子,说明有源矩阵方式的透过型液晶显示装置。In the semiconductor device according to the present invention described above, an active-matrix-type device can be configured. Hereinafter, an active matrix transmissive liquid crystal display device will be described as an example of an electro-optical device including the thin film semiconductor device shown in FIG. 1 .

图3(a)是说明本实施方式的液晶显示装置从各组成元件和对向对向基板侧观察的俯视图,图3(b)是图3(a)沿H-H’线的剖视图。另外,在用于以下说明的各图中,为了使得各层和各器件达到在图面上可辨认程度的大小,各层和各器件具有不同的比例尺。Fig. 3(a) is a plan view illustrating the liquid crystal display device of this embodiment viewed from the side of each component and the opposing substrate, and Fig. 3(b) is a cross-sectional view along line H-H' of Fig. 3(a). In addition, in each drawing used for the following description, each layer and each device have a different scale so that each layer and each device have a size recognizable on the drawing.

本实施方式的液晶显示装置10,如图3(a)、(b)所示,具有由透明基板形成的TFT阵列基板11(基体)和对向基板12通过密封材料13贴合,在由密封材料13所分割的空间内封入液晶层14的结构。TFT阵列基板11的大概中央部位形成图像显示区域17c。在其外侧的边缘区域16,沿着TFT阵列基板11的一条长边的区域(在图3中为沿X方向的边)设有数据线驱动电路17a。数据线驱动电路17a是由与图像显示区域17c的X方向的像素数相同数目的单位电路(图略)组成。另一方面,在图像显示区域17c的两侧,沿着TFT阵列基板11的两条短边的区域(在图3中为沿Y方向的边)分别设有两条扫描线驱动电路17b。而且,在TFT阵列基板11的剩下的一条边上设置多条布线22,以连接设置于图像显示区域17c的两侧的扫描线驱动电路17b和17b。The liquid crystal display device 10 of this embodiment, as shown in Figure 3 (a), (b), has a TFT array substrate 11 (substrate) formed by a transparent substrate and a counter substrate 12 bonded by a sealing material 13. The liquid crystal layer 14 is enclosed in the space divided by the material 13 . An image display region 17 c is formed in a substantially central portion of the TFT array substrate 11 . In the outer edge region 16, a data line driving circuit 17a is provided along one long side region of the TFT array substrate 11 (the side along the X direction in FIG. 3). The data line driving circuit 17a is composed of the same number of unit circuits (not shown) as the number of pixels in the X direction of the image display area 17c. On the other hand, on both sides of the image display area 17c, two scan line drive circuits 17b are provided along the two short sides of the TFT array substrate 11 (the sides along the Y direction in FIG. 3 ). Furthermore, a plurality of wires 22 are provided on the remaining side of the TFT array substrate 11 to connect the scanning line driving circuits 17b and 17b provided on both sides of the image display area 17c.

另外,在靠近TFT阵列基板11数据线驱动电路17a的边端,沿X方向以规定间距设置为一列用于在该TFT阵列基板11上连接FPC的多个连接焊盘19a。因此,在这些连接焊盘19a和数据线驱动电路17a之间,设有保护电路部18。由连接焊盘19a延伸出的多条布线23、24通过保护电路部18同数据线驱动电路17a、扫描线驱动电路17b、17b,以及连接焊盘19a电连接。In addition, a plurality of connection pads 19a for connecting FPCs on the TFT array substrate 11 are arranged in a row at a predetermined pitch along the X direction near the edge end of the data line driving circuit 17a of the TFT array substrate 11 . Therefore, a protection circuit unit 18 is provided between these connection pads 19a and the data line drive circuit 17a. The plurality of wires 23 and 24 extending from the connection pad 19a are electrically connected to the data line drive circuit 17a, the scan line drive circuits 17b and 17b, and the connection pad 19a through the protection circuit unit 18.

从而,在本实施方式的液晶显示装置10中,数据线驱动电路17a和两个扫描线驱动电路17b以及图像显示领域17c相当于图1所示的内部电路(主电路部)17的结构要素。成为该内部电路的同具有多个连接焊盘的19a连接部19,通过保护电路部18电连接的结构。Therefore, in the liquid crystal display device 10 of the present embodiment, the data line driving circuit 17a, the two scanning line driving circuits 17b, and the image display area 17c correspond to components of the internal circuit (main circuit unit) 17 shown in FIG. 1 . This internal circuit is electrically connected to the connection portion 19 having a plurality of connection pads 19 a through the protection circuit portion 18 .

另外,如图1和图2所示,数据线驱动电路17a和连接焊盘19a…之间设置的保护电路部18是将保护电路元件181、182作为主体形成的静电保护电路,通过保护电路元件181、182旁路浪涌电流,以保护在图像显示区域17c内形成的像素开关元件以及驱动电路17a、17b。另外,在本实施方式中,保护电路部18于图像显示区域于图像显示区域17c的左侧用和右侧用设置两个。In addition, as shown in FIG. 1 and FIG. 2, the protection circuit part 18 provided between the data line drive circuit 17a and the connection pads 19a... is an electrostatic protection circuit mainly formed of protection circuit elements 181 and 182. By protecting the circuit elements 181, 182 bypass the surge current to protect the pixel switching elements and the driving circuits 17a, 17b formed in the image display region 17c. In addition, in the present embodiment, two protective circuit units 18 are provided in the image display area for the left side and for the right side of the image display area 17c.

另外,在对向基板12的角部,配置有用于TFT阵列基板11和对向基板12之间导电的基板间导通材料25(上下导通部)。在对向基板12设有共通电极(图略)。用于为该共通电极供给共通电位的布线32通过基板间导通材料25设置TFT阵列基板11上,配置在TFT阵列基板11的最外周位置。在图3(b)上附上符号9而示出的构成元件,是图像显示区域17c内的各像素的每个所设置的像素电极。In addition, an inter-substrate conduction material 25 (upper and lower conduction portions) for conduction between the TFT array substrate 11 and the opposite substrate 12 is arranged at the corner of the opposite substrate 12 . A common electrode (not shown) is provided on the counter substrate 12 . The wiring 32 for supplying a common potential to the common electrode is provided on the TFT array substrate 11 through the inter-substrate conductive material 25 and arranged at the outermost peripheral position of the TFT array substrate 11 . Component elements shown with reference numeral 9 in FIG. 3( b ) are pixel electrodes provided for each pixel in the image display region 17 c.

接下来,在图4(a)是液晶显示装置10的电路结构图。图(b)是表示图(a)所示的TFT30的概略剖视结构的图。如图4(a)所示,在液晶显示装置的10的图像显示区域17c上形成互相交叉延伸的多条数据线6a和扫描线3a,在由数据线6a和扫描线3a围成的矩形状区域中设置像素X,图4中仅示出一个像素,在像素显示区域17c中,多个像素X以俯视时为矩阵状配置。Next, FIG. 4( a ) is a circuit configuration diagram of the liquid crystal display device 10 . Drawing (b) is a figure which shows the schematic cross-sectional structure of TFT30 shown in drawing (a). As shown in Figure 4 (a), a plurality of data lines 6a and scan lines 3a extending across each other are formed on the image display area 17c of the liquid crystal display device 10, in a rectangular shape surrounded by the data lines 6a and the scan lines 3a Pixels X are provided in the region, and only one pixel is shown in FIG. 4 . In the pixel display region 17c, a plurality of pixels X are arranged in a matrix in plan view.

在各像素X中,对应于数据线6a和扫描线3a交叉的位置,设置作为像素开关元件的TFT30,扫描线3a接在TFT30的栅极,数据线6a接在源极,漏极上连接对液晶层14施加电场的像素电极9。另外,接有和像素电极9并联的蓄积电容器70,与像素电极9相反一侧的电极接在电容线3b上。In each pixel X, corresponding to the position where the data line 6a and the scanning line 3a intersect, a TFT 30 as a pixel switching element is arranged, the scanning line 3a is connected to the gate of the TFT 30, the data line 6a is connected to the source, and the drain is connected to the The liquid crystal layer 14 applies an electric field to the pixel electrode 9 . Also, a storage capacitor 70 is connected in parallel with the pixel electrode 9, and an electrode opposite to the pixel electrode 9 is connected to the capacitance line 3b.

若仅参照图4(b)所示的TFT30的剖视结构,TFT基板阵列11上形成半导体膜1a,形成覆盖半导体膜1a的栅极绝缘膜(第1绝缘膜)2,形成介于栅极绝缘膜2和半导体膜1a相对的栅极电极(扫描线)3a。半导体膜1a具有源极区域1b、漏极区域1c和沟道区域1a’。在半导体膜1a中,沟道区域1a’和栅极电极3a相对。形成覆盖栅极电极3a和栅极绝缘膜2的层间绝缘膜(第2绝缘膜)6,在贯通该层间绝缘膜6和栅极绝缘膜2的半导体膜1a的源极区域1b和漏极区域1c设有到达的连接孔。通过所述连接孔数据线6a和源极区域1b电连接,像素电极9和漏极区域1c电连接。该TFT30可以是P沟道型、N沟道型的任意一种。If only referring to the cross-sectional structure of TFT 30 shown in FIG. The gate electrode (scanning line) 3a facing the insulating film 2 and the semiconductor film 1a. The semiconductor film 1a has a source region 1b, a drain region 1c, and a channel region 1a'. In the semiconductor film 1a, the channel region 1a' faces the gate electrode 3a. An interlayer insulating film (second insulating film) 6 covering the gate electrode 3a and the gate insulating film 2 is formed, and the source region 1b and the drain region 1b of the semiconductor film 1a penetrating the interlayer insulating film 6 and the gate insulating film 2 are formed. The pole region 1c is provided with connecting openings for reaching. The data line 6a is electrically connected to the source region 1b through the connection hole, and the pixel electrode 9 is electrically connected to the drain region 1c. This TFT 30 may be either of a P-channel type or an N-channel type.

图4(c)是设置有数据线驱动电路17a和扫描线驱动电路17b的反相器(CMOS-TFT)117的概略剖视图。反相器117具有P沟道TFT117P和N沟道TFT117N通过电极(输出端子)117c相互连接的结构。TFT117P、TFT117N分别使用TFT阵列基板11上形成的半导体膜117s形成。栅极电极(输入端子)117g介于覆盖半导体膜117s而形成的栅极绝缘膜2,和半导体膜117s对向配置。FIG. 4(c) is a schematic cross-sectional view of an inverter (CMOS-TFT) 117 provided with a data line driving circuit 17a and a scanning line driving circuit 17b. The inverter 117 has a structure in which a P-channel TFT 117P and an N-channel TFT 117N are connected to each other through an electrode (output terminal) 117c. TFT 117P and TFT 117N are formed using semiconductor film 117 s formed on TFT array substrate 11 , respectively. The gate electrode (input terminal) 117g is arranged to face the semiconductor film 117s with the gate insulating film 2 formed to cover the semiconductor film 117s interposed therebetween.

本实施方式中,图4(b)所示的TFT30的半导体膜1a,图4(c)所示的反相器117的半导体膜117s,以及图2(b)所示的保护电路元件181的半导体膜118s,均是利用TFT阵列基板11上同层形成的半导体膜而形成。另外,TFT30的栅极电极3a、反相器的117的栅极电极117g,保护电路元件181的浮置电极118g,均利用形成于覆盖上述半导体膜而形成的栅极绝缘膜(第1绝缘膜)2的导电膜形成。因此,任何半导体元件,在同半导体膜、栅极电极(或浮置电极)平面上重合的区域,是本征半导体区域或导入微量浓度杂质的区域,设有沟道区域1a’、I层118i等。In this embodiment, the semiconductor film 1a of the TFT 30 shown in FIG. 4(b), the semiconductor film 117s of the inverter 117 shown in FIG. 4(c), and the protective circuit element 181 shown in FIG. 2(b) The semiconductor films 118s are all formed using the semiconductor films formed in the same layer on the TFT array substrate 11 . In addition, the gate electrode 3a of the TFT 30, the gate electrode 117g of the inverter 117, and the floating electrode 118g of the protection circuit element 181 are all formed on the gate insulating film (first insulating film) formed to cover the above-mentioned semiconductor film. ) 2 conductive film formation. Therefore, in any semiconductor element, the region overlapping with the semiconductor film and the gate electrode (or floating electrode) plane is an intrinsic semiconductor region or a region where a trace concentration of impurities is introduced, and a channel region 1a' and an I layer 118i are provided. wait.

在上述结构的本实施方式的液晶显示装置10中,由于具备前述的薄膜半导体装置的结构,能够通过保护电路部18保护内部电路(数据线驱动电路17a、扫描线驱动电路17b、及图像显示区域17c)免受由连接焊盘19a导入的浪涌电压的影像。藉此,成为制造时和使用时难于产生内部电路破坏,具有优良可靠性的长寿命液晶显示装置。另外,在保护电路部18中,具有如下优点:即使对于输入超过有此种结构的PIN二极管的耐压而PIN二极管被破坏的情况,也不发生连接焊盘19a彼此短路。具有不产生液晶显示装置工作不正常的效果。In the liquid crystal display device 10 of the present embodiment having the above-mentioned structure, since the above-mentioned structure of the thin film semiconductor device is provided, the internal circuits (the data line driving circuit 17a, the scanning line driving circuit 17b, and the image display area) can be protected by the protection circuit portion 18. 17c) Protects from the image of the surge voltage introduced by the connection pad 19a. This provides a long-life liquid crystal display device that is less prone to internal circuit breakdown during manufacture and use and has excellent reliability. In addition, in the protection circuit section 18, there is an advantage that even if the input exceeds the withstand voltage of the PIN diode with such a structure and the PIN diode is destroyed, the connection pads 19a do not short-circuit to each other. It has the effect of not causing abnormal operation of the liquid crystal display device.

另外,如上所述,液晶显示装置10所具备的半导体元件(TFT30、反相器117、以及保护电路元件181),由于共通地做成在导电膜上介于绝缘膜和半导体膜对向配置的结构,因而半导体膜1a、117s、118s的形成工序以及栅极电极3a、117g、浮置电极118g的形成工序能够做成通用的工序。另外,即使向半导体模导入杂质时,将栅极电极3a、117g、以及浮置电极118g用作掩模对半导体膜进行杂质注入,晶体管的沟道区域和PIN二极管的I层能够自匹配地形成。In addition, as described above, the semiconductor elements (TFT 30 , inverter 117 , and protection circuit element 181 ) included in the liquid crystal display device 10 are arranged in common on the conductive film with the insulating film and the semiconductor film facing each other. structure, the steps of forming the semiconductor films 1a, 117s, and 118s and the steps of forming the gate electrodes 3a, 117g, and floating electrodes 118g can be made common. In addition, even when impurities are introduced into the semiconductor film, the gate electrode 3a, 117g, and the floating electrode 118g are used as masks to implant impurities into the semiconductor film, and the channel region of the transistor and the I layer of the PIN diode can be formed in a self-matching manner. .

从而,在本实施方式的液晶显示装置10中,作为构成内部电路的数据线驱动电路17a、扫描线驱动电路17b、以及图像显示区域17c的静电保护电路功能的保护电路部18,能够同时地通过内部电路形成工序形成,可以在不使制造工序复杂化的同时提高显示装置的可靠性。Therefore, in the liquid crystal display device 10 of the present embodiment, the data line driving circuit 17a, the scanning line driving circuit 17b constituting the internal circuit, and the protection circuit unit 18 functioning as an electrostatic protection circuit for the image display area 17c can be simultaneously passed through The internal circuit forming process can improve the reliability of the display device without complicating the manufacturing process.

〔第二实施方式〕[Second Embodiment]

接下来,说明有关本发明的第二实施方式。图5是第二实施方式相关的薄膜半导体装置所具备的保护电路元件的概略剖视图。图5是相当于先前的第1实施方式的图2(b)的图,本实施方式相关的保护电路元件281的平面结构同图2(a)所示的保护电路元件181的基本相同。Next, a second embodiment of the present invention will be described. 5 is a schematic cross-sectional view of a protection circuit element included in the thin film semiconductor device according to the second embodiment. 5 is a diagram corresponding to FIG. 2( b ) of the previous first embodiment, and the planar structure of the protection circuit element 281 according to this embodiment is basically the same as that of the protection circuit element 181 shown in FIG. 2( a ).

图5所示的保护电路元件281以PIN二极管281a和浮置电极118g作为主体构成。因此,其特征为:于同PIN二极管281a的半导体膜118s和浮置电极118g平面重合的位置设置的I层118i、N层118n之间,与N层118n相比杂质浓度低的区域是低杂质浓度区域218n形成的区域。The protection circuit element 281 shown in FIG. 5 is mainly composed of a PIN diode 281a and a floating electrode 118g. Therefore, it is characterized in that between the I layer 118i and the N layer 118n provided at the position overlapping the semiconductor film 118s of the PIN diode 281a and the floating electrode 118g, the region with a lower impurity concentration than the N layer 118n is a low impurity region. Concentration region 218n forms the region.

图12是将根据本实施方式的保护电路元件的电压-电流特性和根据第一实施方式的保护电路元件的比较的图。另外,横轴是施加电压,纵轴是电流。图中的实线表示根据在I层、N层间没有低浓度区域的第一实施方式的保护元件的特性,虚线表示根据在I层、N层之间具有低浓度区域的第二实施方式的保护元件的特性。根据该图,虚线延伸到15V以上,由此可以看出本实施方式的保护电路元件的耐压提高了。在这样的PIN二极管的I层、N层间或I层、P层间设有低浓度杂质区域。保护电路元件的耐压变高的同时,保护电路的耐压增加,可靠性更高。FIG. 12 is a graph comparing the voltage-current characteristics of the protection circuit element according to the present embodiment and the protection circuit element according to the first embodiment. In addition, the horizontal axis represents the applied voltage, and the vertical axis represents the current. The solid line in the figure represents the characteristics of the protective element according to the first embodiment in which there is no low-concentration region between the I layer and the N layer, and the broken line represents the characteristic according to the second embodiment in which there is a low-concentration region between the I layer and the N layer. Characteristics of protective components. According to the figure, the dotted line extends to 15 V or more, and it can be seen that the withstand voltage of the protection circuit element of this embodiment is improved. A low-concentration impurity region is provided between the I layer and the N layer or between the I layer and the P layer of such a PIN diode. While the withstand voltage of the protection circuit element becomes higher, the withstand voltage of the protection circuit increases and the reliability is higher.

这样,在用于像素开关元件和驱动电路的TFT中,为抑制因在栅极绝缘膜中注入热载流子而使电气特性(阈值Vth、转移电导gm、漏极电流Ids等)变动,采用在漏极近旁设置高电阻层的LDD(Lightly Doped Drain)结构,以缓和沟道边界的电场。因此,如本实施方式相关的PIN二极管218n,通过做成在I层118i和N层118n之间设置低浓度杂质区域(高电阻区域)218n的结构,同先前的第一实施方式涉及的保护电路元件181一样,能够容易地与内部电路TFT以相同的工序形成。In this way, in TFTs used for pixel switching elements and driving circuits, in order to suppress fluctuations in electrical characteristics (threshold value V th , transfer conductance gm, drain current I ds, etc.) due to injection of hot carriers into the gate insulating film , using a LDD (Lightly Doped Drain) structure with a high-resistance layer near the drain to ease the electric field at the channel boundary. Therefore, the PIN diode 218n according to this embodiment has a structure in which a low-concentration impurity region (high resistance region) 218n is provided between the I layer 118i and the N layer 118n. Like the element 181, it can be easily formed in the same process as the internal circuit TFT.

〔第三实施方式〕[Third Embodiment]

接下来,说明有关本发明的第3实施方式。图6是第三实施方式相关的薄膜半导体装置所具备的保护电路元件的概略剖视图。图6是相当于先前的第一实施方式的图2(b)的图,本实施方式相关的保护电路元件381的平面结构同图2(a)所示的保护电路元件181的基本相同。Next, a third embodiment of the present invention will be described. 6 is a schematic cross-sectional view of a protection circuit element included in the thin film semiconductor device according to the third embodiment. FIG. 6 is a diagram corresponding to FIG. 2( b ) of the previous first embodiment, and the planar structure of the protection circuit element 381 according to this embodiment is basically the same as that of the protection circuit element 181 shown in FIG. 2( a ).

图6所示的保护电路元件381以PIN二极管381a和浮置电极118g作为主体构成。设置于同PIN二极管381a的半导体膜118s和浮置电极118g平面上重合的位置的I层118i、与N层118n之间,与N层118n相比杂质浓度低的区域是低杂质浓度区域318n形成的区域,同图5所示的PIN二极管281a一样。在本实施方式相关的PIN二极管381a中,低浓度杂质区域318n在同浮置电极118g平面上重合的位置形成。The protection circuit element 381 shown in FIG. 6 is mainly composed of a PIN diode 381a and a floating electrode 118g. Between the I-layer 118i and the N-layer 118n, which are provided on the same plane as the semiconductor film 118s and the floating electrode 118g of the PIN diode 381a, a region with a lower impurity concentration than the N-layer 118n is formed as a low-impurity-concentration region 318n. The region is the same as the PIN diode 281a shown in FIG. 5 . In the PIN diode 381a according to this embodiment, the low-concentration impurity region 318n is formed at a position overlapping the plane of the floating electrode 118g.

这样的保护电路元件381的结构,成为具有所谓GOLDD(GateOverlapped Lightly Doped Drain)结构的TFT的类似结构。从而,构成内部电路的TFT,对于是具有这种GOLDD结构情况下,即使对于构成保护电路元件的PIN二极管381a,若做成如本实施方式的低浓度杂质区域318n以同浮置电极平面上重合地配置的结构,也能够容易地同内部电路以相同的工序形成保护电路元件,并且也能够形成同第二实施方式同样的高耐压的PIN二极管。The structure of such a protection circuit element 381 is a structure similar to a TFT having a so-called GOLDD (Gate Overlapped Lightly Doped Drain) structure. Therefore, when the TFT constituting the internal circuit has such a GOLDD structure, even for the PIN diode 381a constituting the protection circuit element, if the low-concentration impurity region 318n in this embodiment is made so as to overlap the floating electrode plane, Even in the structure arranged in the ground, it is possible to easily form the protection circuit element in the same process as the internal circuit, and it is also possible to form the same high withstand voltage PIN diode as in the second embodiment.

另外,对于形成GOLDD结构的情况,通过两层结构的金属膜形成诸如栅极电极,同时该栅极的上层侧(半导体膜的相反侧)金属膜的面积比下层侧的金属膜狭窄的结构,将相关的栅极电极作为掩模向半导体膜导入杂质。那样的话,对应于上述下层侧的金属膜相对上层侧的金属膜伸出的区域,低浓度杂质区域在半导体膜上自匹配地形成。In addition, in the case of forming a GOLDD structure, a structure such as a gate electrode is formed by a metal film of a two-layer structure, and the area of the metal film on the upper layer side (opposite side of the semiconductor film) of the gate is narrower than that of the metal film on the lower layer side, Impurities are introduced into the semiconductor film using the associated gate electrode as a mask. In this case, a low-concentration impurity region is formed on the semiconductor film in a self-aligning manner corresponding to the region where the metal film on the lower layer side protrudes from the metal film on the upper layer side.

因此,即使制造本实施方式的保护电路元件381时,也能够将浮置电极118g做成和上述GOLDD结构TFT的栅极电极同样的两层结构。通过向N层118n中进行杂质导入,能够做到在浮置电极118g的平面区域形成低浓度杂质区域318n。Therefore, even when the protective circuit element 381 of this embodiment is manufactured, the floating electrode 118g can have the same two-layer structure as the gate electrode of the above-mentioned GOLDD structure TFT. By introducing impurities into the N layer 118n, it is possible to form the low-concentration impurity region 318n in the planar region of the floating electrode 118g.

〔第四实施方式〕[Fourth Embodiment]

接下来,说明关于本发明的第四实施方式。图7是第四实施方式相关的薄膜半导体装置所具备的保护电路元件的概略剖视图。图7是相当于先前的第一实施方式的图2(b)的图,本实施方式相关的保护电路元件481的平面结构同图2(a)所示的保护电路元件181的基本相同。Next, a fourth embodiment of the present invention will be described. 7 is a schematic cross-sectional view of a protective circuit element included in a thin film semiconductor device according to a fourth embodiment. FIG. 7 is a diagram corresponding to FIG. 2( b ) of the previous first embodiment, and the planar structure of the protection circuit element 481 according to this embodiment is basically the same as that of the protection circuit element 181 shown in FIG. 2( a ).

图7所示的保护电路元件481以PIN二极管481a和浮置电极118g作为主体构成。I层118i设置于PIN二极管481a的半导体膜118s和浮置电极118g平面上重合的位置,这一点同先前的第一至第三实施方式一样。本实施方式中,N层118n伸出到浮置电极118g和半导体膜118s平面上重合的区域,这与其他实施方式不同。即使采用具有这种N层伸出部分418n的PIN二极管481a,也能够得到与先前的实施方式同样的结果。另外,即使浮置电极118g延伸到,第二、第三实施方式所示的P层118p、I层118i、或N层118n、I层118i之间具有低浓度杂质区域218n、318n的PIN二极管的P层118p或N层118n,表面也具有同样的高耐压,能够提供对逆向浪涌电压具有保护功能的保护电路元件。The protection circuit element 481 shown in FIG. 7 is mainly composed of a PIN diode 481a and a floating electrode 118g. The I layer 118i is provided at a position where the semiconductor film 118s of the PIN diode 481a overlaps with the floating electrode 118g on the plane, as in the previous first to third embodiments. In the present embodiment, the N layer 118n protrudes to the overlapping region of the floating electrode 118g and the semiconductor film 118s on the plane, which is different from the other embodiments. Even if the PIN diode 481a having such an N-layer overhang 418n is used, the same result as in the previous embodiment can be obtained. In addition, even if the floating electrode 118g extends to the PIN diode shown in the second and third embodiments, the PIN diode having the low-concentration impurity regions 218n and 318n between the P layer 118p and the I layer 118i, or the N layer 118n and the I layer 118i The surface of the P layer 118p or N layer 118n also has the same high withstand voltage, and can provide a protective circuit element with a protective function against reverse surge voltage.

在以前的第一至第三实施方式中,说明将与半导体膜118s的一部分平面上重合配置的浮置电极118g作为掩模,使用半导体膜中导入杂质的情况,在构成内部电路的TFT的形成工序中,没有必要采用必须自匹配地形成沟道区域方法。例如,也可以将在栅极绝缘膜上形成图案的光刻胶作为掩模进行向半导体膜导入杂质,在这种情况下,成为导入杂质后形成栅极电极,可以采用栅极电极和杂质导入区域(例如,漏极区域)一部分平面上重合的结构。从而,对于将相关的结构作为内部电路形成的情况,作为保护电路元件,使用具有本实施方式的PIN二极管481a的器件,制造工序的共通化这一点是有效的。In the previous first to third embodiments, the floating electrode 118g arranged to overlap a part of the semiconductor film 118s on the plane is used as a mask, and the case of introducing impurities into the semiconductor film is used to describe the formation of the TFT constituting the internal circuit. In the process, it is not necessary to adopt a method of forming the channel region in a self-aligning manner. For example, the photoresist patterned on the gate insulating film can also be used as a mask to introduce impurities into the semiconductor film. In this case, the gate electrode is formed after the introduction of impurities. A structure in which a portion of a region (for example, a drain region) overlaps in plane. Therefore, when the related structure is formed as an internal circuit, it is effective to use a device including the PIN diode 481 a of the present embodiment as a protection circuit element and to commonize the manufacturing process.

〔电子机器〕〔Electronic equipment〕

接下来,说明关于具有本发明的上述实施方式的液晶显示装置的电子机器的具体例子。Next, specific examples of electronic equipment including the liquid crystal display device according to the above-mentioned embodiment of the present invention will be described.

图8是作为便携电话机一例的立体图。在图8中,符号1300表示便携电话机主体,符号1301表示使用上述液晶显示装置的显示部。符号1302是操作部,1303、1304分别是接受部和发送部。Fig. 8 is a perspective view of an example of a mobile phone. In FIG. 8, reference numeral 1300 denotes a mobile phone main body, and reference numeral 1301 denotes a display unit using the above-mentioned liquid crystal display device. Reference numeral 1302 is an operating unit, and 1303 and 1304 are a receiving unit and a transmitting unit, respectively.

图8所示的电子器械,由于具有使用上述实施形态的液晶显示装置的显示部,能够实现具备高可靠性和长寿命的液晶显示部。The electronic device shown in FIG. 8 has a display unit using the liquid crystal display device of the above-mentioned embodiment, and can realize a liquid crystal display unit having high reliability and long life.

另外,本发明的技术范围不限于上述实施方式的限定,可在不脱离本发明主旨的范围内作各种变形。例如,本发明也适用于使用有源矩阵基板的电光学装置,不仅是液晶显示装置,也能够适用于有机EL显示器等电流驱动型发光装置。另外,对于数据线驱动电路、扫描线驱动电路等的周边电路的配置,不限于上述方式,也可能进行适当的变形。In addition, the technical scope of the present invention is not limited to the limitations of the above-mentioned embodiments, and various modifications can be made without departing from the gist of the present invention. For example, the present invention is also applicable to electro-optical devices using active matrix substrates, not only liquid crystal display devices but also current-driven light-emitting devices such as organic EL displays. In addition, the arrangement of peripheral circuits such as the data line driving circuit and the scanning line driving circuit is not limited to the above-mentioned configuration, and appropriate modifications may be made.

Claims (14)

1. a thin film semiconductor device is the thin film semiconductor device that comprises matrix and be formed at the semiconductor film on this matrix, it is characterized in that,
Be provided with on the described matrix have the main circuit portion of semiconductor element, by this extended portion of terminal of main circuit portion, insert in the protective circuit portion between described main circuit portion and the described portion of terminal;
Described protective circuit portion is provided with the protective circuit element,
Described protective circuit element comprises: have the PIN diode of described semiconductor film, and between the floating electrode of the relative configuration of I layer of dielectric film and this PIN diode.
2. thin film semiconductor device according to claim 1 is characterized in that,
Constituting the semiconductor film of described PIN diode and the semiconductor film of the semiconductor element of the described main circuit of formation portion is the semiconductor film that the same one deck on described matrix forms.
3. thin film semiconductor device according to claim 2 is characterized in that,
The semiconductor element that described main circuit portion is had is a thin-film transistor,
The conducting film that constitutes the conducting film of described floating electrode and constitute the gate electrode of described thin-film transistor is formed on the same one deck on the described matrix.
4. according to each the described thin film semiconductor device in the claim 1~3, it is characterized in that,
The I layer of described floating electrode and described PIN diode is formed on the rough same position when overlooking.
5. according to each the described thin film semiconductor device in the claim 1~3, it is characterized in that,
Described PIN diode is to have the low concentration impurity zone lower than this P layer impurity concentration between its P layer and I layer, perhaps, has the low concentration impurity zone lower than N layer impurity concentration between N layer and I layer.
6. thin film semiconductor device according to claim 5 is characterized in that,
Described low concentration impurity zone be formed on described floating electrode plane in the zone that overlaps.
7. according to each the described thin film semiconductor device in the claim 1~3, it is characterized in that,
Described PIN diode and floating electrode between the relative configuration of dielectric film have and the part of the P layer of described PIN diode or N layer superposed part in the plane.
8. according to each the described thin film semiconductor device in the claim 1~3, it is characterized in that,
Described protective circuit element directly is connected with described portion of terminal.
9. the manufacture method of a thin film semiconductor device is the manufacture method that has matrix and be formed at the thin film semiconductor device of the semiconductor film on this matrix, it is characterized in that,
Described thin film semiconductor device be provided with on the matrix have the main circuit portion of semiconductor element, by this extended portion of terminal of main circuit portion, insert in the protective circuit portion between described main circuit portion and the described portion of terminal,
The operation that forms described protective circuit portion comprises: the protective circuit element forms operation,
Described protective circuit element forms operation and comprises:
On the semiconductor film that is formed on the matrix, form the operation of dielectric film;
By form on the described dielectric film conductive film pattern form with described semiconductor film plane on the operation of the floating electrode that overlaps;
By described floating electrode is imported impurity as mask in described semiconductor film, on this semiconductor film, form P layer, N layer and I layer, to form the operation of PIN diode.
10. the manufacture method of thin film semiconductor device according to claim 9 is characterized in that,
Described main circuit portion has thin-film transistor, this thin-film transistor contain comprise semiconductor film and in this semiconductor film between the relative gate electrode of dielectric film;
In same operation, form semiconductor film that constitutes described thin-film transistor and the semiconductor film that constitutes described protective circuit element; And
In same operation, form gate electrode that constitutes described thin-film transistor and the floating electrode that constitutes described protective circuit element.
11. the manufacture method of thin film semiconductor device according to claim 10 is characterized in that,
Import operation by same impurity and form the source electrode of described thin-film transistor and the P layer of described PIN diode, the perhaps drain electrode of described thin-film transistor and N layer.
12. the manufacture method of thin film semiconductor device according to claim 11 is characterized in that,
Import in the operation at described impurity, in the semiconductor film of the semiconductor film of described thin-film transistor and described protective circuit element, the low concentration impurity field that the impurity concentration of the impurity ingress area that connects near can forming is low.
13. an electro-optical device is characterized in that,
Contain each the described thin film semiconductor device in the claim 1~8.
14. an e-machine is characterized in that,
Contain the described electro-optical device of claim 13.
CNB2005100860668A 2004-07-23 2005-07-19 Thin film semiconductor device and method of manufacturing the same, electro-optical device, and electronic apparatus Expired - Fee Related CN100454553C (en)

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JP5000650B2 (en) * 2006-06-30 2012-08-15 シャープ株式会社 TFT substrate, display panel including the same, display device, and method for manufacturing TFT substrate
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1165568A (en) * 1995-10-03 1997-11-19 精工爱普生株式会社 Active Matrix Substrate
JP2002033454A (en) * 2000-07-17 2002-01-31 Nec Miyagi Ltd Semiconductor integrated circuit
CN1435883A (en) * 2002-01-30 2003-08-13 联华电子股份有限公司 Electrostatic discharge protection circuit of non-gated diode element and manufacturing method thereof
WO2004019123A1 (en) * 2002-08-24 2004-03-04 Koninklijke Philips Electronics N.V. Manufacture of electronic devices comprising thin-film circuit elements

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1165568A (en) * 1995-10-03 1997-11-19 精工爱普生株式会社 Active Matrix Substrate
JP2002033454A (en) * 2000-07-17 2002-01-31 Nec Miyagi Ltd Semiconductor integrated circuit
CN1435883A (en) * 2002-01-30 2003-08-13 联华电子股份有限公司 Electrostatic discharge protection circuit of non-gated diode element and manufacturing method thereof
WO2004019123A1 (en) * 2002-08-24 2004-03-04 Koninklijke Philips Electronics N.V. Manufacture of electronic devices comprising thin-film circuit elements

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