CN100459044C - Method for forming nano single crystal silicon and making method of non volatile semiconductor memory - Google Patents

Abstract

A method for the formation of nanometer mono-crystalline silicon includes the following technical steps: form silicate-rich medium thin film layer on a semiconductor base; transplant silicate ion into the silicate-rich medium thin film layer; make anneal treatment on the semiconductor base, and form nanometer mono-crystalline silicon on the silicate-rich medium thin film layer. The silicate-rich medium thin film is silicate-rich oxide or silicate-rich nitrogen-oxide, with the temperature being 700 to 1,000 DEG C. The intensity of nanometer mono-crystalline silicon produced with the method is between 1 is multiplied by 1010/cm2 and 1 is multiplied by 1012/cm2, and the quantity of nanometer particles and crystal grain size can be controlled according to needs. The anneal temperature from 700 to 1,000 DEG C renders low heating budget, thus lowering energy consumption and production cost. The invention also provides a method of non-volatile semiconductor memorizer containing nanometer mono-crystalline silicon floating grid.

Description

Manufacturing method of non-volatile semiconductor memory

technical field

The invention relates to a method for forming a nanometer single crystal silicon layer and a method for manufacturing a semiconductor device. Specifically, the present invention relates to a method for epitaxially growing a nano-single-crystal silicon layer on an insulating substrate and a method for manufacturing a non-volatile semiconductor storage device containing a nano-single-crystal silicon floating gate.

Background technique

Non-volatile memory such as erasable programmable read-only memory (electrically programmable read-only memory, EPROM), electrically erasable programmable read-only memory (electrically-erasable programmable read-only memory, EEPROM) and flash memory (flash memory) It is currently widely used as a data storage device for computer systems. These non-volatile memories usually include a large number of gates with electrical insulation properties, which are commonly referred to as floating gates. Nano-single crystal silicon floating gates have attracted extensive attention due to their fast programming capability, low power consumption, high endurance, and high density uniformity.

Due to the superior physical properties of nano-single crystal silicon, such as electron confinement, photoluminescence and electron emission, its preparation methods have also been developed to a certain extent. For example, US Patent Application Publication No. US20050048796 provides a process for forming nanometer single crystal silicon. The specific process steps are as follows: the first step is to treat the surface of the substrate with hydrogen atom groups, and the hydrogen atom groups are obtained by plasma deposition of hydrogen gas; Single crystal silicon with particle size below 10nm, the silicon-containing gas can be a mixed gas of SiH4 or Si2H6 and hydrogen; the third step, by using one of oxygen, oxygen atoms or nitrogen atoms, the single crystal silicon Atoms are connected by oxygen or nitrogen atoms. The above three steps can be performed cyclically until the set thickness of nanometer single crystal silicon is reached. However, it is difficult to control the size and shape of each nano-single-crystal silicon grain in the above-mentioned method, and it is also difficult to control the density of the formed nano-single-crystal silicon.

Another common method for forming nano-single-crystal silicon is the annealing method, which mainly uses high chemical equivalent amorphous silicon nitride film deposition to form nano-single-crystal silicon particles. For example, the US Patent No. 6774061 patent solution provides a method for forming nano-single crystal silicon. The specific process is: forming a silicon dioxide layer on the silicon substrate; forming an exposed mask layer on the silicon dioxide layer; Forming at least one opening on the mask layer; implanting silicon ions into the silicon dioxide layer through the at least one opening on the mask layer, the ion implantation energy is 0.1-7keV; The semiconductor substrate is annealed, so that the implanted silicon ions become orderly distributed nanometer single crystal silicon. However, this method is also difficult to control the size of each nano-single-crystal silicon grain, and it is also difficult to control the quantity of formed nano-single-crystal silicon.

Because the method for forming nanometer single crystal silicon cannot effectively control the quantity, size and shape of nanometer single crystal silicon, therefore, when using the nanometer single crystal silicon prepared by the above method as the floating gate of the non-volatile memory, the programming speed of the memory and Data retention is difficult to improve at the same time.

Contents of the invention

The problem to be solved by the present invention is to provide a method for forming nano-silicon, which can effectively control the quantity and size of nano-silicon grains formed, aiming at the defects in the formation process of nano-single-crystal silicon in the prior art. The invention also provides a method for a non-volatile semiconductor storage device containing a nanometer single-crystal silicon floating gate.

The present invention is achieved through the following technical solutions: a method for forming nano-silicon, the specific process steps are:

Forming a silicon-rich dielectric film layer on a semiconductor substrate;

Implanting silicon ions into the silicon-rich dielectric film layer;

Annealing is performed on the semiconductor substrate to form nanometer single crystal silicon in the silicon-rich dielectric thin film layer.

The semiconductor substrate may be silicon or silicon-on-insulator (SOI).

The silicon-rich dielectric film layer may be silicon-rich oxide _SiOx (0<X<2) or silicon-rich _{oxynitride SiOxNy} (0<X<1, 0<Y<1).

The refractive index of the silicon-rich dielectric film layer is 1.48 to 1.98.

Silicon ion implantation adopts the method of ion vertical implantation, and the density of silicon ions in the environment is 1×10 ¹⁴ to 1×10 ¹⁶ /cm ² , preferably 4×10 ¹⁵ to 1×10 ¹⁶ /cm 2 . cm ² , the ion implantation energy is 50 to 300keV, more preferably 100 to 120keV.

Annealing the semiconductor substrate in NH ₃ , N ₂ , H ₂ or Ar atmosphere, the annealing temperature is between 700 and 1000°C, which can decompose the atoms in the silicon-rich dielectric layer into nano single crystal Si and silicon oxide Or in the form of silicon oxynitride.

According to the content of silicon atoms in the silicon-rich medium used and the density of implanted silicon ions, the density of nano single crystal silicon atoms formed after annealing is between 1x10 ¹⁰ /cm ² and 1x10 ¹² /cm ² , The particle diameter is between 1 and 10 nm.

The temperature for annealing the semiconductor substrate should be strictly controlled between 700 and 1000°C. In the above temperature range, it is easier to form nanometer single crystal silicon and has a lower thermal budget.

On the other hand, the present invention provides the method that contains the non-volatile semiconductor memory of nano single crystal silicon floating gate, and this method comprises the following steps:

forming a trench isolation structure on the semiconductor substrate;

Form an oxide layer on the substrate;

Forming a polysilicon layer and a nanometer monocrystalline silicon floating gate on the above-mentioned oxide layer;

Etching the above-mentioned polysilicon layer, nano single crystal silicon floating gate and oxide layer to form a control gate;

Forming a drain source region in a semiconductor substrate;

Forming a nitride or oxynitride isolation layer on the control gate;

An interlayer dielectric layer is deposited on the isolation layer and forms the contacts to the circuits within the memory.

The aforementioned oxide layer is a tunnel gate oxide layer, and the oxide material is silicon oxynitride (SiON), silicon-rich oxide (SRO), HfO ₂ , Al ₂ O ₃ or SiN.

The process method for forming a polysilicon layer and a nano-single-crystal silicon floating gate on the oxide layer is as follows:

Depositing a silicon-rich dielectric film on the oxide layer;

Depositing a polysilicon layer on the silicon-rich dielectric film layer;

Implanting silicon ions into the silicon-rich dielectric film layer through the polysilicon layer;

Annealing is performed on the semiconductor substrate to form nanometer single crystal silicon in the silicon-rich dielectric thin film layer.

The silicon-rich dielectric film layer may be silicon-rich oxide _SiOx (0<X<2) or silicon-rich _{oxynitride SiOxNy} (0<X<1, 0<Y<1).

The refractive index of the silicon-rich dielectric film layer is 1.48 to 1.98, preferably 1.58 to 1.80.

The density of silicon ions in the environment during the silicon ion implantation is 1×10 ¹⁴ to 1×10 ¹⁶ /cm ² , preferably 4×10 ¹⁵ to 1×10 ¹⁶ /cm ² .

The energy of the aforementioned silicon ion implantation is 50 to 300 keV, preferably 100 to 120 keV.

According to the method of the non-volatile semiconductor storage device containing nano-single crystal silicon floating gate according to claim 20, it is characterized in that the energy of silicon ion implantation is .

The annealing temperature for annealing the semiconductor substrate is 700 to 1000°C.

After annealing the semiconductor substrate, the density of nano-single crystal silicon atoms formed in the silicon-rich dielectric thin film layer is 1x10 ¹⁰ /cm ² to 1x10 ¹² /cm ² .

In the above-mentioned method of non-volatile semiconductor memory containing nano-silicon floating gate, the process of etching the above-mentioned polysilicon layer, nano-silicon floating gate and oxide layer to form a control gate is as follows: depositing silicon oxynitride anti-reflection medium on the polysilicon layer Electric coating, and spray photoresist, exposure and development, define the position of the control gate, and then remove the silicon nitride oxide anti-reflective dielectric coating layer, polysilicon layer, silicon-rich dielectric film layer and tunnel gate outside the control gate oxide layer.

After the control gate is formed, the number of nano single crystal silicon particles contained in each nano single crystal silicon floating gate contained in each control gate is 1 to 100, and the particle diameter is 1 nm to 10 nm.

In the above-mentioned method of the non-volatile semiconductor memory containing the nano-single-crystal silicon floating gate, the isolation layer formed is nitride or oxynitride.

In the method of the above-mentioned non-volatile semiconductor storage device containing nano single crystal silicon floating gate, the interlayer dielectric layer is high-density plasma phosphosilicate glass (HDP PSG) or borophosphosilicate glass (BPSG).

In the method for the above-mentioned non-volatile semiconductor storage device containing nano single-crystal silicon floating gate, the contact is metal tungsten or polysilicon.

Compared with the prior art, the present invention has the following advantages:

1. The method for forming nano-silicon single crystal silicon provided by the present invention, because the quantity of silicon atoms in the silicon-rich dielectric film can be controlled by adjusting the process parameters for forming the silicon-rich dielectric film, and then implanted in the silicon-rich dielectric film Silicon ions, the density of implanted silicon ions can also be determined by adjusting the density of silicon ions in the environment when implanting silicon ions. Therefore, the number of nano single crystal silicon atoms generated by the method for forming nano single crystal silicon provided by the invention More, the density is between 1x10 ¹⁰ /cm ² and 1x10 ¹² /cm ² , and the number of nanoparticles can be controlled. At the same time, the diameter of the grown nano-single crystal silicon is between 1 and 10nm, and the shape is spherical.

2. The present invention performs annealing within the temperature range of 700 to 1000°C. Compared with the process in which the annealing temperature must be greater than 1050°C in the prior art, the annealing temperature is significantly lower, has a lower thermal budget, and reduces energy consumption and production cost; and, since the content of silicon atoms in the silicon-rich dielectric film is relatively high before annealing, nanometer single crystal silicon can be easily formed within the temperature range of the present invention.

3. The nano-single crystal silicon floating gate prepared by the method provided by the present invention has the advantages of easy control of the size of the nano-single crystal silicon crystal grain, high density, etc., and has a large data storage capacity, and the data will not be lost when the power is turned off.

Description of drawings

Fig. 1 is a schematic cross-sectional structure diagram of forming a silicon-rich dielectric film layer on the surface of a semiconductor substrate in the method for forming nano-single-crystal silicon provided by the present invention.

Fig. 2 is a schematic cross-sectional structure diagram of a semiconductor substrate after silicon ions are implanted into a silicon-rich dielectric thin film layer in the method for forming nano-silicon single crystal provided by the present invention.

Fig. 3 is a schematic cross-sectional structure diagram of forming nano-single-crystal silicon in the silicon-rich dielectric film layer after the annealing of the semiconductor substrate in the method for forming nano-single-crystal silicon provided by the present invention.

FIG. 4 is a schematic cross-sectional structure diagram of a semiconductor substrate after forming an insulating isolation layer in the method for forming a non-volatile semiconductor memory provided by the present invention.

5 is a schematic cross-sectional structure diagram after forming a high-K value tunnel gate oxide layer on the surface of a semiconductor substrate in the method for forming a non-volatile semiconductor memory provided by the present invention.

Fig. 6 is a schematic cross-sectional structure diagram of forming a silicon-rich dielectric thin film layer, a polysilicon oxide layer, and implanting silicon ions on the surface of a semiconductor substrate in the method for forming a non-volatile semiconductor memory provided by the present invention.

Fig. 7 is a schematic cross-sectional structure diagram of nano-single-crystal silicon formed by annealing in the silicon-rich dielectric thin film layer in the semiconductor substrate in the method for forming the non-volatile semiconductor memory provided by the present invention.

Fig. 8 is a schematic cross-sectional structure diagram after etching a polysilicon layer, a nano-single crystal silicon floating gate and an oxide layer to form a control gate in the method for forming a non-volatile semiconductor memory provided by the present invention.

FIG. 9 is a schematic cross-sectional structure diagram after forming a drain-source region in a semiconductor substrate in the method for forming a non-volatile semiconductor memory provided by the present invention.

FIG. 10 is a schematic cross-sectional structure diagram after forming a nitride or oxynitride isolation region in the method for forming a non-volatile semiconductor memory provided by the present invention.

FIG. 11 is a schematic cross-sectional view of the formation of the interlayer conductive layer and contacts in the method for forming the non-volatile semiconductor memory provided by the present invention.

Detailed ways

The specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

Example 1

The invention provides a method for forming nano-silicon single crystal. The specific process steps are: 1) forming a silicon-rich dielectric thin film layer on a semiconductor substrate; 2) implanting silicon ions into the silicon-rich dielectric thin film layer; The substrate is annealed.

Referring to FIG. 1 , it is a schematic cross-sectional structure diagram after forming a silicon-rich dielectric thin film layer 102 on a semiconductor substrate 101 . The semiconductor base 101 shown in FIG. 1 is silicon, and silicon-on-insulator (SOI) may also be used as the semiconductor base 101 . The silicon-rich dielectric film layer 102 shown in FIG. 1 can be silicon-rich oxide SiO _x (0<X<2) or silicon-rich oxynitride SiO _x N _y (0<X<1, 0<Y<1 ). The content of silicon atoms in the silicon-rich oxide _SiOx (0<X<2) and silicon-rich _{oxynitride SiOxNy} (0<X<1, 0<Y<1) can be controlled by controlling the rich The formation process of the silicon dielectric thin film layer 102 is controlled.

The formation process of the silicon-rich oxide _SiOx (0<X<2) in the present invention can be prepared by any method known to those skilled in the art. As a preferred embodiment, the present invention provides a process for forming a silicon-rich oxide _SiOx (0<X<2) thin film layer.

Using N ₂ O and SiH ₄ as reaction raw materials to deposit silicon-rich oxide SiO _x (0<X<2) dielectric film layer, the overall reaction formula of the chemical reaction is:

SiH ₄ +N ₂ O→SiO _x +H ₂ +H ₂ O+volatile matter

The above reaction can be carried out in plasma atmosphere and N ₂ , He or Ar atmosphere. The plasma atmosphere includes silicon ions (Si ⁺ ), hydrogen ions (H ⁺ ), and oxygen ions (O ⁻ ) or an electron atmosphere and the like. Using existing plasma-enhanced chemical vapor deposition equipment (PECVD) well known to those skilled in the art, in _N atmosphere, silicon substrate is placed in the reaction chamber, while maintaining the flow of _N in the reaction chamber under the condition of 400 to 2000 sccm, 300 to 1200 sccm of N ₂ O gas and 50 to 200 sccm of SiH ₄ gas are fed, the pressure in the reaction chamber is 1.0 to 5 torr, the radio frequency power is 50 to 250 watts (watt), and the temperature is 300 to 400 ° C. In some cases, the silicon-rich oxide SiO _x thin film layer can be formed by reacting for 1 to 20 seconds (sec).

The refractive index of the silicon-rich oxide SiO _x (0<X<2) dielectric thin film layer prepared by the above method is 1.48 to 1.98, and a more preferable range is 1.58 to 1.80. The magnitude of the refractive index reflects the concentration of silicon atoms in the silicon-rich medium. Generally, the greater the concentration of silicon in the silicon-rich medium, the higher the refractive index of the film.

In a more preferred embodiment, the plasma enhanced chemical vapor deposition equipment is used, the silicon substrate is placed in the reaction chamber, and in the _N atmosphere, the flow of _N in the reaction chamber is maintained at 1600 sccm. The flow rate of N ₂ O is 70 sccm, the flow rate of SiH ₄ is 115 sccm, the pressure in the reaction chamber is 5 torr, the radio frequency power is 135 watt, and the temperature is 400° C. for 15 sec. The refractive index of the prepared silicon-rich oxide SiO _x film layer is 1.80.

The formation process of the silicon-rich oxynitride SiO _x N _y (0<X<1, 0<Y<1) dielectric film layer in the present invention can also be prepared by any method known to those skilled in the art. As a preferred embodiment, the present invention provides a process for forming a silicon-rich oxynitride SiO _x N _y (0<X<1, 0<Y<1) dielectric film layer.

When the silicon-rich dielectric thin film layer used is silicon-rich oxynitride SiO _x N _y (0<X<1, 0<Y<1) dielectric thin film layer, N ₂ O and SiH ₄ are generally used as reaction raw materials, chemical The overall reaction formula is:

SiH ₄ +N ₂ O→SiO _X N _Y +H ₂ +H ₂ O+volatile matter

The above reaction can be carried out under N ₂ , He or Ar atmosphere. Using the existing plasma-enhanced chemical vapor deposition equipment well known to those skilled in the art, under the Ar atmosphere, the silicon substrate is placed in the reaction chamber, while maintaining the flow rate of Ar in the reaction chamber as 3000 to 5000sccm, feed 50 to 150sccm N ₂ O and 50 to 200 sccm of SiH ₄ , under the conditions of the pressure in the reaction chamber of 2.0 to 10torr, the radio frequency power of 80 to 230 watts, and the temperature of 300 to 400 ° C for 1 to 20 sec, can generate Silicon-rich oxynitride SiO _x N _y (0<X<1, 0<Y<1) dielectric film layer.

The refractive index of the silicon-rich oxynitride SiO _x N _y (0<X<1, 0<Y<1) dielectric film layer prepared by the above method is 1.48 to 1.98, and the preferred range is 1.58 to 1.80.

In a more preferred embodiment, adopt plasma-enhanced chemical vapor deposition equipment, feed N in the reverse chamber The flow of ₂ is 3800 sccm, the flow of N ₂ O that feeds is 70 sccm, the flow of SiH ₄ is 115 sccm, in the reaction chamber The pressure is 5 torr, the radio frequency power is 135 watt, and the temperature is 400°C for 15 sec, and the refractive index of the formed silicon-rich oxynitride dielectric film layer is 1.60.

The higher the concentration of silicon in the silicon-rich dielectric thin film layer provided by the present invention, the greater the control of the density of silicon atoms in the nanometer single crystal silicon formed later.

Referring to FIG. 2 , silicon ions are directly implanted into the silicon-rich dielectric film layer 102 . Silicon ions can be implanted vertically, and the density of silicon ions in the environment is 1×10 ¹⁴ to 1×10 ¹⁶ /cm ² , preferably 4×10 ¹⁵ to 1×10 ¹⁶ /cm ² , the ion implantation energy is 50 to 300 keV, more preferably 100 to 120 keV.

Implanting silicon ions into the silicon-rich dielectric thin film layer can increase the silicon content in the silicon-rich dielectric thin film layer, and the implanted silicon ion content can be better controlled by ion implantation, so that the subsequent The quantity of nano single crystal silicon formed in the silicon dielectric thin film layer is effectively controlled.

Referring to FIG. 3 , annealing the semiconductor substrate 101 at 700 to 1000° C. can generate nano-single crystal silicon 103 in the silicon-rich dielectric film layer 102 with controllable quantity, size and shape.

In a specific embodiment, the semiconductor substrate is annealed in NH ₃ , N ₂ , H ₂ or Ar atmosphere, and the annealing temperature is 700 to 1000° C., so that the silicon-rich oxide or rich silicon in the silicon-rich dielectric film layer Silicon oxynitride atoms can be decomposed into nano single crystal silicon and silicon oxide SiO _x (or SiO _x N _y ) with controllable size, shape and quantity, and the density of nano single crystal silicon atoms is 1x10 ¹⁰ /cm ² to 1x10 ¹² /cm ² . It can be seen from Fig. 3 that after annealing, the nano-single-crystal silicon atoms are evenly distributed in the silicon-rich dielectric film layer, the shape is spherical, and the diameter of the silicon atoms is 1 to 10 nm.

The annealing temperature for the semiconductor substrate should be maintained at 700 to 1000° C. Compared with the process in the prior art where the annealing temperature must be greater than 1050° C., the annealing temperature is significantly lower. This is because the present invention firstly adopts the silicon-rich dielectric film, which contains a relatively high content of silicon atoms, and then implants a controlled amount of silicon ions through the ion implantation process. Therefore, the silicon ion content in the silicon-rich dielectric film It becomes higher, and after annealing at 700 to 1000°C, nano-single-crystal silicon can be easily formed, and the quantity, shape and size of nano-single-crystal silicon can be easily controlled.

The invention adopts relatively low annealing temperature, has low thermal budget, and reduces energy consumption and production cost.

The nano single crystal silicon prepared by the above method can be used as a floating gate of a non-volatile storage device, and can also be used to make an active layer of a nano light emitting device.

Example 2

The invention provides a method for a non-volatile semiconductor storage device containing a nanometer single-crystal silicon floating gate. The method comprises the following steps: forming a trench isolation structure on a semiconductor substrate; forming an oxide layer on the substrate; forming an oxide layer on the above-mentioned oxide layer. Polysilicon layer and nano-silicon floating gate; forming a control gate on a semiconductor substrate; forming a drain source region in a semiconductor substrate; forming a nitride or oxynitride isolation region; depositing an interlayer conductive layer and forming a contact.

Taking the P-type semiconductor substrate as an example, and with reference to FIG. 4 , after the surface of the semiconductor substrate 201 is cleaned, an isolation trench 202 is formed in the substrate 201 using shallow trench isolation (STI) technology. The technology for forming the isolation trench 202 can be prior art known to those skilled in the art.

Referring to FIG. 5, an oxide layer 203 is formed on the semiconductor substrate 201, the oxide layer 203 is a tunnel gate oxide, and the tunnel gate oxide can be silicon oxynitride (SiON), silicon-rich oxide (SRO) , HfO ₂ , Al ₂ O ₃ or SiN, the technology for depositing the above tunnel gate oxide is a prior art well known to those skilled in the art.

Referring to FIG. 6 and FIG. 7 , a polysilicon layer and a nanometer single crystal silicon floating gate are formed on the oxide layer 203 . The process steps of forming the polysilicon layer and the nanometer single crystal silicon floating gate include: depositing a silicon-rich dielectric film layer 204 on the oxide layer 203; depositing a polysilicon layer 205 on the silicon-rich dielectric film layer 204; implanting silicon ions through the polysilicon layer 205 The silicon-rich dielectric thin film layer 204; the semiconductor substrate 201 is annealed, and the silicon-rich dielectric thin film layer 204 forms uniformly distributed nanometer single crystal silicon 206, which can be used as a floating gate.

Referring to Fig. 6, on the oxide layer 203, a silicon-rich dielectric film layer 204 is deposited, and the silicon-rich dielectric film layer 204 can be silicon-rich oxide _SiOx (0<X<2) or silicon-rich oxynitride _{SiOxN y} (0<X<1, 0<Y<1), the preparation method of silicon-rich oxide and silicon-rich oxynitride and the method of depositing a silicon-rich dielectric film layer in the method for forming nano-single crystal silicon in Example 1 of the present invention same. The thickness of the silicon-rich dielectric film layer 204 is between 1.5nm and 50nm.

Then a polysilicon layer 205 is deposited on the silicon-rich dielectric thin film layer 204, the thickness of the polysilicon layer 205 is between 10 and 200 nm, and it is used as a control gate electrode in a non-volatile semiconductor memory. The process method for depositing the polysilicon layer 205 is low pressure chemical vapor deposition (LPCVD) well known to those skilled in the art.

Then, silicon ions are implanted into the silicon-rich dielectric film layer 204 through the polysilicon layer 205 . Silicon ion implantation adopts the method of ion vertical implantation, and the density of silicon ions in the environment is 1×10 ¹⁴ to 10×10 ¹⁵ /cm ² , preferably 1×10 ¹⁶ to 4×10 ¹⁵ /cm 2 . cm ² , the ion implantation energy is 50 to 300keV, more preferably 120keV. According to needs, the content of silicon ions and the energy of ion implantation can be controlled during ion implantation, and the quantity of silicon ions implanted into the silicon-rich dielectric thin film layer 204 can be controlled.

Implanting silicon ions into the silicon-rich dielectric film layer can make the content of silicon in the silicon-rich dielectric film layer higher, and the method of ion implantation can better control the content of silicon ions, so that the subsequent silicon-rich dielectric layer The amount of nano single crystal silicon formed in the process is effectively controlled.

Referring to FIG. 7 , the semiconductor substrate 201 is annealed. After the annealing, nano single crystal silicon 206 is formed in the silicon-rich dielectric thin film layer 204 . The silicon-rich dielectric thin film layer 204 containing evenly distributed nano single crystal silicon 206 can be used as a floating gate of the non-volatile semiconductor memory.

The process of annealing the semiconductor base 201 is to conduct the semiconductor base 201 under NH ₃ , N ₂ , H ₂ or Ar atmosphere, and the annealing temperature is between 700°C and 1000°C.

After the annealing treatment, the excess silicon atoms in the silicon-rich dielectric thin film layer 204 and the silicon ions implanted by the ion implantation method are transformed into nanometer single crystal silicon 206 and silicon oxide SiO _x (or SiO _x N _y ). Since the number of silicon atoms in the silicon-rich dielectric thin film layer 204 and the number of implanted silicon ions can be controlled by controlling the manufacturing process parameters, the number of nano single crystal silicon particles formed is controllable. At the same time, the shape and size of the nano single crystal silicon particles formed by the method can also be controlled. The density of silicon atoms in the nanometer single crystal silicon floating gate provided by the invention is between 1×10 ¹⁰ /cm ² and 1×10 ¹² /cm ² , the particle diameter is between 1 and 10 nm, and the shape is spherical.

Referring to FIG. 8 , the polysilicon layer 205 , the nano-silicon floating gate and the oxide layer 203 are etched to form a control gate. The method of forming the control gate is a prior art well known to those skilled in the art. In this embodiment, a more preferred technical solution is given: a silicon oxynitride (SiON) anti-reflective dielectric coating (DARC) layer (not shown in the figure) is deposited on the polysilicon layer 205 as a protective layer in subsequent steps , the method of depositing silicon oxynitride anti-reflective dielectric film layer is common plasma enhanced chemical vapor deposition (PECVD); spray photoresist on the silicon oxynitride anti-reflective dielectric film layer, according to the designed control gate Expose and develop the photoresist to define the position of the control gate, and then remove the silicon oxynitride anti-reflective dielectric coating layer, polysilicon layer 205, and nano-single crystal silicon outside the control gate by chemical etching. The floating gate and the oxide layer 203 form a control gate as shown in FIG. 8 , and the nano-single-crystal silicon floating gate is a silicon-rich dielectric film layer 204 containing nano-single-crystal silicon 206 . The number of nano single crystal silicon particles contained in each nano single crystal silicon floating gate included in each control gate is between 1 and 100, and the particle diameter is between 1 nm and 10 nm.

Referring to FIG. 9 , a drain source region 207 is formed in the semiconductor body 201 . In the present invention, an implantation process is used to perform a source or drain doping process to form a drain-source region 207 . In one embodiment, the semiconductor base 201 is made of p-type silicon, therefore, N-type dopant implantation is performed on the source and drain.

Referring to FIG. 10, an isolation layer 208 is formed on the control gate. The isolation layer is nitride or oxynitride, and the isolation layer 208 acts as an etching stop layer to protect the gate structure in the subsequent etching process of the interlayer dielectric layer.

Referring to FIG. 11, an interlayer dielectric layer 209 is deposited on the isolation layer 208, and contacts 210 are formed to connect circuits within the memory. An interlayer dielectric layer 209 is deposited on the isolation layer 208, and the interlayer dielectric layer is high-density plasma phosphosilicate glass (HDP PSG) or borophosphosilicate glass (BPSG). The deposition method can use the existing technology, and in one embodiment of the present invention, it can be prepared by sub-atmospheric vapor deposition (SACVD). Then, grooves are formed in the interlayer dielectric layer by etching, and contact materials are deposited in the grooves, and the interlayer dielectric layer and contact materials are polished by chemical mechanical polishing. The contact is made of metal tungsten or polysilicon (polysilicon), which plays the role of conducting the circuit in the circuit.

Although the present invention has been disclosed above with preferred embodiments, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (15)

1, a kind of manufacture method that contains the non-volatile semiconductor storage device of nano single crystal silicon floating gate, it is characterized in that, comprises following processing steps: forming a trench isolation structure on the semiconductor substrate; Form an oxide layer on the substrate; Depositing a silicon-rich dielectric film layer on the oxide layer; Depositing a polysilicon layer on the silicon-rich dielectric film layer; Implanting silicon ions into the silicon-rich dielectric film layer through the polysilicon layer; Annealing the semiconductor substrate to form nano-single crystal silicon in the silicon-rich dielectric film layer, the silicon-rich dielectric film layer formed with nano-single-crystal silicon constitutes a nano-single crystal silicon floating gate; Etching the above-mentioned polysilicon layer, nano single crystal silicon floating gate and oxide layer to form a control gate; Forming a drain source region in a semiconductor substrate; Forming a nitride or oxynitride isolation layer on the control gate; An interlayer dielectric layer is deposited on the isolation layer and forms the contacts to the circuits within the memory. 2. The method for manufacturing a non-volatile semiconductor memory containing nano-silicon single-crystal floating gates according to claim 1, wherein the material of the oxide layer is silicon oxynitride, silicon-rich oxide, HfO ₂ , Al ₂ O ₃ or SiN. 3. The method for manufacturing a non-volatile semiconductor memory containing nano-silicon floating gates according to claim 2, wherein the silicon-rich dielectric thin film layer is silicon-rich oxide SiO _x , where 0<X <2, or silicon-rich oxynitride SiO _x N _y , wherein 0<X<1, 0<Y<1. 4. The method for manufacturing a non-volatile semiconductor memory containing a nanometer single crystal silicon floating gate according to claim 1 or 3, characterized in that the refractive index of the silicon-rich dielectric film layer is 1.48 to 1.98. 5. The method for manufacturing a non-volatile semiconductor memory containing nano-single-crystal silicon floating gates according to claim 4, wherein the refractive index of the silicon-rich dielectric film layer is 1.58 to 1.80. 6. The method for manufacturing a non-volatile semiconductor memory device containing nanometer single-crystal silicon floating gates according to claim 1, wherein the density of silicon ions in the environment during silicon ion implantation is 1×10 ¹⁴ to 1×10 ¹⁶ pcs/cm ² . 7. The method for manufacturing a non-volatile semiconductor memory device containing nano-single-crystal silicon floating gates according to claim 1, wherein the density of silicon ions in the environment during silicon ion implantation is 4×10 ¹⁵ to 1×10 ¹⁶ pcs/cm ² . 8. The method for manufacturing a non-volatile semiconductor memory device containing a nano-silicon floating gate according to claim 1, wherein the silicon ion implantation energy is 50 to 300 keV. 9. The manufacturing method of the non-volatile semiconductor memory containing nano-silicon single crystal floating gate according to claim 8, characterized in that the energy of silicon ion implantation is 100 to 120keV. 10. The method for manufacturing a non-volatile semiconductor memory device containing a nanometer single crystal silicon floating gate according to claim 1, wherein the annealing temperature is 700 to 1000°C. 11. The method for manufacturing a non-volatile semiconductor memory device containing a nano-single-crystal silicon floating gate according to claim 1, characterized in that the process of etching the polysilicon layer, the nano-single-crystal silicon floating gate and the oxide layer to form a control gate To: deposit silicon oxynitride anti-reflective dielectric film on the polysilicon layer, spray photoresist, expose and develop, define the position of the control gate, and then remove the silicon oxynitride anti-reflective dielectric film outside the control gate layer, polysilicon layer, nano single crystal silicon floating gate and oxide layer. 12. The method for manufacturing a non-volatile semiconductor memory with nano-single-crystal silicon floating gates according to claim 1, wherein the nano-single-crystal silicon contained in each nano-single-crystal floating gate contained in each control gate The number of crystalline silicon particles is 1 to 100, and the particle diameter is 1nm to 10nm. 13. The method for manufacturing a non-volatile semiconductor memory containing a nanometer single crystal silicon floating gate according to claim 1, wherein the isolation layer is made of nitride or oxynitride. 14. The method for manufacturing a non-volatile semiconductor memory device containing nanometer single crystal silicon floating gates according to claim 1, wherein the interlayer dielectric layer is high-density plasma phosphosilicate glass or borophosphosilicate Glass. 15. The method for manufacturing a non-volatile semiconductor memory with a nano-silicon floating gate according to claim 1, wherein the contact is made of metal tungsten or polysilicon.

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