CN100468660C - Method for forming metal oxide semiconductor transistor - Google Patents

Abstract

A method for forming metal oxide semiconductor transistor includes providing a substrate, forming a metal oxide semiconductor transistor on the substrate. Then, a self-aligned metal silicification process is carried out, and then an infrared treatment is carried out on the substrate to repair the damage in the substrate. The method can repair the damage in the substrate, so the junction leakage of the metal oxide semiconductor transistor can be effectively reduced, and the yield is further improved.

Description

Method of forming a metal oxide semiconductor transistor

technical field

The invention relates to a method for forming a semiconductor element, in particular to a method for forming a metal oxide semiconductor (MOS), so as to effectively improve the problem of transistor junction leakage (junction leakage).

Background technique

As the semiconductor process enters the deep sub-micron era, increasing the drive current of NMOS and PMOS will greatly improve the time-delay performance of transistor elements. ) has become increasingly important.

For example, traditionally there is research on the development of ILD low dielectric constant (low k) materials to increase the driving current. In recent years, domestic and foreign studies have begun to study the shallow trench isolation (STI) oxide layer, the silicon nitride (SiN) compression or tensile structure (stressor) of the polysilicon cap (Poly-Cap), and the silicon nitride termination of the contact window. Layer (SiN contact etching stopper layer, abbreviated as SiN CESL) film stress (film stress) on the drive current of the transistor element. The result obtained is that the STI oxide, the silicon nitride compressive or tensile structure of the polysilicon cap, and the contact silicon nitride stop layer film stress are deposited as compressive or tensile stress. Moreover, the more tension-resistant the film layer is, the more the NMOS driving current increases; relatively, the more compressed the film layer is, the more the PMOS driving current increases.

In addition, the need to reduce the leakage current of transistor elements is also very important. Recently, some experts at home and abroad tend to think about how to repair the defects of transistors to reduce the leakage path. Therefore, how to effectively increase the stress of the high-tension or high-compression contact silicon nitride stop layer film, and at the same time reduce the current junction leakage of the transistor has become one of the key points to improve the performance of the transistor.

Contents of the invention

The object of the present invention is to provide a method for forming a metal oxide semiconductor transistor, so as to increase the driving current of the device and improve the junction leakage of the transistor.

Another object of the present invention is to provide a method for forming metal-oxide-semiconductor transistors to repair the damage on the wafer surface, so that the junction leakage of the transistors can be greatly improved, thereby improving the yield rate.

The invention provides a method for forming a metal oxide semiconductor transistor, which includes firstly providing a substrate, and then forming a metal oxide semiconductor transistor on the substrate. Afterwards, a silicon nitride contact etching stopper layer (contact etching stopper layer, CESL) is deposited on the substrate to cover the metal oxide semiconductor transistor. Then, a UV curing procedure (UV curing) is performed on the contact etch stop layer, and an infrared (infrared radiation, IR) treatment is performed on the substrate at the same time.

According to the method for forming a metal oxide semiconductor transistor according to an embodiment of the present invention, the power density of the infrared treatment is between 0.7-14.1 W/cm ² ; preferably between 1.4-7.0 W/cm ² .

According to the method for forming a metal oxide semiconductor transistor according to an embodiment of the present invention, the temperature of the ultraviolet curing program is between 150 degrees Celsius and 700 degrees Celsius, the time is between 10 seconds and 60 minutes, and the wavelength of the UV light includes 100nm ~ 400nm wavelength range.

According to the method for forming a metal oxide semiconductor transistor according to an embodiment of the present invention, after the step of forming the metal oxide semiconductor transistor on the substrate, it may further include performing a self-aligned metal silicidation process (self-aligned metal silicidation process ) to form a layer of self-aligned metal silicide layer (metal salicide layer) on the surface of the gate, source, and drain of the metal oxide semiconductor transistor.

According to the method for forming a metal oxide semiconductor transistor according to an embodiment of the present invention, the method for depositing the contact etch stop layer on the substrate includes depositing a silicon nitride layer on the substrate by chemical vapor deposition. The contact etch stop layer can be a compressive dielectric film or a tension dielectric film.

The present invention further provides a method for forming a metal oxide semiconductor transistor, which includes providing a substrate, and then forming a metal oxide semiconductor transistor on the substrate. Next, a self-aligned metal silicide process is performed, and then an infrared (IR) treatment is performed on the substrate to repair the damage in the substrate.

According to the method for forming a metal oxide semiconductor transistor according to another embodiment of the present invention, the power density of the infrared treatment is between 0.7-14.1 W/cm ² ; preferably between 1.4-7.0 W/cm ² .

According to the method for forming a metal oxide semiconductor transistor according to another embodiment of the present invention, after the substrate is subjected to infrared (IR) treatment, a contact etch stop layer may be deposited on the substrate to cover the metal oxide semiconductor transistor. The method for depositing the contact etch stop layer on the substrate includes depositing a silicon nitride layer on the substrate by chemical vapor deposition.

According to another embodiment of the method of forming a MOS transistor of the present invention, when the aforementioned MOS transistor is a PMOS, the contact etch stop layer is a compressive dielectric film.

According to the method for forming a metal oxide semiconductor transistor according to another embodiment of the present invention, when the aforementioned metal oxide semiconductor transistor is NMOS, the contact etch stop layer is a layer of tensile dielectric layer (tensile dielectric film).

In the present invention, an infrared treatment (IR treatment) is added at the same time when the ultraviolet curing process is performed on the contact etch stop layer (CESL) to improve the component stress, thereby producing the effect of heat treatment on the substrate surface to repair the implantation process ( The damage caused by the implantation process). In addition, the present invention can also perform infrared treatment on the surface of the wafer after the self-aligned metal silicide process, which not only achieves the purpose of repairing the damage of the substrate, but also does not affect the nickel silicide (NiSi) because the temperature is not higher than 400 degrees Celsius. process, so that the junction leakage of the transistor can be greatly improved, thereby improving the yield rate.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, the present invention will be described in more detail below with reference to the accompanying drawings and preferred embodiments.

Description of drawings

1A to 1D are schematic cross-sectional views of a process for forming a metal oxide semiconductor transistor according to a first embodiment of the present invention;

2A to 2D are schematic cross-sectional views of a process for forming a metal oxide semiconductor transistor according to a second embodiment of the present invention;

Fig. 3 is the NMOS that obtains according to the method of the present invention and the NMOS that traditionally has not been processed by infrared (IR) in the comparative figure of JLeak;

Fig. 4 is the comparison figure of the PMOS obtained according to the method of the present invention and the traditional PMOS without infrared (IR) processing in terms of JLeak;

Fig. 5 is a comparison chart of JD between the NMOS obtained by the method of the present invention and the NMOS that has not been treated by ultraviolet curing (UV curing) and infrared (IR) conventionally.

simple notation

100, 200: base

102, 202: isolation structure

104, 204: gate structure

104a: gate dielectric layer

104b: grid

104c: spacer wall

106, 206: source and drain

108, 208: source and drain extension regions

110, 210: metal silicide layer

112: contact window etch stop layer

114: UV curing program

116, 212: Infrared (IR) processing

A, C, E: represent squares of metal-oxide-semiconductor transistors according to the present invention

B, D, F: Blocks representing conventional metal-oxide-semiconductor transistors

Detailed ways

The concept of the present invention is to use infrared radiation (IR), which is traditionally avoided as much as possible, to process the substrate formed with metal oxide semiconductor transistors, so as to greatly improve the junction leakage of the transistors, thereby improving the yield. The following examples are given to illustrate the present invention, but the present invention is not limited to the content described in the following examples.

first embodiment

1A to 1D are schematic cross-sectional views of a manufacturing process for forming a metal-oxide-semiconductor transistor according to a first embodiment of the present invention.

Referring to FIG. 1A , a substrate 100 is firstly provided, and it is assumed that it can be divided into a PMOS region and an NMOS region through several isolation structures 102 . Then, a metal oxide semiconductor transistor is formed on the substrate 100 . Wherein, the substrate 100 is, for example, a silicon based substrate; and the isolation structure 102 separating the PMOS region and the NMOS region is generally a shallow trench isolation structure (shallow trench isolation, STI), and its material is, for example, silicon oxide. The method of forming metal-oxide-semiconductor transistors can vary according to the size and process of the device; for example, the gate structure 104 can be formed on the substrate 100 between the isolation structures 102, and the gate The electrode structure 104 at least includes a gate dielectric layer 104a, a gate 104b and a spacer 104c. The material of the gate dielectric layer 104 a is, for example, silicon oxide, the material of the gate 104 b is, for example, doped polysilicon, and the material of the spacer 104 c is, for example, silicon oxide or silicon nitride. In addition, the substrate 100 below the gate structure 104 serves as the channel region 105 of the MOSFET. In addition, the above-mentioned gate structure 104 may also include other components, but since this is inferred by a person having ordinary knowledge in the technical field of the present invention by virtue of the existing technology, it will not be repeated here.

Then, referring to FIG. 1B, the source and drain 106 are formed in the substrate 100 on both sides of the gate structure 104. The formation method may be by using a traditional ion implantation process; or, when the semiconductor process enters the deep submicron era (such as 65nm or less), the source and drain electrodes 106 can be grown only in the silicon-based substrate 100 by means of a selective epitaxial deposition process (selective epitaxial deposition) without growing on silicon oxide or silicon nitride, The selective epitaxial deposition process includes vapor phase epitaxy, which includes reduced pressure chemical vapor deposition epitaxial deposition, atmospheric chemical vapor deposition epitaxy ) and ultra high vacuum chemical vapor deposition epitaxy. Furthermore, the source and drain extension regions 108 may be formed under the spacers 104 c in the gate structure 104 before forming the source and drain 106 to improve the short channel effect. The material of the source and drain extension layer 108 is, for example, single crystal silicon with dopant, epitaxial silicon, silicon germanium (SiGe) or silicon carbide (SiC), and the source and drain extension The formation method of layer 108 is similar to the formation method of source and drain 106, such as conventional ion implantation process or selective epitaxial deposition process. Moreover, the above-mentioned source and drain extension layer 108 and source and drain 106 can be doped in-situ during formation to implant dopants or be doped ex-situ. Implantation of dopants in a heterogeneous manner.

Then, at this time, the step of FIG. 1C can be carried out, and a self-aligned metal silicidation process (self-aligned metal silicidation process) can be carried out to form the surface of the gate 104b and the surface of the source and drain 106 in the gate structure 104. A self-aligned metal salicide layer (metal salicide layer) 110 . The material of the metal silicide layer 110 is a material selected from the group consisting of titanium silicide, nickel silicide, cobalt silicide, platinum silicide, tungsten silicide, tantalum silicide, and molybdenum silicide. In addition, the metal silicide layer 110 formed on the surface of the gate 104b and the metal silicide layer 110 formed on the surfaces of the source and drain 106 may be metal silicide layers of different materials, and the manufacturing process thereof may be slightly changed; for example First cover the surface of the gate 104b with a top cover layer until the silicide metal layer 110 on the surface of the source and drain 106 is formed, then remove the top cover layer, and then form the silicide metal layer on the surface of the gate 104b 110.

After that, referring to FIG. 1D , a contact etching stopper layer (contactetching stopper layer, CESL) 112 is deposited on the substrate 100 to cover the metal oxide semiconductor transistor 104, wherein the method of depositing the contact etching stopper layer 112 is, for example, A silicon nitride layer is deposited on the substrate by chemical vapor deposition process. The contact etch stop layer 112 can be a compressive dielectric film or a tension dielectric film. Next, a UV curing process (UV curing) 114 is performed on the contact etch stop layer 112 , and an infrared (IR) treatment 116 is performed on the substrate 100 at the same time. Wherein, the temperature of the ultraviolet curing program 114 is about 150 degrees Celsius to 700 degrees Celsius, the time is about 10 seconds to 60 minutes, and the wavelength of the UV light includes, for example, a wavelength range of 100 nm to 400 nm. Moreover, the power density of the infrared treatment 116 is, for example, between 0.7˜14.1 W/cm ² ; preferably, it is between 1.4˜7.0 W/cm ² .

Since the present embodiment adds infrared treatment while performing the ultraviolet curing process, it has the effect of repairing the damage in the substrate, and thus can effectively reduce the junction leakage of the transistor while improving the efficiency of the metal oxide semiconductor transistor. For example, when the metal-oxide-semiconductor transistor in the first embodiment is NMOS, after coating a layer of tension dielectric layer (such as silicon nitride layer) on the substrate, the ultraviolet curing process 114 can be performed at the same time. An infrared (IR) treatment 116, so that the tensile stress of the tension dielectric layer can be enhanced until it is greater than 1.8GPa, so as to obtain the maximum NMOS driving current, and because there is an infrared treatment on the substrate, it can be repaired due to the post-implantation process The damage caused greatly improves the junction leakage of NMOS, thereby improving the yield.

second embodiment

2A to 2D are schematic cross-sectional views of a process for forming a metal-oxide-semiconductor transistor according to a second embodiment of the present invention.

Referring to FIG. 2A , a substrate 200 is firstly provided, and it is assumed that it can be divided into a PMOS region and an NMOS region through several isolation structures 202 . Then, a metal oxide semiconductor transistor is formed on the substrate 200 . The method for forming metal-oxide-semiconductor transistors may vary according to the size and process of the device; There are a gate dielectric layer, a gate and a spacer, and its detailed structure can refer to the previous embodiment or the process and structure that can be deduced by those skilled in the art of the present invention by virtue of the existing technology, so it will not be described here Let me repeat.

Then, referring to FIG. 2B , a source electrode and a drain electrode 206 are formed in the substrate 200 on both sides of the gate structure 204, and the formation method may be by using a conventional ion implantation process or the selective epitaxial deposition described in the previous embodiment. process, wherein the selective epitaxial deposition process is such as a vapor phase epitaxy process, which includes methods such as reduced pressure chemical vapor deposition epitaxy, atmospheric pressure chemical vapor deposition epitaxy, and ultra-high vacuum chemical vapor deposition epitaxy. In addition, a so-called source and drain extension region 208 may be optionally formed under the spacer in the gate structure 204 before forming the source and drain 206 to improve the short channel effect. Wherein, the material and formation method of the source and drain extension layers 208 are as described in the previous embodiment.

Next, referring to FIG. 2C , a self-aligned metal silicide process is performed to form a self-aligned metal silicide layer 210 on the surface of the gate and the surfaces of the source and drain 206 in the gate structure 204 . Wherein, the self-aligned metal silicide process is, for example, first depositing a metal layer (not shown) on the substrate 200, so that the metal layer covers the gate surface of the gate structure 204 and the surfaces of the source and drain 206, and then Then, the metal layer and the silicon-containing gate structure 204 , the source electrode and the drain electrode 206 are silicided, and then the metal layer not involved in the reaction is removed. The material of the metal silicide layer 210 is a material selected from the group consisting of titanium silicide, nickel silicide, cobalt silicide, platinum silicide, tungsten silicide, tantalum silicide, and molybdenum silicide. In addition, the metal silicide layer 210 formed on the surface of the gate structure 204 and the surface of the source and drain 206 may be the same or different materials. For example, when the silicide metal layer 210 formed on the surface of the gate structure 204 and the surface of the source and drain electrodes 206 are of different materials, the manufacturing process can be slightly changed; for example, the gate structure 204 is first The surface is covered with a top cover layer, and the top cover layer is removed until the silicide metal layer 210 on the surface of the source and drain 206 is formed, and then another silicide metal layer 210 on the surface of the gate structure 204 is formed.

Afterwards, referring to FIG. 2D , in the stage after the self-aligned metal silicide process, an infrared (IR) treatment 212 is performed on the substrate 200 to repair the damage in the substrate 200, wherein the power density of the infrared treatment 212 is, for example, 0.7 ~14.1W/cm ² ; and preferably between 1.4~7.0W/cm ² . Afterwards, a contact etch stop layer (CESL) may optionally be deposited on the substrate 200 to cover the MOS transistor 204 , the method includes depositing a silicon nitride layer on the substrate 200 by chemical vapor deposition. Moreover, when the metal oxide semiconductor transistor 204 is a PMOS, the contact etch stop layer is a compressive dielectric film; otherwise, when the metal oxide semiconductor transistor is NMOS, the contact etch The stop layer is a layer of tensile dielectric layer (tensile dielectric film), so as to improve the structural stress of the PMOS region and the NMOS region.

Since the second embodiment can choose to perform infrared treatment at any stage after the self-aligned metal silicide process, damages in the substrate can be repaired, thereby effectively reducing the junction leakage of the transistor. In addition, when the self-aligned metal silicide process is developed to the nickel silicide process, the method of the second embodiment will not affect the nickel silicide process because the temperature is mostly not higher than 400 degrees Celsius.

The following is the electrical comparison between the metal oxide semiconductor transistor (MOS) obtained by the method of the present invention and the traditional non-infrared (IR) treated metal oxide semiconductor transistor.

Please refer to FIG. 3 and FIG. 4 first, these two figures respectively show the junction leakage (junction leakage, JLeak) comparison diagram, wherein the squares A and C obtained according to the method of the present invention mainly adopt the method described in the first embodiment, and the power density of the infrared treatment is about 5.66W/cm ² . It can be seen from Figure 3 and Figure 4 that the junction leakage of NMOS (square B) and PMOS (square D) that has not been treated by infrared rays is higher than that of the NMOS (square A) and PMOS (square C) of the present invention. Out 25.89%. Therefore, the present invention can indeed effectively reduce the junction leakage of the metal oxide semiconductor transistor, thereby improving the yield.

In addition, FIG. 5 is a comparison chart of JD between the NMOS obtained by the method of the present invention and the NMOS that has not been treated with ultraviolet curing (UV curing) and infrared (IR). It can be seen from FIG. 5 that the junction leakage of NMOS without UV curing process and IR treatment (see box F) is 15 times higher than that of box E obtained by the method of the present invention.

To sum up, the present invention can effectively reduce the junction leakage of the transistor because the infrared (IR) that traditionally wants to be filtered out as much as possible is used to treat the substrate to repair the damage caused by the implantation process or other processes in the substrate. . In addition, if the infrared treatment is combined with the ultraviolet curing process, the tensile stress of silicon nitride can be effectively enhanced to more than 1.4GPa, thereby increasing the driving current of the NMOS by more than 12%.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall prevail as defined by the appended claims.

Claims (14)

1. method that forms metal oxide semiconductor transistor comprises:

Substrate is provided;

In this substrate, form metal oxide semiconductor transistor;

Deposited silicon nitride contact hole etching suspension layer in this substrate is to cover this metal oxide semiconductor transistor; And

This silicon nitride contact hole etching suspension layer is carried out the ultraviolet curing program, simultaneously infra red treatment is carried out in this substrate, wherein the power density of this infra red treatment is at 0.7～14.1W/cm ²Between.

2. the method for formation metal oxide semiconductor transistor as claimed in claim 1, wherein the power density of this infra red treatment is at 1.4～7.0W/cm ²Between.

3. the method for formation metal oxide semiconductor transistor as claimed in claim 1, wherein the temperature of this ultraviolet curing program is between 150 degree Celsius are spent to Celsius 700.

4. the method for formation metal oxide semiconductor transistor as claimed in claim 1, wherein this ultraviolet curing procedure time is between 10 seconds to 60 minutes.

5. the method for formation metal oxide semiconductor transistor as claimed in claim 1, wherein the UV optical wavelength of this ultraviolet curing program comprises 100nm～400nm range of wavelengths.

6. the method for formation metal oxide semiconductor transistor as claimed in claim 1 wherein after forming the step of this metal oxide semiconductor transistor in this substrate, also comprises and aims at silication technique for metal voluntarily.

7. the method for formation metal oxide semiconductor transistor as claimed in claim 1 wherein comprises in the method for this silicon nitride contact hole etching suspension layer of deposition in this substrate and utilizes chemical vapor deposition method deposited silicon nitride layer in this substrate.

8. the method for formation metal oxide semiconductor transistor as claimed in claim 1, wherein this silicon nitride contact hole etching suspension layer comprises compressive dielectric layer or tension force dielectric layer.

9. method that forms metal oxide semiconductor transistor comprises:

Substrate is provided;

In this substrate, form metal oxide semiconductor transistor;

Aim at silication technique for metal voluntarily; And

Infra red treatment is carried out in this substrate, and to repair the damage in this substrate, wherein the power density of this infra red treatment is at 0.7～14.1W/cm ²Between.

10. the method for formation metal oxide semiconductor transistor as claimed in claim 9, wherein the power density of this infra red treatment is at 1.4～7.0W/cm ²Between.

11. the method for formation metal oxide semiconductor transistor as claimed in claim 9 wherein carries out also comprising after this infra red treatment to this substrate: deposition contact hole etching suspension layer in this substrate, to cover this metal oxide semiconductor transistor.

12. the method for formation metal oxide semiconductor transistor as claimed in claim 11 wherein comprises in the method for this contact hole etching suspension layer of deposition in this substrate and utilizes chemical vapor deposition method deposited silicon nitride layer in this substrate.

13. the method for formation metal oxide semiconductor transistor as claimed in claim 11, wherein working as this metal oxide semiconductor transistor is PMOS, and then this contact hole etching suspension layer is a compressive dielectric layer.

14. the method for formation metal oxide semiconductor transistor as claimed in claim 11, wherein working as this metal oxide semiconductor transistor is NMOS, and then this contact hole etching suspension layer is the tension force dielectric layer.

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