CN100478930C - Identifying-code configuration method of high-grade programable interruption controller - Google Patents

Abstract

The invention is an identification code configuring method for advanced programmable interrupt controllers, applied to a multiprocessor computer system, reallocating identification code of advanced programmable interrupt controller of each CPU in the initializing course, presetting partial identification codes to I/O advanced programmable interrupt controllers and updating multiprocessor configuration table in basic I/O system (BIOS) to avoid the problem of causing identification code conflict at the time of processing interrupt request of peripheral devices, and improving the stability of the multiprocessor computer system.

Description

Identification code configuration method of advanced programmable interrupt controller

【Technical field】

The invention relates to an identification code configuration method, in particular to an identification code configuration method for an advanced programmable interrupt controller in a multiprocessor computer system.

【Background technique】

With the advent of the information age, computer systems have become one of the indispensable tools in people's lives. In order to improve the processing efficiency of computer systems, a Symmetrical Multi-Processor (SMP) system has been developed in recent years. , when the computer system is processing a task, the speed of two processors executing the processing task in parallel is much faster than that of one processor alone. The processor is fast, and when one of the processors fails, the remaining processors can continue to take over its work to maintain the stability of the computer system. Due to the above advantages, most large workstations or server systems use a multi-processor architecture.

At the system level, a multiprocessor system requires two Advanced Programmable Interrupt Controllers (APIC) to handle interrupt requests (Interrupt Request, IRQ): one of which is located in the central processing unit (CPU) The local APIC (Local APIC), the other is the input/output APIC (Input/OutputAPIC; I/O APIC) belonging to the input/output system, and the two can be connected to each other through a dedicated APIC bus (APIC Bus). The local APIC is responsible for handling local interrupts (Local Interrupts) for the local processors. At the same time, it accepts and generates interrupt requests between processors through the AIPC bus; while the I/O APIC uses the redirection table to redirect An interrupt request sent from a local APIC to another local APIC via the APIC bus.

But the I/O APIC can also cause system failures, one of which is the allocation of IDs when the number of processors is large.

When the computer system is turned on, the basic input/output system (BIOS) will set the identification code (ID) stored in the register of each APIC, and need to read from the multiprocessor configuration table (Multiprocessor configuration table; MP configuration table) The identification code of the APIC to provide the information required for the operation of the operating system. The MP configuration table stored in the BIOS has its specific format specification. For example, the MP configuration table following the Intel MP1.4 specification uses a specific multiprocessor and architecture.

In the previous basic input/output system, the parameters of the local APIC on the CPU side in the MP configuration table will be established first, and its identification code will be established starting from 0, while the identification code of the I/O APIC will start from the last CPU After the identification code of the local APIC of the terminal, it is arranged.

For example, when there are 8 CPUs with dual cores in the computer system, there are 8*2 16 local APICs that need to be assigned identification codes, and each local APIC occupies the identification codes 0-15 in sequence, so I/ The identification codes of OAPIC need to be arranged from 16, and these identification codes are stored in the registers of the I/O APIC chipset, but generally speaking, the I/O APIC only supports registers with limited bits, such as AMD8131 The registers of the two I/O APICs in the bridge chip only support 4 bits, that is, only 16 identification codes (0-15) can be set at most. When writing the identification code 16 into the first I/O APIC When register, because can't write complete 10000 (16 of binary method, need 5), will be written as 0000 (binary) this moment, identical with the local APIC identification code of the first central processing unit and form conflict.

Therefore, how to provide an identification code configuration method for an advanced programmable interrupt controller has become one of the problems to be solved by researchers.

【Content of invention】

The present invention mainly provides an identification code configuration method of an advanced programmable interrupt controller, which redistributes the arrangement order of the identification codes of the advanced programmable interrupt controller of the central processing unit and the input/output advanced programmable interrupt controller, so as to The invention solves the identification code conflict problem of the advanced programmable interrupt controller in the multiprocessor computer system, and improves the stability of interrupt request processing.

In the identification code configuration method of the advanced programmable interrupt controller disclosed in a preferred embodiment of the present invention, a new identification code is assigned to the local advanced programmable interrupt controller of each central processing unit respectively; A reserved identification code is assigned to each I/O Advanced Programmable Interrupt Controller. The identification code is different from the new identification codes mentioned above.

In another preferred embodiment of the present invention, it further includes the step of separately storing the assigned reserved identification codes in a register (register) of each input/output advanced programmable interrupt controller; secondly, the reserved identification code selection The combination of positive integers from 0 to (2 ^x -1), x is the number of bits supported by the registers of each input/output advanced programmable interrupt controller; in addition, it also includes storing each new identification code in each local advanced Steps in another register of the programmable interrupt controller; in addition, the new identification code is selected from a group combination of positive integers from 2 ^x to (2 ^y -1), where y is defined by the register of each local advanced programmable interrupt controller Number of digits supported, and x<y.

Furthermore, in a preferred embodiment of the present invention, the new identification code is written in the multiprocessor configuration table, corresponding to the local Advanced Programmable Interrupt Controller identification code field; and these allocated reserved identification codes The multiple I/O advanced programmable interrupt controller identification code fields corresponding to the multiprocessor configuration table are written into the multiprocessor configuration table; as for the storage location of the multiprocessor configuration table, it is located in the basic input/output system of the computer system.

In yet another preferred embodiment of the present invention, the number of reserved identification codes is equal to the number of input/output advanced programmable interrupt controllers.

In a preferred embodiment of the present invention, the step of allocating new identification codes further includes: first assigning the smallest new identification code to one of the local advanced programmable interrupt controllers; and successively accumulating 1 with the smallest new identification code, Distributed one by one to the remaining local Advanced Programmable Interrupt Controllers.

In a preferred embodiment of the present invention, before the new identification code is assigned, the local advanced programmable interrupt controllers of each central processing unit have been assigned an original identification code; and in the step of assigning the new identification code, respectively use Add the number of reserved identification codes to the original identification codes of each local advanced programmable interrupt controller, and make each new identification code.

【Description of drawings】

FIG. 1 is a system block diagram of a preferred embodiment of the present invention.

FIG. 2 is a main flow chart of the method for configuring an APIC identification code in a preferred embodiment of the present invention.

FIG. 3A is a detailed flow chart of the method for configuring an APIC identification code in a preferred embodiment of the present invention.

FIG. 3B is a detailed flowchart of the APIC identification code configuration method continued from FIG. 3A .

【Detailed ways】

The invention starts from the sequence of identification code allocation of Advanced Programmable Interrupt Controller (APIC), and solves the problem of identification code allocation conflict in the prior art.

Please refer to FIG. 1 , which is a system block diagram of a preferred embodiment of the present invention. This example is a computer system with 8 single-core CPUs. Among them, the first central processing unit 10, the second central processing unit 11 ... to the eighth central processing unit 17 respectively have a dedicated first local advanced programmable interrupt controller (hereinafter referred to as the first local APIC) 10a, a second local advanced The programmable interrupt controller (hereinafter referred to as the second local APIC) 11a ... the eighth local advanced programmable interrupt controller (hereinafter referred to as the eighth local APIC) 17a handles interrupt requests for each CPU respectively. At the same time, the first partial APIC 10a, the second partial APIC 11a ... the eighth partial APIC 17a communicate with the first and second input/output advanced programmable interrupt controllers (hereinafter referred to as I) through the front side bus (front side bus) 30. /O APIC) 20, 21 communicate and process interrupt requests from each interface device. In practice, the connection between I/O APIC and local APIC can also use APIC bus, ICC bus (Interrupt Controller Communications Bus), etc.; I/O APIC 20, 21 may be integrated on a single chip, such as AMD 8131 bridge chip. Has 2 I/O APICs.

In addition, the first and second I/O APICs 20, 21 and the first partial APIC 10a, the second partial APIC 11a ... the eighth partial APIC 17a in the central processing unit all have dedicated registers (not shown in the figure), which can be used to store individual identification codes. In this example, the registers of the I/O APIC support 4-bit identification code storage, while the registers of the local APICs in each CPU provide 8 bits. In other words, the registers of the I/O APIC can only store the identification code value of 0-15, and cannot store more than 16, while the local APIC can store the identification code value of (0-255).

Please refer to FIG. 2 , which is a main flow chart of the APIC identification code configuration method in a preferred embodiment of the present invention. Since the distribution of the identification code affects the initialization of the CPU, it will become a huge and cumbersome BIOS (basic input/output system) revision project. Therefore, this example does not change the initialization program of the CPU as the premise to carry out the APIC identification code. redistribution.

First, start the CPU to initialize, and initialize the local APICs of each CPU one by one (step 100); this part follows the general procedure to enable the local APICs of each CPU, and complete the identification code distribution procedure.

The initialized local APIC is assigned an original identification code n _o , these original identification codes n _o may occupy part or all of the 0-15 values, so that the registers of the I/O APIC cannot support it, so a new identification code n must be reassigned To the local APIC (step 101) of each central processing unit; The numerical value of its new identification code n can be that original identification code n _o adds the quantity of I/O APIC, or original identification code n _o directly adds 16, that is Give the value of 0-15 to the I/O APIC.

The process of assigning a new identification code n includes updating the identification code value of the local APIC in each register and writing the MP configuration table (Multiprocessor configuration table) in the BIOS; there is no need to limit the order of the two. The MP configuration table contains the data field elements (entries) required by various operating systems. In addition to the identification codes of I/O APIC and local APIC, it also includes interrupt fields (interrupt entry), bus fields (bus entry), etc.; Whether the MP configuration table is correct or not is related to the normal operation of the operating system.

Then, the identification code m of each I/O APIC is assigned one by one starting from 0 (step 102). Since it starts from 0, it can allow 16 I/O APIC identification codes. 16 I/O APICs are too many for most computer systems, so 16 identification codes can be said to be an I/O APIC. Safe amount. The allocation method can directly allocate the identification code m of the I/O APIC in the MP configuration table, and then store it in the register of the I/O APIC accordingly.

Of course, the exact value assigned to the ID is related to the number of bits supported by the register. If the maximum identification code value that can be supported by the number of register bits is used as the security configuration, the identification code value m assigned to the I/O APIC will fall between 0 and (2 ^x -1), and the local APIC can use the new identification code n is between 2 ^x and (2 ^y -1), where x and y are the number of identification code bits supported by the I/O APIC and local APIC registers respectively, and x<y.

Next, please refer to FIG. 3A and FIG. 3B , which are detailed flow charts of the method for configuring the APIC identification code in a preferred embodiment of the present invention.

After the general central processing unit initialization program, the first partial APIC 10a, the second partial APIC 11a ... the eighth partial APIC 17a in each central processing unit will be enabled one by one, and an original identification code n _o will be assigned as 0-15; the process is as shown in Figure 3A. First, in step 200, enable the local APIC of the first central processing unit and assign the original identification code n _o =0, that is, enable the first partial APIC 10a of the first central processing unit 10, at this time the first partial APIC 10a The value n _o of the assigned original identification code is 0, and is stored in its dedicated register.

Next, set the original identification code n _o =1 (step 201), use a program loop to enable and distribute the original identification codes of all local APICs one by one. First, look for whether there is a central processing unit next (step 202), enable the local APIC of this central processing unit and distribute its original identification code as _no (step 203); when executing step 202 for the first time, the second The CPU 11 will be found first, and its second APIC 11a will be enabled, and the original identification code _no will be assigned the current value 1 and stored in its dedicated register. Then, make the original identification code n _o =n _o +1 (step 204), and return to step 202 to continue searching for the next central processing unit until the eighth local APIC 17a of the eighth central processing unit 17 is enabled Allocation with the identification code, the original identification code n _o =7 of the eighth local APIC 17a. In this embodiment, each processor has a single core, so each has only one local APIC; for a dual-core processor, an individual local APIC is required to handle interrupt requests for each core. Therefore, in a dual-core 8-processor system, there are a total of 16 local APICs, and all 16 identification codes from 0 to 15 will be occupied in the initial stage.

When the second central processing unit does not exist, all local APIC identification codes will be written into the MP configuration table (step 205); at this time, the BIOS will be stored in the first local APIC 10a, the second local APIC 11a ... the eighth local APIC 17a The identification codes of each exclusive register of the MP are established one by one in the local APIC field of the MP configuration table.

Please refer to FIG. 3B , to continue the steps of FIG. 3A , first update the local APIC new identification code n=n _o +r (step 206 ) of the first central processing unit, where r is the number of reserved identification codes. 0 to (r-1) are reserved for I/O APIC. Generally speaking, the reserved number can be equal to the number of I/O APIC, or 2 ^x are reserved, and x is the identification code supported by the I/O APIC register The number of digits; for the 2 I/OAPICs that can support storage of 4-bit identification codes in this example, 2 identification codes 0 and 1 (r=2) can be reserved, and r=2 ⁴ =16 can also be reserved , that is, 0 to 15.

Next, a program loop is used to update the identification codes of all other local APICs one by one. Update the local APIC new identification code of the next central processing unit as n=n+1 (step 207); With the second partial APIC 11a to the eighth partial APIC 17a, it can be very simple with the new identification of the first partial APIC code as a benchmark, update in the way of n=n+1, of course, it can also be updated individually in the way of n=n _o +r, that is, add 2 or 16 to the individual original identification codes (depending on the number of reserved identification codes) Depends), as an individual new identifier. Secondly, it is judged whether the local APICs of all central processing units have been updated to be new identification codes (step 208), if not, then return to the previous step to continue updating; after all the local APIC registers have been updated, each part of the MP configuration table is updated APIC identification code field (step 209).

Next, enable the first I/O APIC and assign the identification code m=0 (step 210), that is, enable the first I/O APIC 20 and assign its identification code as 0. Then, enable the next I/O APIC and assign the identification code m=m+1 (step 211), that is, enable the second I/O APIC 21 and assign its identification code as m=0+1=1. Then find whether there is an I/O APIC next to exist (step 212), for the situation of more than two I/O APICs, promptly get back to step 210 and continue initialization. Finally, write all I/O APIC identification codes into individual registers and MP configuration tables (step 213).

Of course, I/O APIC can use all reserved identification codes arbitrarily, and it is not limited to start from 0 or use continuously. In addition, the present invention is not limited to be executed during the initialization process after booting. Through appropriate program arrangements, it is also possible to enter the BIOS in other states to perform the identification code reallocation process, so as to correct errors in time.

The identification code configuration method of the advanced programmable interrupt controller disclosed by the present invention places the identification code of the I/O APIC before the local APIC of the central processing unit, avoiding the conflict of identification codes; The identification code of the APIC, and reserve a small value along with the identification code for the I/O APIC, so as to effectively avoid the conflict when the operating system reads the identification code, so as to improve the stability of the computer system.

Claims (10)

1, a kind of identifying-code configuration method of Advanced Programmable Interrupt Controllers APICs, be applied to have a computer system of a plurality of central processing units, respectively this central processing unit has at least one local Advanced Programmable Interrupt Controllers APICs (Local APIC), confession is linked up with a plurality of I/O Advanced Programmable Interrupt Controllers APICs (I/O APIC) in this computer system, with handling interrupt requests (interrupt request), it is characterized in that: the method includes the steps of:

Distribute the extremely respectively local Advanced Programmable Interrupt Controllers APICs of this central processing unit of a new identification code respectively; And

To these I/O Advanced Programmable Interrupt Controllers APICs, these are reserved the represented numerical value of figure place that identification codes support for the register of this I/O Advanced Programmable Interrupt Controllers APICs respectively and these and reserve identification code and be different from above-mentioned each new identification code with a plurality of reservation identity assignments;

Wherein, these new identification codes be assigned with these reserve identification codes, be written in the multiprocessor allocation list (Multiprocessorconfiguration table) in the basic input/output (BIOS) of this computer system.

2, the identifying-code configuration method of Advanced Programmable Interrupt Controllers APICs as claimed in claim 1 is characterized in that: this identifying-code configuration method comprise more respectively that storage is assigned with these reserve the step of identification codes in a register (register) of this I/O Advanced Programmable Interrupt Controllers APICs respectively.

3, the identifying-code configuration method of Advanced Programmable Interrupt Controllers APICs as claimed in claim 2 is characterized in that: these are reserved identification code and are selected from 0 to (2 ^x-1) combination of positive integer group, the wherein figure place supported for the register of this I/O Advanced Programmable Interrupt Controllers APICs respectively of x.

4, the identifying-code configuration method of Advanced Programmable Interrupt Controllers APICs as claimed in claim 3 is characterized in that: the identifying-code configuration method of this Advanced Programmable Interrupt Controllers APICs also comprises respectively the respectively step of this new identification code in respectively should another register of part Advanced Programmable Interrupt Controllers APICs of storage.

5, the identifying-code configuration method of Advanced Programmable Interrupt Controllers APICs as claimed in claim 4 is characterized in that: these new identification codes are selected from 2 ^xTo (2 ^y-1) combination of positive integer group, the wherein figure place supported for register that respectively should the part Advanced Programmable Interrupt Controllers APICs of y, and x＜y.

6, the identifying-code configuration method of Advanced Programmable Interrupt Controllers APICs as claimed in claim 1, it is characterized in that: these new identification codes and these reservation identification codes that are assigned with are written in a plurality of local Advanced Programmable Interrupt Controllers APICs identification code field and a plurality of I/O Advanced Programmable Interrupt Controllers APICs identification code field corresponding in this multiprocessor allocation list.

7, the identifying-code configuration method of Advanced Programmable Interrupt Controllers APICs as claimed in claim 1 is characterized in that: the number that these reserve identification codes equals the quantity of these I/O Advanced Programmable Interrupt Controllers APICs.

8, the identifying-code configuration method of Advanced Programmable Interrupt Controllers APICs as claimed in claim 1 is characterized in that: this distribution respectively more comprises in the step of this new identification code:

Distribute earlier in these new identification codes reckling to these local Advanced Programmable Interrupt Controllers APICs one of them; And

This new identification code with minimum adds up 1 one by one, is dispensed to remaining these local Advanced Programmable Interrupt Controllers APICs one by one.

9, the identifying-code configuration method of Advanced Programmable Interrupt Controllers APICs as claimed in claim 1 is characterized in that: before this new identification code was assigned with, respectively the local Advanced Programmable Interrupt Controllers APICs of this central processing unit was assigned with an original identification code respectively.

10, the identifying-code configuration method of Advanced Programmable Interrupt Controllers APICs as claimed in claim 9, it is characterized in that: distribute in the step of this new identification code, add that with original identification code that respectively should the part Advanced Programmable Interrupt Controllers APICs these reserve the number of identification codes respectively, as this new identification code respectively.

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