CN100485765C - Drive circuit, drive method, electro-optical apparatus, and electronic system - Google Patents

Abstract

At least one of the scanning line driving part and the data line driving part includes: a shift register for sequentially outputting transfer signals; a first enable supply line for supplying a plurality of series of first enable signals having a frequency smaller than the transfer signal The first pulse width of the pulse width; The second enable supply line is used to supply a series of second enable signals having a second pulse width smaller than the first pulse width; and a pulse width limiting circuit for receiving Input transfer signal, first and second enable signal. The pulse width limiting circuit limits the pulse width of the transfer signal to the first pulse width by shaping the input transfer signal based on the single first enable signal, and limits the pulse width of the transfer signal to the first pulse width based on the second enable signal by shaping the After the transfer signal width, the pulse width of the transfer signal is limited to the second pulse width.

Description

Driving circuit, driving method, electro-optical device and electronic system

technical field

The present invention relates to the technical field of an electro-optical device driving circuit mounted on an electro-optical device such as a liquid crystal device, a driving method thereof, the electro-optical device, and an electronic system including the electro-optical device.

Background technique

This type of drive circuit is fabricated on a substrate of an electro-optical device such as a liquid crystal device as a data line drive circuit for driving data lines or a scan line drive circuit for driving scan lines. In its operation, the data line driving circuit samples the image signal supplied from the image signal line in accordance with the timing of sampling pulses, thereby supplying the image signal to the data line. Here, if the driving frequency becomes particularly high, the leading and trailing edges of the sampling pulses used for sampling that form a sequence in time slightly overlap. Therefore, image signals sampled at different times also partially overlap and are supplied to the data lines. The result is poor resolution and ghosting.

Therefore, hitherto, in order to realize high-definition image display accompanied by a high driving frequency, there has been a technique for sequentially modulating each of the sampling pulses by a selected plurality of series of enable signals. However, if the phase of the sampling pulse is shifted, the image signals sampled at different times will also overlap, so the resolution may still deteriorate and ghost images may appear. For example, according to the technique described in Patent Document 1, the output of the shift register (first clock signal) is shaped by the second clock signal to generate a sampling pulse to use it for turning on and off of a sampling switch. In this case, the variation of the sampling pulse is absorbed in the variation of the second clock signal.

[Patent Document 1] Japanese Unexamined Patent Application Publication No. 8-286640.

Contents of the invention

However, due to differences between the series of enable signals, the shape and pulse width of the sampling pulses sometimes differ for each series of sampling pulses. In that case, streaked bright spots corresponding to those series may appear on the display. However, the technology disclosed in Patent Document 1 cannot sufficiently deal with such problems. As the driving frequency increases, the influence of the difference between the above-mentioned series of enable signals relatively increases, and thus this problem becomes more serious. In this regard, the above-mentioned problems are not limited to liquid crystal devices. In principle, the same problem can also occur in other electro-optical devices.

The present invention has been made in consideration of, for example, the above-mentioned problems. An object of the present invention is to provide an electro-optical device driving circuit and a method of driving the electro-optical device, enabling high-quality display, and to provide the electro-optical device and an electronic system to which these are applied.

In order to solve the above-mentioned problems, according to the present invention, there is provided an electro-optical device driving circuit for driving an electro-optical device including a plurality of data lines and a plurality of scanning lines extending to cross each other, and electrically A plurality of pixel parts connected to the data line and the scanning line, the driving circuit includes: a scanning line driving part for supplying a scanning signal to the plurality of scanning lines; and a data line driving part for image Signals are supplied to the plurality of data lines, wherein at least one of the scanning line driving section and the data line driving section includes a shift register for sequentially shifting from a plurality of stages, respectively, based on a clock signal having a predetermined cycle. outputting transfer signals; a first enable supply line for supplying a plurality of series of first enable signals having pulses having a pulse width smaller than transfer signals output from the plurality of stages a first pulse width of width; a second enable supply line for providing a series of second enable signals having a second pulse width with a pulse width less than the first pulse width; and a pulse width limit a circuit for shaping each pulse of the input transfer signal by receiving the input transfer signal, first and second enable signals, and based on a plurality of series of respective first enable signals, thereby The pulse width of the transfer signal is limited to the first pulse width, and for, after the transfer signal is limited to the first pulse width, based on the one series of second enable signals, by shaping the transfer signal pulses to limit the pulse width of the transfer signal to a second pulse width.

According to the electro-optical device driving circuit of the present invention, when driving, the image signal is supplied from the data line driving part through the data line to the pixel part line selected by the scanning line driving part through horizontal scanning, so that data is written into the pixel part in line. One or both of the scanning signal of the scanning line driving part and the sampling pulse of the data line driving part are adjusted to have constant pulse width. For example, the adjusted transfer signal is input to a corresponding scan line in the scan line driving part. For another example, the adjusted transfer signal is used as a sampling pulse to sample an image signal, and the sampled image signal is input to a corresponding data line. In this regard, as described earlier, the sampling pulse is a signal for controlling timing at the time of sampling in order to selectively supply the image signal supplied on the image signal line to the data line. Generally, the sampling pulse controls the on and off of the sampling switch provided between the image signal line and the data line. In addition, transfer signals from the shift register are sequentially output from each stage. This means that signals are output from each stage one by one, and it is not necessarily limited to the case where each transfer signal arranged in time series corresponds to a physical array of each stage.

As a common means of achieving higher frequencies, this transfer signal is shaped by multiple series of enable signals within a pulse width limiting circuit. That is, the pulse width of the transfer signal is limited by the pulse widths of the series of enable signals having narrower pulse widths. Here, "a plurality of series" means, for example, that the circuits have the same or different configurations, and signal generation sources or supply paths, such as a plurality of enable signal generation circuits and a plurality of enable signal supply paths, are different from each other. Even if the signals end up overlapping and are processed as a series of signals, this case is included in the concept. In such a case, if the signals are intentionally made to have the same waveform from the beginning, the waveform may be slightly different due to the characteristics of circuit elements and the electronic influence of elements and wiring. Since a plurality of series of enable signals can be handled as signals independent of each other, one transfer signal can be divided under the condition of time sharing and separately supplied to a plurality of signal lines.

However, even if only waveform shaping using such multiple series of enable signals is performed, problems with display may arise due to differences among the series. For example, in the data line driving section, since the pulse shape of the enable signal is reflected on the image signal, the difference in luminance becomes conspicuous due to the difference in the series of pulse widths, and thus the display quality sometimes deteriorates. Specifically, bright spots in the form of vertical stripes appear corresponding to the period of the series. Also, in the scanning line driving section, since the pulse shape of the enable signal is reflected on the scanning signal, the difference in pulse width between the series sometimes becomes bright spots in the form of horizontal stripes.

Therefore, in the electro-optical device driving circuit of the present invention, after being shaped by such a plurality of series of enable signals in the pulse width limiting circuit, the transfer signal is further shaped by a series of enable signals. This enable signal is supplied from the second enable signal line, which has, for example, the pulse width and pulse frequency of the last output signal. Here, "a series" means that the generation source and supply path are the same. In such a case, the width of each pulse and the interval (ie, frequency) of the signal, the shape of deformation including rise time and fall time, etc., become substantially uniform. Enable signals of the same series have consistent pulse widths, etc. to a large extent, at least when compared to multiple series of enable signals. Therefore, the width of each pulse of the transfer signal becomes uniform by this shaping. That is, at this shaping stage, variations in the pulse width of the transfer signal due to differences in series that have occurred at the previous shaping stage can be eliminated. In this regard, the pulse width of a series of enable signals (i.e., the "second pulse width") is shaped so that its pulse width has been limited to that of the pulse width of multiple series of enable signals (i.e., the "first pulse width"). The signal is shifted such that the pulse width is less than the pulse width of the plurality of series of enable signals.

In this way, when the transferred signal has undergone at least two stages of shaping, a signal with a constant pulse width can finally be obtained. Expressed differently, if the signal undergoes two-stage shaping as described above, it is largely Thus, the pulse width of the final output transfer signal (such as sampling pulse, etc.) can be made constant. That is to say, at least the above two stages of shaping are necessary in the present invention. However, a similar shaping step can also be performed. In that case, of course, a final shaping step via a series of enable signals must also be included.

The scanning line driving part generates and outputs scanning signals according to the transfer signals, and the data line driving part samples image signals according to the transfer signals. Therefore, if at least one of the scanning line driving section and the data line driving section performs the above two-stage shaping, at least one of the image signal and the scanning signal can be made to have a constant pulse according to the pulse width of the transfer signal after shaping. width.

Therefore, according to the electro-optical device driving circuit of the present invention, if a plurality of series of enable signals are used when processing the transfer signal, bright spots due to differences between the series of enable signals are difficult to appear, or Actually won't show up.

In an aspect of the electro-optical device driving circuit of the present invention, the pulse width limiting circuit performs shaping of all pulses limited to the transfer signal after the first pulse width based on a series of second enable signals.

According to this aspect, a second stage of shaping based on a series of second enable signals is performed on all transfer signals that have already been shaped based on a plurality of series of first enable signals of the first stage. Thus, bright spots caused by temporal and spatial differences between the series of enable signals can be reliably reduced.

In another aspect of the electro-optic device driving circuit of the present invention, the pulse width limiting circuit adjusts a pulse period of the transfer signal at the output of the pulse width limiting circuit by shaping pulses of the transfer signal based on the second enable signal.

According to this aspect, not only the pulse width but also the pulse period of the transfer signal is adjusted by the second enable signal during shaping, thereby enabling generation and output of timing signals having appropriate shapes (pulse width and pulse period). Furthermore, if only the second enable signal has an appropriate pulse shape in this way, the waveform of the first enable signal is allowed to have a large error.

In another aspect of the electro-optical device driving circuit of the present invention, the pulse width limiting circuit performs primary shaping of roughly shaping each pulse of the transfer signal based on each of a plurality of series of the first enable signal, and based on a The second enabling signal of the series performs secondary shaping with higher accuracy than the primary shaping on the transfer signal pulses limited to the first pulse width.

According to this aspect, the transfer signal is roughly adjusted by primary shaping, and then more precisely adjusted by secondary shaping. Here, "shaping" means that in addition to adjusting the pulse width of the pulse signal, the pulse shape including the pulse period and deformation at rising time and falling time is adjusted according to a predetermined value or a predetermined shape.

In the primary shaping, the pulse shape of the transfer signal is allowed to have a residual error in addition to the variation introduced by the difference in the series of first enable signals. Those errors can be corrected by quadratic shaping according to the accuracy of the second enable signal. Furthermore, in the primary shaping, the difference from the pulse width and pulse shape of the second enable signal can be intentionally left as a margin in the secondary shaping.

In another aspect of the electro-optical device driving circuit of the present invention, the pulse width limiting circuit includes a logic circuit for converting the pulse of the transfer signal to The width is limited to the first pulse width, and then by performing the AND operation between the signal based on the operation result of the AND operation and the second enable signal, the pulse width of the transfer signal after being limited to the first pulse width is limited to second pulse width.

According to this aspect, the pulse width of the transfer signal is limited by the enable signal by performing an AND operation in the logic circuit. In this case, the above-mentioned two-stage shaping step can be implemented by providing two stages of AND circuits, one of which is usually provided in logic. For example, when a logical operation with other signals is performed with an equivalent operation circuit between them or before/after the circuit, etc., the actual circuit size can be reduced. Furthermore, in order to implement the shaping step in a very simple manner, one method considered is to supply a transfer signal between the source and drain of a transistor such as a TFT, the gate of which is controlled by an enable signal. However, the construction of the circuit by means of logic circuits has a much better operational stability of the output signal for the input signal.

In another aspect of the electro-optical device driving circuit of the present invention, in addition to the shift register, the first and second enable supply lines, and the pulse width limiting circuit, the data line driving section further includes a sampling circuit for The timing sampled image signal modulated by the transfer signal after being limited to the second pulse width.

According to this aspect, in the data line driving section, the timing signal adjusts the sampling timing of the image signal. Thus, bright spots in the form of vertical stripes hardly appear on the display, or practically do not appear at all when driven.

In this regard, the pulse width limiting circuit in the data line driving section may receive a precharge timing signal instead of an input of the transfer signal during a precharge period prior to a period in which an image signal is sampled.

In this case, in the data line driving section, during the precharge period, the pulse width limiting circuit shapes and outputs the precharge timing signal instead of the transfer signal. Before applying the image signal, the precharge circuit charges and discharges the data line with a certain potential in order to correct the time delay of the image signal from the voltage level, which is generated by the potential of the data line due to the parasitic capacitance of the data line itself or the like. Specifically, "video precharge" is well known, which supplies a precharge signal from an image signal wiring to a data line during precharging. In order to perform precharging in this way, for the timing signal of the present invention, it is necessary to operate the sampling circuit to electrically connect the image signal line to the data line during the precharging. Here, according to the pre-charging timing signal, the timing signal during the pre-charging period is output, so a pre-charging operation such as "video pre-charging" can be realized. Incidentally, the precharge timing signal can be used as an OR circuit and in a pulse width limiting circuit including an AND circuit.

In order to solve the above-mentioned problems, according to the present invention, an electro-optical device is provided, including: the above-mentioned electro-optical device driving circuit of the present invention (note that the circuit includes various aspects thereof); a plurality of data lines and a plurality of scan lines; multiple pixel sections.

According to the electro-optical device of the present invention, the device includes the electro-optical device driving circuit of the present invention described above, so that it can display with high definition. Such electro-optical devices enable the realization of various display units such as liquid crystal devices, organic electroluminescent (EL) devices, electrophoretic devices such as electronic paper, display devices using electron emission elements (field emission displays and surface conduction electron emission display), etc.

In order to solve the above-mentioned problems, according to the present invention, there is provided an electronic system comprising the electro-optical device described above (note that the circuit includes various aspects thereof).

According to the electronic system of the present invention, the system includes the electro-optical device of the present invention described above. This electro-optical device is equipped with the electro-optical device drive circuit of the present invention, so it can display with high definition. This electronic system can be applied to various electronic systems such as projection display devices, television sets, cellular phones, electronic diaries, word processors, viewfinder type/direct view monitor type video recorders, workstations, television (TV) phones , POS terminal, touch pad, etc.

In order to solve the problems described above, according to the present invention, there is provided a method of driving an electro-optical device for an electro-optical device including a plurality of data lines and a plurality of scan lines extending across each other, and a plurality of pixel portions electrically connected to the data line and the scanning line, respectively, the method comprising: a primary shaping step for a plurality of series based on a first pulse width having a pulse width smaller than a pulse width of a transfer signal; a first enable signal for limiting a pulse width of the transfer signal to a first pulse width by shaping each pulse of the transfer signal sequentially output based on a clock signal having a predetermined period; and a secondary shaping step for Based on a series of second enable signals having a second pulse width smaller than the first pulse width, the transfer signal is transformed by shaping all pulses of the transfer signal that are limited to the first pulse width after the initial shaping step The pulse width of is defined as the second pulse width.

According to the method of driving an electro-optical device of the present invention, as described in the section regarding the driving circuit of the electro-optical device of the present invention, the primary shaping step is performed using a plurality of series of enable signals. Afterwards, a secondary shaping step is performed with a series of enable signals, so that the transferred signal undergoes at least two stages of shaping. The pulse width of the signal after the secondary shaping step is limited by the pulse width of a series of second enable signals, so that a timing signal with a constant pulse width can finally be obtained.

Therefore, according to the method of driving an electro-optical device of the present invention, when a plurality of series of enable signals are used when a transfer signal is processed, bright spots due to differences between the series of enable signals hardly appear or actually will not appear.

These operations and other advantages of the present invention will become clearer through the implementation forms described below.

Brief description of the drawings

(Fig. 1) Fig. 1 is a plan view showing the overall configuration of the electro-optical device according to the first embodiment;

(Fig. 2) Fig. 2 is a sectional view taken along the H-H ' line of Fig. 1;

(FIG. 3) FIG. 3 is a plan view showing a circuit configuration on a TFT array substrate of an electro-optical device according to a first embodiment;

(Fig. 4) Fig. 4 is a block diagram showing the composition of the main drive system of the electro-optical device according to the first embodiment;

(Fig. 5) Fig. 5 shows a diagram of the constitution of the logic circuit in the circuit system of Fig. 4, wherein (A) is a logic circuit diagram, (B) is a logic circuit diagram representing an equivalent circuit of (A), and (C) is a circuit diagram;

(FIG. 6) FIG. 6 is a timing chart for explaining a driving method of the electro-optical device according to the first embodiment;

(FIG. 7) FIG. 7 is a block diagram showing the configuration of the main drive system of the electro-optical device according to a modification of the first embodiment;

(Fig. 8) Fig. 8 is a diagram showing the configuration of a logic circuit in the circuit system of Fig. 7, wherein (A) is a logic circuit diagram, (B) is a logic circuit diagram representing an equivalent circuit of (A), (C) is a circuit diagram;

(FIG. 9) FIG. 9 is a schematic sectional view showing an example of a projection color display as an embodiment of an electronic system to which the electro-optical device of the present invention is applied;

(FIG. 10) FIG. 10 is a logic circuit diagram representing another example of the logic circuit in the circuit system shown in FIG. 7;

(FIG. 11) FIG. 11 is a logic circuit diagram when a part of the logic circuit shown in FIG. 8 is replaced with another circuit.

(reference sign)

2...scanning line, 3...data line, 6...image signal line, 7...sampling circuit, 10...TFT array substrate, 10a...image display area, 51...moving Bit register, 52, 55...logic circuit, 52A, 52B...and (AND) circuit, 52D...or (OR) circuit, 54...unit circuit, 71...sampling switch, 81, 82...enabling supply line, 101...data line driving circuit, 104...scanning line driving circuit, d1, d2...pulse width, Pi...transfer signal, ENB1—ENB4...enabling Enable signal, M-ENB...main enable signal, Qi...primary shaping signal, Si...sampling circuit drive signal, NRG...precharge timing signal

Best form for carrying out the invention

Hereinafter, the best mode for carrying out the present invention will be described with reference to the accompanying drawings.

1. First form of implementation

First, an embodiment of the present invention will be described with reference to FIGS. 1 to 6 . The following embodiments are cases where the electro-optical device of the present invention is applied to a liquid crystal device.

<Configuration of Liquid Crystal Device>

First, the overall configuration of the liquid crystal device in this embodiment will be described with reference to FIGS. 1 to 3 . FIG. 1 is a plan view of a liquid crystal device seen from the side of a counter substrate. Fig. 2 is a sectional view taken along line H-H' of Fig. 1 .

In FIG. 1 and FIG. 2 , the liquid crystal device includes a TFT array substrate 10 and a counter substrate 20 arranged oppositely. A liquid crystal layer 50 is encapsulated between the TFT array substrate 10 and the opposite substrate 20 . The TFT array substrate 10 and the counter substrate 20 are bonded to each other through the sealing substance 52 provided in the sealing area around the image display area 10a. The sealing substance 52 is formed of, for example, an ultraviolet curable resin, a thermosetting resin, or the like for bonding the two substrates. In the manufacturing process, after the sealing substance is applied on the TFT array substrate 10, the substance is hardened by ultraviolet irradiation, heating, or the like. In addition, a gap material such as glass fiber, glass pellets, etc. is dispersed in the sealing substance 52 to ensure that the gap between the TFT array substrate 10 and the counter substrate 20 (gap between substrates) is a predetermined value. The frame light-shielding film 53 , which defines the frame area of the image display area 10 a and shields light, is provided on the side facing the substrate 20 parallel to the inner side of the sealing area where the sealing substance 52 is provided. However, such a frame light-shielding film 53 can be used as a built-in light-shielding film, and part or all of it is provided on one side of the TFT array substrate 10 .

On the TFT array substrate 10 , a data line driving circuit 101 and an external circuit connection terminal 102 are provided along one side of the TFT array substrate 10 in a peripheral region located around the image display region 10 a. Scanning line driving circuits 104 are provided along both sides close to the above-mentioned side, and are covered by the frame light-shielding film 53 . Furthermore, a plurality of wires (wire lines) 105 are arranged along the remaining side of the TFT array substrate 10, and are covered by the frame light-shielding film 53, so as to be connected and arranged on both sides of the image display area 10a in this way. The two scanning line driving circuits 104. In addition, in order to ensure the electrical connection between the TFT array substrate 10 and the opposite substrate 20 , upper and lower conductive terminals 106 are provided between the two substrates.

In FIG. 2, on the TFT array substrate 10, a pixel electrode 9a is formed on the pixel switch TFT and various wirings, and an alignment layer is further formed thereon. On the other hand, in the image display region 10 a on the counter substrate 20 , the counter electrode 21 facing the plurality of pixel electrodes 9 a is formed through the liquid crystal layer 50 . That is, a liquid crystal capacitor is formed between the single electrodes by applying a voltage between the pixel electrode 9 a and the counter electrode 21 . A grid-shaped or stripe-shaped light-shielding film 23 is formed on the counter electrode 21 , and an alignment layer is covered thereon. The liquid crystal layer 50 includes, for example, a liquid crystal made by mixing one or several kinds of nematic liquid crystals in the liquid crystal. Between such a pair of alignment layers, the liquid crystal layer 50 is in a predetermined alignment state.

In this regard, although not shown here, on the TFT array substrate 10, in addition to the data line driver circuit 101, the scan line driver circuit 104, and the like, the later-mentioned sampling circuit 7 and the like are formed. In addition, an inspection circuit or the like may be formed to inspect the quality, defects, etc. of the liquid crystal device during the manufacturing process or the transportation process. Also, on the incident side of the projected light on the counter substrate 20 and on the outgoing side of the emitted light from the TFT array substrate 10, according to, for example, operation modes such as TN (Twisted Nematic) mode, STN (Super TN) mode, D - STN (Double-STN) mode, etc., and the difference between the standard white mode and the standard black mode, a polarizing film, a retardation film, a polarizer, etc. are provided along a predetermined direction. The above is the outline of the configuration of such a liquid crystal device.

Next, the main configuration of such a liquid crystal device will be described with reference to FIGS. 3 to 5. FIG. Here, FIG. 3 shows the configuration of the main part of the liquid crystal device. FIG. 4 shows circuitry for shaping transfer signals in the configuration shown in FIG. 3. FIG. FIG. 5 shows a circuit configuration of a logic circuit in the circuit system of FIG. 4 .

In Fig. 3, the structure of the liquid crystal device is that the TFT array substrate 10 is formed by, for example, a quartz substrate, a glass substrate, or a silicon substrate, and the opposite substrate 20 (not shown in this figure) is separated from the TFT array substrate through the liquid crystal layer. 10 are arranged opposite to each other to control the voltage applied to the pixel electrodes 9a arranged separately in the image display area 10a, and to adjust the electric field applied to the liquid crystal layer for each pixel. Thus, the amount of light transmitted between the two substrates is controlled, thereby displaying an image in a gray scale. This liquid crystal device adopts the method of TFT active matrix addressing. In the image display area 10a of the TFT array substrate 10, a plurality of pixel electrodes 9a arranged in a matrix form, and a plurality of scanning lines 2 and data lines 3 intersecting each other are formed to form a pixel portion corresponding to a pixel. In this regard, although not shown in the figure, a switching element such as a transistor or a thin film transistor (TFT) is formed between each pixel electrode 9a and the data line 3, and according to scanning signals respectively supplied through the scanning lines 2 It is controlled to be in a conduction or non-conduction state, and a storage capacitor is formed for maintaining the voltage applied to the electrode 9a. In addition, a drive circuit such as the data line drive circuit 101 is formed in the surrounding area of the image display area 10a.

The data line driving circuit 101 includes a shift register 51 , a logic circuit 52 , and a sampling circuit 7 . The shift register 51 sequentially outputs the transfer signal Pi from each stage based on the X-side clock signal CLX (and its inverted signal CLX′) having a predetermined period input into the data line driving circuit 101 and the shift register start signal DX (i=1, . . . , n).

The logic circuit 52 is a specific example of the "pulse width limiting circuit" of the present invention, and it has a shaping transfer signal Pi (i=1, . . . , n) based on the enabling signal and a final output sampling circuit driving signal based on the enabling signal. Function of Si (i=1, . . . , 2n). In FIG. 4, the logic circuit 52 includes an AND circuit 51A and an AND circuit 52B. The AND circuit 52A performs switching between the transfer signal Pi (i=1, . . . , n) input from the shift register 51 and one of the enable signals ENB1-ENB4 respectively supplied from the four enable supply lines 81 Between and (AND) operation, and output the result as the primary shaping signal Qi (i=1,...,2n). The AND circuit 52B is provided at a subsequent stage, and performs an AND operation between the primary shaping signal Qi (i=1, . . . , n) and the main enable signal M-ENB supplied from the enable supply line 82, And output the result as the sampling circuit driving signal Si (i=1, . . . , 2n). By performing the AND operation, the transfer signals Pi(i=1,...???,n) and The waveform of the primary shaping signal Qi (i=1, . . . , 2n) is limited to the pulse width of the enabling signal. Here, the enable signals ENB1-ENB4 and the master enable signal M-ENB are examples of "a series of first enable signals" and "a series of second enable signals", respectively.

In addition, transfer signals Pi (i=1, . . . , n) are input from the shift register 51 into the AND circuit 52A for each pair of the signals. That is, the layout design of the data line driving circuit 101 having such a constitution can save space since the number of wiring lines is reduced by half in this portion, and thus it is advantageous to make the pitch narrower. In addition, the transfer signal Pi (i=1,...,n) is simultaneously input into a pair of AND circuits 52A, therefore, different signals among the enable signals ENB1-ENB4 are input into that pair of AND circuits 52A, Therefore, the primary shaping signal Qi (i=1, . . . , n) is output at different times.

The logic circuit 52 is composed using a unit circuit 54 including an AND circuit 52A and an AND circuit 52B shown in FIG. 5A as a unit. Each unit circuit 54 is arranged corresponding to each branch line of the transfer signal Pi (i=1, . . . , n). The unit circuit 54 is equivalent to the logic circuit 52C of FIG. 5(B), so specifically, the circuit can be constructed using TFTs as in FIG. 5(C).

The sampling circuit 7 samples the image signal VID supplied to the image signal line 6 according to the sampling circuit driving signal Si (i=1, . . . , 2n), that is, a reference clock signal, and applies each signal as a data signal to data line 3. For example, as shown in FIG. 4 , the sampling circuit 7 includes a sampling switch 71 including a single-channel TFT, such as a P-channel or N-channel TFT, or a complementary TFT. These sampling circuit drive signals Si are an example of "sequential signals" in the present invention.

In this regard, for simplicity of description, it is assumed that the image signal line 6 is one line, and the image signal VID is assumed to be supplied from this image signal line 6 to any one of the sampling switches 71 . However, the image signal may be serial-parallel expanded (ie, phase expanded). For example, when the image signals are serially-parallel expanded into 6-phase image signals VID1-VID6, these image signals are respectively input into the sampling circuit 7 through 6 image signal lines. When a parallel image signal obtained by converting a serial image signal is simultaneously supplied to a plurality of image signal lines, the image signal can be input to the data line 3 for each group, and thus the driving frequency can be suppressed.

The scan line driving circuit 104 sequentially applies the scan signal generated based on the Y-side clock signal CLY (and its inverted signal CLY'), that is, the reference clock for applying the scan signal, to a plurality of scan lines 2 in order to scan along the The alignment direction of the lines 2 scans a plurality of picture electrodes 9a arranged in a matrix with data signals and scan signals. At that time, voltage is applied to each scanning line 2 from both ends simultaneously.

In this regard, various timing signals such as clock signals are generated by an unillustrated timing generator and supplied to the respective circuits on the TFT array substrate 10 . In addition, a power supply voltage and the like necessary for driving each driving circuit are supplied from an external circuit. Furthermore, the counter electrode potential LCC is supplied from an external circuit to the signal lines drawn from the upper and lower conductive terminals 106 . The counter electrode potential LCC is supplied to the counter electrode 21 through the upper and lower conductive terminals 106 . The counter electrode potential LCC becomes a reference potential of the counter electrode 21 to maintain a potential difference with the pixel electrode 9a at an appropriate value and to form a liquid crystal holding capacity.

<Method of Driving Liquid Crystal Device>

Next, referring to the operation of this liquid crystal device with reference to accompanying drawings 3 to 6, in particular, the transfer signal Pi (i=1,...,n) is shaped into the sampling circuit driving signal Si (i=1,...,2n ) steps are described. FIG. 6 is a timing chart of various signals in the driving system shown in FIG. 4 .

As shown in the timing chart of FIG. 6, first, in the data line driving circuit 101, the transfer signal Pi (i=1, . . . , n) is output from the shift register 51 in the order of P1, P2, . . . . At this time, the odd-numbered transfer signal P _2K-1 and the even-numbered transfer signal P _2K are output in complementary timing (note that K=1, . . . , n/2). Each transfer signal Pi (i=1, . The pulse width is defined as the pulse width d1 of the enable signals ENB1-ENB4. Each enable signal ENB1-ENB4 has a phase shift, so each pulse does not overlap each other. Therefore, in a pair of AND circuits 52A, the same transfer signal Pi (i=1, . waveform. Since the transfer signal Pi (i=1, . . . , n) is output according to the clock signal CLX etc. input into the shift register 51, the increase frequency is limited because of the limitation on the clock period. However, the period can be made smaller in this way by performing an AND operation with the enable signal in the logic circuit 52 to define the pulse width.

Here, each output of the AND circuit 52A is used as the primary shaped signal Qi (i=1, . . . , 2n). Here, since the enable signals ENB1-ENB4 are of different series, it is considered that there is a case where the waveforms are not completely similar. In such a case, pulses having different pulse widths from other pulses are mixed in the primary shaped signal Qi (i=1, . . . , 2n). For example, as shown in FIG. 6, when the enable signal ENB3 has a pulse width d1' wider than the reference pulse width d1, the corresponding pulse width of the primary shaping signal Q3 also becomes the pulse width d1'.

The above-described shaping step of the transfer signal Pi (i=1, . . . , n) in the AND circuit 52A is only the primary shaping step, followed by secondary shaping in the AND circuit 52B.

After the AND operation with the main enable signal M-ENB in the AND circuit 52B (that is, shaped by the main enable signal M-ENB), the pulse of the single primary shaping signal Qi (i=1,...,2n) The width is defined as the pulse width d2 of the master enable signal M-ENB. Since the master enable signal M-ENB is composed of a single series, its pulse width d2 can be regarded as always constant, unlike the enable signals ENB1-ENB4. In addition, the pulse width d2 is narrower than the pulse width d1. Therefore, the pulse width d1' of the primary shaping signal Q3 is also limited by the pulse width d2 to generate and output the sampling circuit driving signal S3.

In this way, each pulse of the primary shaping signal Qi (i=1, . i=1, . . . , 2n) have a uniform pulse width d2. That is to say, in the logic circuit 52 , the sampling circuit driving signal Si (i=1 . . . , 2n) whose pulse width is adjusted to the pulse width d2 is finally obtained. In this regard, in this embodiment, not only the pulse widths of the signals respectively output from the primary shaping step and the secondary shaping step are regularized by the waveform of the enable signal, but also the pulse interval and further including the pulse width in the rise time and fall time A deformed pulse period or pulse shape can also be regularized by the waveform of the enable signal. That is to say, the pulse period or pulse interval of the pulses of the sampling circuit driving signal Si (i=1..., 2n) is adjusted to a predetermined value by the master enable signal M-ENB, and the pulse shape is also adjusted to a predetermined shape.

A sampling circuit driving signal Si (i=1, . In this way, the image signal VID is sampled. Here, since the pulse width of the sampling circuit driving signal Si (i=1,...,2n) is unified to the pulse width d2, the pulse width of the data signal to be generated is also adjusted to the pulse width d2, and is uniform . In addition, the pulse period or pulse interval of the sampling circuit driving signal Si (i=1, . . . , 2n) has a predetermined value, and the pulse period or pulse interval of the data signal to be generated is also adjusted to a predetermined value. Here, since the pulse shape of the sampling circuit driving signal Si (i=1, . . . , 2n) is adjusted to a predetermined shape, the pulse shape of the data signal to be generated is also adjusted to a predetermined shape. Accordingly, a data signal whose pulse width, pulse shape, etc. are properly controlled can be obtained.

The data signal is applied from each data line 3 to the pixel electrode 9a of the selected pixel column, and charges or discharges an unshown storage capacitor for writing data. At this time, since the pulse width and pulse shape of the data signal are uniform, as mentioned above, the luminance can be expressed as a relatively appropriate value, so the appearance of bright spots in the displayed image can be reduced or prevented based on the difference in pulse width . That is to say, the bright spots of the display can be controlled by the height and width of the data signal supplied to the pixel electrode 9a, and the deformation during the rising time and falling time.

In this way, according to the present embodiment, as described above, the pulse width of the data signal is adjusted by the sampling circuit drive signal Si generated through two stages of shaping steps. Thus, in the primary shaping step, when multiple series of enable signals ENB1-ENB4 are used, bright spots due to differences between the series of enable signals ENB1-ENB4 hardly appear or practically do not occur. Will appear. In addition, the pulse cycle or pulse interval and pulse shape of the data signal are adjusted to a predetermined value and a predetermined shape by the sampling circuit drive signal Si, respectively, thereby enabling proper driving.

In addition, the pulse width of the sampling circuit driving signal Si (i=1, . . . , 2n) is finally adjusted by the pulse width d2 of the main enable signal M-ENB, and its pulse shape is also adjusted to a predetermined shape. Therefore, the output waveform of the primary shaping step does not need to have high precision. Thus, there is a method in which the pulse width, cycle, pulse shape, etc. of the transfer signal Pi (i=1, . . For example, in the initial shaping, the pulse shape of the transfer signal Pi (i=1, . . . , n) is allowed to have residual error. These errors can be corrected according to the accuracy of the master enable signal M-ENB by a secondary shaping step. In this regard, in the primary shaping step, the difference in pulse width and pulse shape from the master enable signal M-ENB may be intentionally left as a margin in the secondary shaping step.

In this regard, in the above-described embodiment, the enable signals for the primary shaping step are considered to be 4 series of enable signals ENB1-ENB4. The number of series of enable signals may be lower than this (eg 2 series), or may be higher than this (eg 8 series or more). If the driving frequency becomes further higher, corresponding to processing with higher definition, the number of series of the enable signals is increased to narrow the pulse width. In this case, it occurs more often that the pulse shapes in the series become different. Therefore, a method of performing shaping by one series of enable signals after shaping by a plurality of series of enable signals in this way is effective for maintaining display quality.

<2: Variation 1>

In the above-mentioned embodiment forms, the operation of the writing period (that is, the sampling period) of the image signal VID has been described. However, in such a liquid crystal device, a precharge operation may be performed before the sampling period. In this case, the liquid crystal device can be configured as follows, for example. Here, FIG. 7 shows a circuit system for shaping a transfer signal in a liquid crystal device according to a modification of this embodiment form. FIG. 8 shows a circuit configuration of a logic circuit in the circuit system of FIG. 7 .

The liquid crystal device according to this modification has substantially the same basic configuration as that of the foregoing embodiments. However, this liquid crystal device is different in that the logic circuit 52 of the data line driving circuit 101 is replaced by the logic circuit 55, and precharging is performed at the driving time. Therefore, the same components as those in the foregoing embodiments are denoted by the same reference numerals, and their descriptions are appropriately omitted.

In FIG. 7, the logic circuit 55 includes three stages, an AND circuit 52A, an OR circuit 52D, and an AND circuit 52B. The OR circuit 52D is provided at a stage subsequent to the AND circuit 52A, and at a stage preceding the AND circuit 52B. The OR circuit 52D receives the input from the output of the AND circuit 52A and the precharge timing signal NRG (noise reduction gate), and outputs "high" when at least one of these signals is input. The precharge timing signal NRG is supplied from the outside of the TFT array substrate 10 .

Such a data line driving circuit drives, for example, as follows.

The precharge timing signal NRG defines a precharge period before the sampling period of the image signal VID, and is supplied to the OR circuit 52D immediately. During that time, the same signal as the precharge timing signal NRG is input to the AND circuit 52B through the enable supply line 82 . Therefore, during the input of the precharge timing signal NRG, all the sampling switches 71 become conductive at the same time, and all the data lines 3 are brought into a conductive state connected to the pixel signal line 6 at once. During the input of the precharge timing signal NRG, the logic circuit 55 operates so that all the sampling switches 71 become conductive at the same time, and all the data lines 3 immediately enter a conductive state connected to the pixel signal line 6 . At this time, during the precharging, the data line 3 may receive the image signal supplied from the image signal line 6, or may be connected to a predetermined potential different from that of the image signal. Alternatively, the data line 3 may only be in a conductive state with the image signal line 6 and may not receive a signal supplied from the image signal line 6 .

During the sampling period, in the same manner as the logic circuit 52, the logic circuit 55 generates and outputs the sampling circuit drive signal Si (i=1,  … , 2n). That is to say, the precharge timing signal NRG is not input into the OR circuit 52D during this period, so the OR circuit 52D outputs "high", corresponding to the primary shaping signal Qi (i=1, . . . , 2n).

During precharging, the capacitance occurring between the data line 3 and the counter electrode 21 , the transistor capacitance of the sampling switch 71 , and the wiring capacitance of the image signal line 6 are charged or discharged through the image signal line 6 . Therefore, the variation in potential between the data lines 3 after precharging becomes almost or practically no problem. As a result, variations in writing data signals during subsequent sampling are suppressed, so that high-definition images with reduced display spots can be displayed.

Concrete descriptions have been given of the embodiments of the present invention and modifications thereof. However, the present invention is not limited to these, and various modifications are possible. For example, in the embodiment described above, each output from the shift register 51 is branched and input to each pair of AND circuits 52A. However, this shunt input is not necessarily required. For example, if the entire data line driving circuit is constituted as a group of unit circuits corresponding to the respective data lines, various signals are not shared among a plurality of circuits but are input to and output from each unit circuit.

Furthermore, in this embodiment only two stages of shaping steps are carried out on the transfer signal via AND circuits 52A and 52B. However, in the present invention, at least two stages of steps described above should be performed, and, for example, a similar shaping step may be further performed. In that case, however, a final shaping step via a series of enable signals must be included without fail.

In addition, the description has been given on the shaping of the transfer signal in the data line driving circuit 101 . However, the transfer signal can also be shaped in the same way in the scanning line driving circuit 104 .

<3: Variation 2>

Next, referring to FIG. 10, a practical circuit configuration as a circuit system for shaping the transfer signal shown in FIG. 8(A) will be described. Fig. 10 is a logic circuit diagram showing another example of the circuit system shown in Fig. 8(A) regarding shaping of the transfer signal.

That is, each logic circuit 52 (AND circuit and OR circuit) shown in FIGS. constitute. The circuit shown in FIG. 10 is an example embodying this fact, and is an example of a practical circuit configuration of the logic circuit 55 in FIG. 7 .

In this regard, if the structure for precharging (or circuit 62D, inverting circuit 64, and input of precharge timing signal NRG) is removed from the logic circuit of FIG. 10, the result becomes logic circuit 52 in FIG. A practical circuit constitutes.

In FIG. 10 , the logic circuit 66 includes four stages, namely, a NAND circuit 62A, an OR circuit 62D, a NAND circuit 62B, and an inverting circuit 63 . The OR circuit 62D is provided at a stage after the NAND circuit 62A and at a stage before the NAND circuit 62B. The OR circuit 62D receives the output from the NAND circuit 62A and the precharge timing signal NRG (Noise Reduction Gate) via the inverting circuit 64 as inputs, and outputs "H" when at least one of these signals is input. The precharge timing signal NRG is supplied from outside the TFT array substrate. The inverter circuit 63 includes three inverter circuits 63A, 63B, and 63C, which are sequentially connected at stages subsequent to the NAND circuit 62B. The inverter circuits 63A, 63B, and 63C are formed of transistors having sequentially increased channel bandwidths so that the output signals are sequentially increased. More specifically, the channel bandwidth of the transistors included in the inverter circuit 63B is larger than that of the transistors included in the inverter circuit 63A. The channel bandwidth of the transistors included in the inverter circuit 63C is larger than that of the transistors included in the inverter circuit 63B. According to the logic circuit 66, the sampling switch 71 electrically connected to the next stage of the logic circuit 66 can be driven by the sampling circuit driving signal Si having a large output, compared to the case of using the logic circuit 55.

Next, an example of a logic circuit that can replace the AND circuit 52B and the NAND circuit 62B will be described with reference to FIG. 11 . FIG. 11 is a logic circuit diagram showing an example of an equivalent circuit that can replace the AND circuit 52B and the NAND circuit 62B.

In FIG. 11, an equivalent circuit 72B includes a transmission gate (transmission gate) 74 having a pair of n-channel transistors 74n and a pair of p-channel transistors 74p, and a transistor for electrically connecting the transistors constituting the emission gate 74. Gate of the inverting circuit 73. The master enable signal M-ENB is input to the gate of the transistor 74n. According to the equivalent circuit 72B, the pulse width can be shaped narrower than the case where the sampling circuit drive signal Si is output through the AND circuit 52B and the NAND circuit 62B. Thus, a more preferable sampling circuit drive signal Si can be output when the sampling switch 71 is driven by a high frequency. In addition, the circuit size can be significantly reduced, so this configuration is more advantageous when the pixel pitch is narrowed.

<4: Electronic system>

The liquid crystal device described above can be applied to, for example, a projector. Here, a description will be given of a projector in which the liquid crystal device of the embodiment described above is used as a light valve.

FIG. 9 is a plan view showing an example of a configuration of a projector. As shown in the figure, a lighting unit 1102 including a white light source such as a halogen lamp is provided in the projector 1100 . The projected light emitted from the lighting unit 1102 is divided into three primary color lights RGB by four reflectors 1106 and two dichroic mirrors 1108 arranged inside the light pipe, and then input to the liquid crystal devices 100R, 100B, and 100G as light valves. , each liquid crystal device corresponds to each primary color. The configurations of the liquid crystal devices 100R, 100B, and 100G are the same as those of the liquid crystal display devices described above. The three primary color signals of R, G, and B supplied from the image signal processing circuit are respectively modulated in the liquid crystal device. Each beam of light modulated by these liquid crystal devices enters the dichroic prism 1112 from three directions. Each color image is formed by dichroic prism 1112 and emitted as one color image. This color image is projected onto a screen 1120 and the like through a projection lens 1114 .

In this projection color display device, by using the liquid crystal device in the above embodiment, it is possible to display a high-definition image with little or almost no bright spots.

In this regard, the liquid crystal device of the above-described embodiment can be applied to a direct view type or reverse type color display device in addition to a projector. In that case, on the counter substrate 20 , RGB color filters should be formed together with their protective films in the region opposed to the image electrode 9 a. Alternatively, on the TFT array substrate, a color filter layer opposite to RGB can be formed under the image electrode 9a by using a color resist or the like. Further, in each of the above cases, if microlenses corresponding to the pixels are provided on the opposite substrate 20, the light-gathering efficiency of the incident light can be improved and the display brightness can be improved. Furthermore, a dichroic filter may be formed on the opposite substrate 20, which generates RGB color light by superimposing a plurality of interference layers having different refraction factors by utilizing interference of light. Brighter displays can be produced with a counter substrate having such a dichroic filter.

The present invention has been described above using a liquid crystal device and a liquid crystal projector as examples. However, the present invention can also be applied to electro-optical devices capable of matrix addressing other than liquid crystal devices. Such electro-optical devices include, for example, electroluminescence devices, electrophoretic devices, display devices using electron emission elements (field emission displays and surface conduction electron emission displays), and the like. In addition, the electronic system of the present invention is realized by including the electro-optical device of the present invention described above. In addition to the above-mentioned projector, the electronic system can be implemented as various electronic systems, such as televisions, viewfinder type/direct view monitor type video recorders, car navigation systems, pagers, electronic diaries, calculators , word processors, workstations, TV phones, POS terminals, devices with touch screens, etc.

The invention is not limited to the embodiments described above. The present invention can be appropriately changed without departing from the spirit and scope of the present invention, which can be understood from the appended claims and the entire specification. Therefore, an electro-optical device driving circuit with these changes, a method of driving an electro-optical device, an electro-optical device, and an electronic system including the device should all be included in the technical scope of the present invention.

Claims (10)

1. An electro-optical device driving circuit for driving an electro-optical device, the electro-optical device comprising a plurality of data lines and a plurality of scanning lines extending across each other, and a plurality of pixel portions electrically connected to each other To the data line and the scan line, the drive circuit includes: a scanning line driving section for supplying scanning signals to the plurality of scanning lines; and a data line driving section for supplying image signals to the plurality of data lines, Wherein, at least one of the scanning line driving part and the data line driving part includes a shift register for individually sequentially outputting transfer signals from a plurality of stages based on a clock signal having a predetermined cycle, a set of first enable supply lines for supplying a plurality of series of first enable signals whose supply paths are different from each other, the first enable signals having pulses smaller than the transfer signals output from the plurality of stages The first pulse width, a second enable supply line for supplying a series of second enable signals having the same generation source and supply path, the second enable signals having a second pulse width smaller than the first pulse width, and a pulse width limiting circuit for shaping each of the input transfer signals by receiving the input transfer signals, first and second enable signals, and based on the plurality of series of individual first enable signals pulses, to limit the pulse width of the transfer signal to the first pulse width, and to jointly shape the Pulses of the transfer signal subsequent to being respectively limited to a first pulse width by the plurality of series of first enable signals limit a pulse width of the transfer signal to a second pulse width. 2. The electro-optical device drive circuit according to claim 1, wherein said pulse width limiting circuit performs the limiting of all pulses of said transfer signal after the first pulse width based on said one series of second enable signals. plastic surgery. 3. The electro-optical device drive circuit according to claim 1 or claim 2, wherein said pulse width limiting circuit outputs a signal at said pulse width limiting circuit by shaping the pulse of said transfer signal based on said second enable signal. terminal to adjust the pulse period of the transfer signal. 4. The electro-optical device driving circuit according to claim 1 or 2, wherein said pulse width limiting circuit executes roughly performing each pulse of said transfer signal based on the first enable signal of each of said plurality of series. performing primary shaping of shaping, and based on the series of second enable signals, performing secondary shaping with higher accuracy than the primary shaping on the transfer signal limited to the first pulse width. 5. The electro-optical device driving circuit according to claim 1 or 2, wherein said pulse width limiting circuit includes a logic circuit for converting said transfer signal to The pulse width of is limited to the first pulse width, and by performing an AND operation between the signal based on the operation result of the AND operation and the second enable signal, the transfer signal after having been limited to the first pulse width The pulse width is limited to the second pulse width. 6. The electro-optical device driving circuit according to claim 1 or 2, wherein said data line driving section is further A sampling circuit is included for sampling the image signal at a timing at which the transfer signal after having been limited to the second pulse width is modulated. 7. The electro-optical device driving circuit according to claim 6, wherein said pulse width limiting circuit in said data line driving section receives a substituting for said transfer signal during a precharging period prior to a period during which said image signal is sampled The input precharge timing signal. 8. An electro-optical device characterized by comprising: the electro-optical device driving circuit according to claim 1 or 2. 9. An electronic system comprising an electro-optical device according to claim 8. 10. A method of driving an electro-optical device, the method being applied to an electro-optical device comprising a plurality of data lines and a plurality of scanning lines extending across each other, and a plurality of pixel portions, the plurality of pixels Parts are respectively electrically connected to the data line and the scanning line, and the method includes: a primary shaping step for, based on a plurality of series of first enable signals whose supply paths are different from each other having a first pulse width smaller than a pulse width of a transfer signal, by shaping said each pulse of the transfer signal, limiting the pulse width of the transfer signal to a first pulse width; and a secondary shaping step for a series of second enable signals based on the same generation source and supply path having a second pulse width smaller than the first pulse width, defined by shaping to the first pulse width after the primary shaping step all pulses of the transfer signal, limiting the pulse width of the transfer signal to the second pulse width.

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