[go: up one dir, main page]

CN100483659C - Manufacturing method of packaging structure - Google Patents

Manufacturing method of packaging structure Download PDF

Info

Publication number
CN100483659C
CN100483659C CNB2006101256491A CN200610125649A CN100483659C CN 100483659 C CN100483659 C CN 100483659C CN B2006101256491 A CNB2006101256491 A CN B2006101256491A CN 200610125649 A CN200610125649 A CN 200610125649A CN 100483659 C CN100483659 C CN 100483659C
Authority
CN
China
Prior art keywords
substrate
cutter
material layer
chip
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CNB2006101256491A
Other languages
Chinese (zh)
Other versions
CN101131945A (en
Inventor
翁国良
李政颖
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Semiconductor Engineering Inc
Original Assignee
Advanced Semiconductor Engineering Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Priority to CNB2006101256491A priority Critical patent/CN100483659C/en
Publication of CN101131945A publication Critical patent/CN101131945A/en
Application granted granted Critical
Publication of CN100483659C publication Critical patent/CN100483659C/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The invention discloses a manufacturing method of a packaging structure, which comprises the following steps of firstly, providing a substrate, wherein the substrate is provided with a substrate surface; then, a chip is arranged on the surface of the substrate; then, forming a packaging material layer on the surface of the substrate; then, attaching a film on the surface of the packaging material layer; then, a first cutter is used for penetrating through the substrate and the packaging material layer along a cutting line, but not penetrating through the film, and the cutting line surrounds the chip; then, a second cutter penetrates through the substrate along a part of the cutting line but does not penetrate through the packaging material layer to expose a part of the packaging material layer, wherein the width of the second cutter is larger than that of the first cutter.

Description

The manufacture method of encapsulating structure
[technical field]
The present invention relates to a kind of manufacture method of encapsulating structure, particularly protrude from the manufacture method of the encapsulating structure of substrate side surfaces relevant for a kind of formation one encapsulating material layer.
[background technology]
Along with the continuous development of semiconductor technology, be applied in the various electronic product, brought people and handled day-to-day work and go up many facilities.Wherein semiconductor chip via an encapsulation procedure after, can avoid semiconductor chip to be collided or to make moist.Existing encapsulation procedure can be with reference to accompanying drawing and following detailed description.
Please refer to Figure 1A to 1E, it has represented the structural representation in the manufacturing process of existing encapsulating structure.At first, shown in Figure 1A, provide a substrate 110.Then, shown in Figure 1B, chip 120 is set on substrate 110.Adopt many bonding wire 150 routings to engage (Wire Bonding) chip 120 and substrate 110, be used for electrically connecting chip 120 and substrate 110.The circuit of chip 120 inside is to be electrically connected to the external world by substrate 110.Then, shown in Fig. 1 C, on substrate 110, form sealing 130, be used for avoiding chip 120 to make moist or collide.Then, shown in Fig. 1 D, utilize a cutter 140 cutting sealing 130 and substrates 110.Shown in Fig. 1 E, the substrate 110 after the cutting forms an encapsulating structure 100.
The formed encapsulating structure 100 of existing manufacture method, the sidewall of its sealing 130 are that the sidewall with substrate 110 trims.Yet, in encapsulation procedure, how to research and develop the manufacture method of the encapsulating structure that makes new advances, with the reduction manufacturing cost, and develop a greater variety of encapsulating structures, be an important topic in fact with demand in response to product.
[summary of the invention]
The object of the present invention is to provide a kind of manufacture method of encapsulating structure, it utilizes one first cutter and one second cutter to form an encapsulating structure, like this can be so that encapsulating structure only needs with existing cutting mode, just can make that encapsulating material layer protrudes from substrate side surfaces, thereby save expensive die cost, and do not need to increase complicated processing procedure.
For reaching above-mentioned purpose, the present invention adopts following technical scheme: a kind of manufacture method of encapsulating structure, and this method comprises: step (1) provides a substrate, and this substrate has a substrate surface; Step (2) is that at least one chip is set on substrate surface; Step (3) is to form an encapsulating material on substrate surface; Step (4) is to attach a film on the surface of encapsulating material layer; Step (5) is to run through substrate and encapsulating material layer with one first cutter along a line of cut, but does not run through this film, and described line of cut is to be surrounded on chip; And step (6) is to run through substrate with one second cutter along this line of cut to small part, but does not run through encapsulating material layer, and to expose the part encapsulating material layer, wherein the width of this second cutter is greater than the width of first cutter.
Carrying out being provided with after the chip described in the above-mentioned steps (2), also needing to carry out a routing and engage (wiring bonding, WB) step of chip and substrate.
Said chip is that a rectangular configuration and line of cut also are to form a rectangle
Be to utilize second cutter to run through substrate with the second cutter cutting substrate described in the above-mentioned steps (6), also can running through substrate along two opposed side edges of line of cut along four rectangle sides of line of cut.
Above-mentioned steps (6) described with the second cutter cutting substrate after, also to carry out a step that removes film.
Compared to prior art, the manufacture method of encapsulating structure of the present invention is to form an encapsulating structure with one first cutter and one second cutter, makes encapsulating material layer protrude from substrate side surfaces, and has the following advantages:
The first, manufacture method of the present invention does not need with special mould, only needs can make that in the mode of cutting encapsulating material layer protrudes from substrate side surfaces, saves special die cost.
The second, manufacture method of the present invention is the structure that forms encapsulating material layer in the mode of cutting, and it just can reach purpose of the present invention with existing cutting processing procedure, and does not need the processing procedure of extra increase complexity, saves many manufacturing costs.
[description of drawings]
Figure 1A～1E be the expression existing encapsulating structure manufacturing process in structural representation.
Fig. 2 is the manufacturing flow chart of expression encapsulating structure of the present invention.
Fig. 3 A～3H is the wherein structural representation of an embodiment of expression according to the manufacturing process of encapsulating structure of the present invention.
Fig. 4 is illustrated in the substrate among Fig. 3 F and the vertical view of line of cut thereof.
Fig. 5 is the substrate among the presentation graphs 3G and the vertical view of line of cut thereof.
Fig. 6 be the expression encapsulating structure of the present invention another embodiment in substrate and the vertical view of line of cut.
[embodiment]
Embodiment one
Please be simultaneously with reference to Fig. 2 and Fig. 3 A～3H, Fig. 2 is the manufacturing flow chart of expression encapsulating structure of the present invention.Fig. 3 A～3H is the structural representation of expression according to the manufacturing process of encapsulating structure of the present invention.The present invention is that the encapsulating structure with a fingerprint identifier is that example explains, but the application product of manufacture method of the present invention is not limited thereto.
At first, in the step S21 of Fig. 2, need provide a substrate 210, structural representation as shown in Figure 3, this substrate 210 have a substrate surface 210a (being first surface).
Then, in the step S22 of Fig. 2, need chip 220 be set on substrate surface 210a, shown in Fig. 3 B.Chip 220 in the present embodiment is the identification of fingerprint chip, and this chip 220 has an active surface 220a.Active surface 220a is used for and the proficiency abutment, with the identification fingerprint.And adopt routing to engage (WireBounding) chip 220 and substrate 210, make chip 220 and substrate 210 electrically connect.
Then, in the step S23 of Fig. 2, on substrate surface 210a, form an encapsulating material layer 230, shown in Fig. 3 C, and encapsulating material layer 230 to expose the part active surface 220a, like this can so that active surface 220a can with the finger contact.
Then, in the step S24 of Fig. 2, attach a film 270 at the surperficial 230a of encapsulating material layer 230, shown in Fig. 3 D.
Then, shown in Fig. 3 E, substrate overturn 210 and chip 220 make substrate 210, encapsulating material layer 230 and film 270 arrange from top to bottom in regular turn.
Please be simultaneously with reference to shown in Fig. 4 and Fig. 3 F, wherein Fig. 4 has represented the substrate among Fig. 3 F and the vertical view of line of cut thereof.A plurality of chips 220 are the belows that are arranged in substrate 210 with matrix form, and the chip 220 among the figure is to be represented by dotted lines.Wherein, chip 220 is that a rectangular configuration and many staggered line of cut L are surrounded on chip 220 and form a plurality of rectangle line of cut L.
Then, in the step S25 of Fig. 2, run through substrate 210 and encapsulating material layer 230 with one first cutter 250 along line of cut L, shown in Fig. 3 F.Wherein, first cutter 250 is to run through substrate 210 and encapsulating material layer 230, but does not run through film 270, makes that substrate 210 and the encapsulating material layer 230 after the cutting still can be fixed by film 270.
Then, in the step S26 of Fig. 2, along running through substrate 210, but do not run through encapsulating material layer 230 with one second cutter 260, shown in 3G figure to small part line of cut L.Wherein, the width W 260 of second cutter 260 is the width W 250 greater than first cutter 250 shown in Fig. 3 F, makes that the substrate 210 after the cutting exposes encapsulating material layer 230 partly.
Please be simultaneously with reference to shown in Figure 5, it is illustrated in the vertical view of substrate shown in Fig. 3 G and line of cut thereof.In the present embodiment, step S25 runs through substrate 210 with second cutter 260 along the dual-side L of the correspondence of line of cut L.
Then, shown in Fig. 3 H, remove film 270, to form an encapsulating structure 200.
Please refer to shown in Fig. 3 H, after second cutter 260 ran through substrate 210, the side 210b of substrate 210 and encapsulating material layer 230 formed an accommodation space 280.Present embodiment also is provided with a light emitting source 240 in this accommodation space 280, light emitting source 240 is to be used for penetrating a light S, and it passes through encapsulating material layer 230 to the external world.Wherein, the encapsulating material layer 230 of present embodiment is a transparent material, and light emitting source 240 is chevilled silks, can penetrate light S after the chevilled silk energising.
The formed encapsulating structure 200 of above-mentioned manufacture method be can be in accommodation space 280 ccontaining light emitting source 240, and the S that can emit beam after light source 240 energisings.After the fingerprint identifier of present embodiment penetrated light S, the user just can learn whereby whether fingerprint identifier is positioned at initiate mode.
Embodiment two
Please refer to shown in Figure 6, the substrate of encapsulating structure of its expression another embodiment of the present invention and the vertical view of line of cut thereof.In the present embodiment, second cutter 260 will run through substrate 210 along four sides of line of cut L.Make the encapsulating material layer 230 around the chip 220 all protrude from substrate side 210b, can form bigger accommodation space between encapsulating material layer 230 and the substrate side 210b like this.
According to above two embodiment, though the manufacture method of encapsulating structure of the present invention is to be that example explains to be applied to fingerprint identifier, but manufacture method of the present invention but can be applicable to various encapsulating structure, so long as form an encapsulating structure with one first cutter and one second cutter, to reach the purpose that encapsulating material layer protrudes from substrate side, be included in the scope of the present invention.
The manufacture method of the disclosed encapsulating structure of the above embodiment of the present invention, it forms an encapsulating structure with one first cutter and one second cutter, makes encapsulating material layer protrude from substrate side surfaces, and has the following advantages:
The first, manufacture method of the present invention does not need with special mould, only needs can make that in the mode of cutting encapsulating material layer protrudes from substrate side surfaces, saves special die cost.
The second, manufacture method of the present invention is the structure that forms encapsulating material layer in the mode of cutting, and it just can reach purpose of the present invention with existing cutting processing procedure, and does not need the processing procedure of extra increase complexity, saves many manufacturing costs.

Claims (8)

1.一种封装结构的制造方法，该方法包括：步骤(1)是提供一基板，该基板具有一基板表面；步骤(2)是在基板表面上设置至少一芯片；步骤(3)是在基板表面上形成一封装材料；其特征在于：该制造方法还包括有步骤(4)、(5)及(6)，其中步骤(4)是在封装材料层的表面上贴附一薄膜；步骤(5)是以一第一刀具沿一切割线贯穿基板及封装材料层，但不贯穿该薄膜，所述的切割线是环绕于芯片；以及，步骤(6)是以一第二刀具沿至少部分的该切割线贯穿基板，但不贯穿封装材料层，以暴露出部分封装材料层，其中该第二刀具的宽度大于第一刀具的宽度。1. A manufacturing method of a packaging structure, the method comprising: step (1) is to provide a substrate, the substrate has a substrate surface; step (2) is to arrange at least one chip on the substrate surface; step (3) is to A packaging material is formed on the surface of the substrate; it is characterized in that: the manufacturing method also includes steps (4), (5) and (6), wherein step (4) is to attach a thin film on the surface of the packaging material layer; step (5) using a first cutter to penetrate the substrate and the packaging material layer along a cutting line, but not passing through the film, and the cutting line surrounds the chip; and, step (6) is to use a second cutter along at least Part of the cutting line penetrates the substrate but does not penetrate the encapsulation material layer to expose a part of the encapsulation material layer, wherein the width of the second cutter is greater than that of the first cutter. 2.如权利要求1所述的封装结构的制造方法，其特征在于：在进行了步骤(6)所述的以第二刀具切割基板之后，还要进行一移除薄膜的步骤。2 . The manufacturing method of the packaging structure according to claim 1 , wherein after performing the step (6) of cutting the substrate with the second cutter, a step of removing the film is further performed. 3 . 3.如权利要求1所述的封装结构的制造方法，其特征在于：封装材料层是采用了透明材料。3. The manufacturing method of the packaging structure according to claim 1, wherein the packaging material layer is made of a transparent material. 4.如权利要求1所述的封装结构的制造方法，其特征在于：封装结构是一指纹辩识器，芯片是一指纹辩识芯片。4. The manufacturing method of the packaging structure according to claim 1, wherein the packaging structure is a fingerprint reader, and the chip is a fingerprint recognition chip. 5.如权利要求1所述的封装结构的制造方法，其特征在于：在进行步骤(2)所述的设置芯片之后，还需要进行一打线接合芯片及基板的步骤。5 . The manufacturing method of the package structure according to claim 1 , characterized in that: after the step (2) of disposing the chip, a step of wire bonding the chip and the substrate is further required. 6 . 6.如权利要求1所述的封装结构的制造方法，其特征在于：芯片是一矩形结构且切割线也是形成一矩形。6. The manufacturing method of the packaging structure as claimed in claim 1, wherein the chip is a rectangular structure and the dicing lines also form a rectangle. 7.如权利要求6所述的封装结构的制造方法，其特征在于：在步骤(6)中所述的以第二刀具切割基板是要利用第二刀具沿切割线的四个矩形侧边贯穿基板。7. The manufacturing method of the packaging structure according to claim 6, characterized in that: in step (6), cutting the substrate with the second cutter is to use the second cutter to penetrate through the four rectangular sides of the cutting line substrate. 8.如权利要求6所述的封装结构的制造方法，其特征在于：在步骤(6)中所述的以第二刀具切割基板是要利用第二刀具沿切割线的两个相对的侧边贯穿基板。8. The manufacturing method of the packaging structure according to claim 6, characterized in that: in the step (6), cutting the substrate with the second cutter is to use the second cutter along two opposite sides of the cutting line through the substrate.
CNB2006101256491A 2006-08-25 2006-08-25 Manufacturing method of packaging structure Active CN100483659C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNB2006101256491A CN100483659C (en) 2006-08-25 2006-08-25 Manufacturing method of packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNB2006101256491A CN100483659C (en) 2006-08-25 2006-08-25 Manufacturing method of packaging structure

Publications (2)

Publication Number Publication Date
CN101131945A CN101131945A (en) 2008-02-27
CN100483659C true CN100483659C (en) 2009-04-29

Family

ID=39129144

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2006101256491A Active CN100483659C (en) 2006-08-25 2006-08-25 Manufacturing method of packaging structure

Country Status (1)

Country Link
CN (1) CN100483659C (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10433772B2 (en) 2016-08-16 2019-10-08 Guangdong Oppo Mobile Telecommunications Corp., Ltd. Fingerprint sensor and terminal using the same

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112009000666T5 (en) * 2008-03-24 2011-07-28 Murata Mfg. Co., Ltd., Kyoto Method for producing an electronic component module
CN106019128A (en) * 2016-05-05 2016-10-12 中国科学院微电子研究所 Chip packaging structure applied to irradiation test and manufacturing method thereof
CN106295589B (en) * 2016-08-16 2018-12-04 广东欧珀移动通信有限公司 Fingerprint module, terminal equipment with fingerprint module and processing method of fingerprint module

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6281047B1 (en) * 2000-11-10 2001-08-28 Siliconware Precision Industries, Co., Ltd. Method of singulating a batch of integrated circuit package units constructed on a single matrix base
US20020098620A1 (en) * 2001-01-24 2002-07-25 Yi-Chuan Ding Chip scale package and manufacturing method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6281047B1 (en) * 2000-11-10 2001-08-28 Siliconware Precision Industries, Co., Ltd. Method of singulating a batch of integrated circuit package units constructed on a single matrix base
US20020098620A1 (en) * 2001-01-24 2002-07-25 Yi-Chuan Ding Chip scale package and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10433772B2 (en) 2016-08-16 2019-10-08 Guangdong Oppo Mobile Telecommunications Corp., Ltd. Fingerprint sensor and terminal using the same

Also Published As

Publication number Publication date
CN101131945A (en) 2008-02-27

Similar Documents

Publication Publication Date Title
US8088650B2 (en) Method of fabricating chip package
TW200729371A (en) Semiconductor device and manufacturing method of the same, camera module
CN100483659C (en) Manufacturing method of packaging structure
JP2001035972A5 (en)
WO2006118994A3 (en) Multi-chip module and method of manufacture
US20190088624A1 (en) Manufacturing method of semiconductor device and semiconductor device
TW200945544A (en) Integrated circuit package and manufacturing method thereof
JP2004335605A (en) Semiconductor device manufacturing method and electronic device manufacturing method
US7433199B2 (en) Substrate structure for semiconductor package and package method thereof
US11390519B2 (en) Method for manufacturing a MEMS sensor
CN102412360B (en) Light-emitting diode packaging substrate and forming method of light-emitting diode packaging structure
CN101192545A (en) Sensing package and manufacturing method thereof
TWI293201B (en) Manufacturing method of a package structure
CN1196185C (en) Second half-etching preparation method of image sensor single-layer lead frame
TWI405308B (en) Package and fabricating method thereof
US20150144972A1 (en) Matrix leadframe for led packaging
CN116314541A (en) Element substrate and method for manufacturing same
CN208284496U (en) Packaging body with stacked chips
JP2003068962A (en) Frame and method for manufacturing semiconductor device
TW202226476A (en) Hydrophobic feature to control adhesive flow
CN102447038B (en) Formation method of light-emitting diode packaging structure
CN101527293A (en) Quad flat non-leaded package and lead frame
JP2009302350A (en) Method of manufacturing semiconductor device, and semiconductor device
CN101145548A (en) Universal packaging substrate and application mechanism thereof
CN105633027A (en) Fan-out wafer level chip packaging structure and manufacturing method thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant