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CN100492039C - System and method for testing faults in integrated circuit system-on-chip - Google Patents

System and method for testing faults in integrated circuit system-on-chip Download PDF

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Publication number
CN100492039C
CN100492039C CNB2005100262429A CN200510026242A CN100492039C CN 100492039 C CN100492039 C CN 100492039C CN B2005100262429 A CNB2005100262429 A CN B2005100262429A CN 200510026242 A CN200510026242 A CN 200510026242A CN 100492039 C CN100492039 C CN 100492039C
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test
core
bus
edge
port
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CN1734278A (en
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张金艺
李娇
盛强
任小军
陈文威
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Shanghai Shu Multi-Chip Electronic Co Ltd
University of Shanghai for Science and Technology
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Shanghai Shu Multi-Chip Electronic Co Ltd
University of Shanghai for Science and Technology
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Abstract

The invention relates to an accident detection system and method of SoC System on a chip, which comprises the following parts: strong detection circuit for complete integration chip; detection invitation mechanism whose circuit connects together with serial detection buses; parallel detection bus; IP (Intellectual Property) seed rim packaging chain circuit unit; clock controlling unit and IP seed selection decoding unit. The invitation detection mechanism consists of IP seed independent invitation detection mechanism and IP accident invitation detection mechanism between seeds. This invention adapts each present IP (DFT Design for Testability) method to detect circuit by system layer and IP seeds, which improves system accident percentage of coverage on the integration chip.

Description

The test macro of fault and method in the integrated circuit SOC (system on a chip)
Technical field
The present invention relates to a kind of integrated circuit fault test system and method, particularly a kind of fault test system and method that is applied to integrated circuit SOC (system on a chip) (SoC System on a Chip).
Background technology
Based on IP (Intellectual Property) multiplex technique, the design scale of integrated circuit and realization function have had a sudden change, and (VLSI Very Large Scale IntegrationCircuit) develops into present SOC (system on a chip) by original special function VLSI (very large scale integrated circuit).But along with the increase of integrated circuit on-chip system chip scale and design complexities, the test problem that is difficult for is increasingly serious originally.If can't solve system testing problem on the integrated circuit chip effectively, it will become the main bottleneck of system development on the integrated circuit chip.
Integrated circuit SOC (system on a chip) based on IP reuse technical design structure, usually include IP kernels such as CPU, DSP from different vendor, Memory, ADC/DAC, PLL, and system designer is for integrating these IP kernels and finish the design that the system-specific function adds, and forms with hierarchical structures such as IP kernel layer and system layer.For solving system testing problem on the integrated circuit chip, mainly be to add Testability Design (DFTDesign for Testability) part at present, to improve the controllability and the ornamental of each node of internal system in its design phase.The conventional DFT method, as: scan path method (Full Scan, Partial Scan), boundary scan method (Boundary Scan) and built-in self-test method (BIST) etc., the circuit structure that is suitable for is separately all arranged, generally only be suitable for design for Measurability to single IP kernel.If only use wherein a kind of DFT method to finish the test job of whole integrated circuit SOC (system on a chip), obviously be inconsiderable.
For the integrated circuit SOC (system on a chip) of forming with the stratification form, should mix the method for using with multiple DFT method and realize corresponding fault test work, but standardized mixed structure method of testing not as yet so far, a lot of method of testings still are in conceptual phase and checking property application stage, wherein have Fscan-Bscan, NIMA and present IEEE carrying out standardized P1500 standard.These method of testings all exist: different circuit structure characteristic IP kernels use with a kind of DFT method and the internuclear line fault of each IP kernel in the IP kernel layer does not have problems such as test link, and then causes integrated circuit on-chip system chip fault test expense and fault coverage index to be difficult to be effectively controlled and improve.
Summary of the invention:
The object of the present invention is to provide a kind of fault test system and method that is applied to the integrated circuit SOC (system on a chip).The circuit structure of its test macro is simple; The test of its method of testing mechanism of looking for is simple and direct, is applicable to the integrated circuit SOC (system on a chip) that various use IP reuse technical design make up.
For reaching above-mentioned purpose, the present invention adopts following technical proposals:
The test macro of fault in a kind of integrated circuit SOC (system on a chip) can not only be used for finishing the test of each IP of integrated circuit SOC (system on a chip) (Intellectual Property) nuclear, can also be used to finish the test of interconnection line between IP; It is for improving the circuit that the integrated circuit SOC (system on a chip) can be tested to be increased, and it is characterized in that: its circuit selects decoding unit (5) to be made up of IP kernel serial test bus (1), concurrent testing bus (2), IP kernel edge seal unit link (3), clock control cell (4) with IP kernel; In the circuit: serial test bus (1) has the input and output pin (WSI, WSO) of external scan chain circuit, and the edge seal unit link (3) of inner each IP kernel of output connection in the sheet; Concurrent testing bus (2) has one group of external test bus signal input pin (TBI) and one group of external test bus signal output pin (TBO), and is connected with the DFT interface of inner each IP kernel in sheet; Edge seal unit link (3) has an external encapsulation unit scan enable signals input pin (WSE), and output connects serial test bus (1) in the sheet; Clock control cell (4) have an external system works clock signal input pin (CLK) ,-individual external test enable signal input pin (TEN), an external IP kernel test clock signals input pin (IPTCLK) and an external edge seal unit link test clock signal input pin (WCLK), and output connects edge seal unit link (3) around inner each IP kernel and each IP kernel in the sheet; IP kernel selects decoding unit (5) that one a group of external IP kernel option code signal input pin (IPSB) and an external test enable signal input pin (TEN) are arranged, and output connects internal clocking control module (4) in the sheet.
Above-mentioned serial test bus is by being made up of an input bus, an output bus and 2N triple gate, and wherein, N is the number of contained IP kernel in the integrated circuit SOC (system on a chip).The edge seal unit link of each IP kernel all is connected with the serial test bus by two triple gates.
Above-mentioned concurrent testing bus has one group of test bus input signal and the one group of test bus output signal that is used for connecting the inner DFT of each IP kernel interface section.According to the difference of the DFT method that each IP kernel adopted, the concurrent testing bus is also different with the syndeton of its inner DFT interface: for the IP kernel that adopts the built-in self-test method, the concurrent testing bus is attached thereto by six triple gates; For the IP kernel that adopts the boundary scan method, the concurrent testing bus is attached thereto by four triple gates; For the IP kernel that adopts scanning method, the concurrent testing bus is attached thereto by three triple gates.
Above-mentioned edge seal unit link is that the wsi of institute's fringing encapsulation unit on each input/output port of IP kernel and wso port serial connection are formed.The wsi port of first edge seal unit connects the input bus of serial test bus; The wso port of previous edge seal unit connects the wsi port of a back edge seal unit; The wso port of last edge seal unit connects the output bus of serial test bus.The edge seal unit WC1, the WC2 that comprise two kinds of different connection form in each IP kernel edge seal unit link.
Above-mentioned WC1 edge seal unit is the input port that the do port of edge seal unit is connected IP kernel.
Above-mentioned WC2 edge seal unit then is the output port that edge seal unit di port is connected IP kernel.
Above-mentioned edge seal unit is the preferred circuit that the IEEE tissue proposes, and is made up of two No. two selector switchs and a d type flip flop.
Above-mentioned clock control cell is made up of with door a not gate and 3N two inputs, and wherein, N is the number of contained IP kernel in the integrated circuit SOC (system on a chip).Corresponding to each IP kernel and its edge seal unit link, its clock control circuit part is formed by three two inputs and door.
Above-mentioned IP kernel select decoding unit according to the different mining of the IP kernel number that uses in the integrated circuit SOC (system on a chip) with a kind of variable circuit structure.When N IP kernel arranged in the integrated circuit SOC (system on a chip), then IP kernel selected decoding unit will have a test enable signal input port (TEN), m=log 2 NIndividual IP kernel option code signal input port (m gets integer) and 2 mIndividual IP kernel is selected signal output port; Circuit is by 2m not gate and 2 mIndividual (1+m) input is formed with door.
The method of testing of fault in a kind of integrated circuit SOC (system on a chip) that adopts above-mentioned test macro is characterized in that its test looks for the mechanism part and look for machine-processed the composition by the test of IP kernel independent test mechanism of looking for and the internuclear line fault of IP kernel.
Above-mentioned IP kernel independent test is looked in the mechanism, and by the concurrent testing bus, walking abreast connects the DFT interface of different IP kernels, does not wherein comprise the test clock port of DFT.Select signal according to the IP kernel that IP kernel selects decoding unit to produce, choose corresponding IP kernel, and work with clock control cell one, shield the test clock of other IP kernel, input/output port in other IP kernel of high resistant DFT interface makes other IP kernel be in dormant state, and then selected IP kernel can be tested separately under the situation of using concurrent testing bus and test clock alone, its resolution chart is the original resolution chart of this IP kernel, need not to regenerate.The repetition aforesaid operations can be finished the test to all IP kernel internal elements.
The above-mentioned independent test to IP kernel is looked in the mechanism, if the DFT method of certain IP kernel is a scanning method, then, also need to finish the input and output of corresponding test patterns of the original input/output port of IP kernel and test response by the edge seal unit link of serial test bus and this IP kernel except that finishing by the concurrent testing bus the input and output of corresponding IP kernel test patterns and test response.Select signal according to the IP kernel that IP kernel selects decoding unit to produce, when choosing a certain IP kernel, also choose respective edges encapsulation unit link, and work with clock control cell one, shield the test clock of other IP kernel and the test clock of other edge seal unit link, the input/output port in other IP kernel of high resistant DFT interface and the input/output port of other edge seal unit link, make other IP kernel and edge seal unit link all be in dormant state, and then when selected IP kernel can be tested separately, its edge seal unit link also can independently use serial test bus and test clock.Can realize the input of the original input port test patterns of IP kernel and the output of the original output port test response of IP kernel by this edge seal unit link.
The test of the internuclear line fault of above-mentioned IP kernel is looked in the mechanism, and each IP kernel edge seal unit link all links to each other with the serial test bus.Select signal according to the IP kernel that IP kernel selects decoding unit to produce, choosing a certain IP iIn the time of nuclear, also choose respective edges encapsulation unit link, and work with clock control cell one, shield the test clock of other edge seal unit link, the input/output port of other edge seal unit link of high resistant, make other edge seal unit link be in dormant state, and then make selected edge seal unit link can use serial test bus and test clock separately.At this moment, at first can add the internuclear line fault test of corresponding IP kernel sign indicating number to this edge seal unit link, and this test patterns is displaced to last edge seal unit of edge seal unit link by the WSI port of serial test bus; Secondly, choose IP I+1The edge seal unit link of nuclear is with IP iNuclear periphery encapsulation unit link sends to such an extent that signal is displaced to the WSO port of serial test bus by interconnection line; At last, the data that obtain from the WSO port are analyzed, judged IP iExamine to IP I+1The line failure condition of nuclear transmission direction.Because the transmission direction of signal is two-way on the internuclear line of IP kernel, for by IP I+1Examine to IP iThe internuclear line fault test of nuclear transmission direction, it is an inverse process.At first, choose IP I+1The edge seal unit link of nuclear, the WSI port by the serial test bus adds the internuclear line fault test of corresponding IP kernel sign indicating number to it, and this test patterns is displaced to IP I+1Examine last the edge seal unit in the pairing edge seal unit link; Secondly, choose IP iExamine pairing edge seal unit link, with IP I+1Examining pairing edge seal unit link sends to such an extent that signal is displaced to the WSO port of serial test bus by interconnection line; At last, analyze, judge IP obtaining data from the WSO port I+1Examine to IP iThe line failure condition of nuclear transmission direction.So just finished IP iNuclear and IP I+1The internuclear line fault test of nuclear.Repeat said process, finish the test of the internuclear line fault of whole IP kernels.
The present invention compared with prior art, have following conspicuous advantage: the present invention allows at first that the IP kernel to different circuit structure characteristics uses different DFT methods targetedly on the IP kernel layer of integrated circuit SOC (system on a chip), as to high speed processor IP nuclears such as CPU/DSP boundary scan method, to memory I P such as RAM/ROM nuclear built-in self-test method, to UDL IP kernels such as general control/proprietary feature scanning method, guarantee on this level, because of DFT partly adds the back to related integrated circuit SOC (system on a chip) area, number of pins, power consumption, speed, test such as test patterns length and test duration expense is the most reasonable, the fault coverage of IP kernel test is the highest; Secondly, on the system layer of integrated circuit SOC (system on a chip), set up two groups and can select test bus, mechanism is looked in utilization test flexibly, different DFT interfaces to each IP kernel in the integrated circuit SOC (system on a chip) effectively are connected with edge seal unit link, from system layer buried each IP kernel of going into system is realized independent test, and can carry out the test of the internuclear line fault of IP kernel, the fault coverage of whole integrated circuit SOC (system on a chip) is further improved.Circuit structure of the present invention is simple, the test mechanism of looking for is simple and direct, is applicable to the integrated circuit SOC (system on a chip) that various use IP reuse technical design make up.
Description of drawings
Fig. 1 is the circuit structure block scheme of one embodiment of the invention.
Fig. 2 is that machine-processed implementing procedure figure is looked in the test of IP kernel fault in the realization integrated circuit SOC (system on a chip) of Fig. 1 example.
Fig. 3 is that machine-processed implementing procedure figure is looked in the test of the internuclear line fault of IP kernel in the realization integrated circuit SOC (system on a chip) of Fig. 1 example.
Fig. 4 is Fig. 1 exemplary circuit schematic diagram.
Fig. 5 is the circuit theory diagrams of edge seal unit in the edge seal unit link in Fig. 1 example.
Fig. 6 is the block symbol figure of edge seal unit in Fig. 1 example.
Fig. 7 is the circuit theory diagrams of single edge seal unit link in Fig. 1 example.
Fig. 8 is the circuit theory diagrams of two neighboring edge encapsulation unit links in Fig. 1 example.
Fig. 9 is the circuit theory diagrams that IP kernel is selected an embodiment of decoding unit in Fig. 1 example.
Figure 10 is the truth table that IP kernel is selected an embodiment of decoding unit among Fig. 9.
Embodiment
A preferential embodiment of the present invention is: referring to Fig. 1, Fig. 2 and Fig. 3, comprise the promising circuit that improves integrated circuit SOC (system on a chip) testability and increase and look for mechanism based on the test of this circuit operation.Its circuit selects decoding unit 5 to be made up of IP kernel serial test bus 1, concurrent testing bus 2, IP (Intellectual Property) nuclear periphery encapsulation unit link 3, clock control cell 4 with IP kernel; Its test mechanism of looking for is made up of IP kernel independent test mechanism of looking for 6 and the internuclear line fault test of the IP kernel mechanism of looking for 7.
This circuit structure is: referring to Fig. 1, serial test bus 1 has input and output pin WSI, the WSO of external scan chain circuit, and the edge seal unit link 3 of each IP kernel of output connection in the sheet; Concurrent testing bus 2 has one group of test bus signal input pin TBI and one group of test bus signal output pin TBO, and is connected with the DFT interface of inner each IP kernel in sheet; Edge seal unit link 3 has an external encapsulation unit scan enable signals input pin WSE, and output connects serial test bus 1 in the sheet; Clock control cell 4 has an external system works clock signal input pin CLK, an external test enable signal input pin TEN, an external IP kernel test clock signals IPTCLK and an external edge seal unit link test clock signal WCLK, and output connects inner each IP kernel, each IP kernel edge seal unit link 3 on every side in the sheet; IP kernel selects decoding unit 5 that one group of external IP kernel option code signal input pin IPSB and an external test enable signal input pin TEN are arranged, and output connects clock control cell 4 in the sheet.
Referring to Fig. 4, above-mentioned serial test bus 1 is made up of an input bus WSI, an output bus WSO and 2N triple gate, and wherein, N is the number of contained IP kernel in the integrated circuit SOC (system on a chip).The edge seal unit link 3 of each IP kernel all is connected with the serial test bus by two triple gates (W1, W2).Referring to Fig. 4, above-mentioned concurrent testing bus 2 has one group of test bus input signal TBI0, TBI1, TBI2, TBI3, TBI4 and a group of test bus output signal TBO0, the TBO1 that is used for connecting the inner DFT of each IP kernel interface section.According to the difference of the DFT method that each IP kernel adopted, concurrent testing bus 2 is also different with the syndeton of its inner DFT interface: for the IP kernel that adopts the built-in self-test method (IP for example 1), concurrent testing bus 2 is attached thereto by six triple gates (B1, B2, B3, B4, B5, B6); For the IP kernel that adopts the boundary scan method (IP for example 2), concurrent testing bus 2 is attached thereto by four triple gates (T1, T2, T3, T4); For the IP kernel that adopts scanning method (IP for example 3), concurrent testing bus 2 is attached thereto by three triple gates (S1, S2, S3).Referring to Fig. 7, above-mentioned edge seal unit link 3 is that the wsi of institute's fringing encapsulation unit WC on each input/output port of IP kernel and wso port serial connection are formed.The wsi port of first edge seal unit connects the input bus WSI of serial test bus 1; The wso port of previous edge seal unit connects the wsi port of a back edge seal unit; The wso port of last edge seal unit connects the output bus WSO of serial test bus 1.The edge seal unit (WC1, WC2) that comprises two kinds of different connection form in each IP kernel edge seal unit link.Wherein, the do port of WC1 connects the input port of IP kernel, and the di port of WC2 connects the output port of IP kernel.Referring to Fig. 8, when edge seal unit link between two adjacent IP kernels linked to each other, the di of WC1 type edge seal unit end connected the do end of WC2 type edge seal unit.Referring to Fig. 5, above-mentioned edge seal unit WC is the preferred circuit that the IEEE tissue proposes, and is made of two MUX (M1, M2) and a d type flip flop (D1).Referring to Fig. 6, it is the block symbol figure of edge seal unit.Referring to Fig. 4, above-mentioned clock control cell 4 is by a not gate E1, and 3N two inputs are formed with door, and wherein N is the number of contained IP kernel in the integrated circuit SOC (system on a chip).Corresponding to each IP kernel and its edge seal unit link, its clock control cell is formed by three two inputs and door (C1, C2, C3).Referring to Fig. 4, above-mentioned IP kernel select decoding unit 5 according to the different mining of the IP kernel number that is utilized in the integrated circuit SOC (system on a chip) with a kind of variable circuit structure.When N IP kernel arranged in the integrated circuit SOC (system on a chip), then IP kernel selected decoding unit will have test enable signal input port TEN, a m=log 2 NIndividual IP kernel option code signal input port (m gets integer) and 2 mIndividual IP kernel is selected signal output port; Circuit is by 2m not gate and 2 mIndividual (1+m) input is formed with door.Referring to Fig. 9, have in the present embodiment integrated circuit SOC (system on a chip) smaller or equal to 16 IP kernels, its circuit has four IP kernel option code signal input port IPSB0, IPSB1, IPSB2 and IPSB3 and a test enable signal input port TEN, 16 IP kernel option code signal output port S IP1, S IP2, S IP3, S IP4, S IP5, S IP6, S IP7, S IP8, S IP9, S IP10, S IP11, S IP12, S IP13, S IP14, S IP15And S IP16Circuit is by 8 not gates (U1, U2, U3, U4, U5, U6, U7 and U8), and 16 five inputs are formed with door (U9, U10, U11, U12, U13, U14, U15, U16, U17, U18, U19, U20, U21, U22, U23 and U24).
Referring to Fig. 2, the above-mentioned IP kernel independent test mechanism of looking for 6 is started working when TEN=1.At this moment, the work clock conductively-closed of all IP kernels, integrated circuit enters test mode, select signal according to the IP kernel that IP kernel selects decoding unit 5 to produce, choose corresponding IP kernel, and work with clock control cell 4 one, shield the test clock of other IP kernel, input/output port in other IP kernel of high resistant DFT interface, make other IP kernel be in dormant state, and then selected IP kernel can be tested separately under the situation of using concurrent testing bus 2 and test clock IPTCLK alone, its resolution chart is the original resolution chart of this IP kernel, need not to regenerate.If the DFT method that selected IP kernel adopts is a scanning method, except that finishing by concurrent testing bus 2 input and output of corresponding IP kernel test patterns and test response, also need to finish the input and output of corresponding test patterns of the original input/output port of IP kernel and test response by the edge seal unit link 3 of serial test bus 1 and this IP kernel.Select signal according to the IP kernel that IP kernel selects decoding unit 5 to produce, when choosing a certain IP kernel, also choose respective edges encapsulation unit link, and work with clock control cell 4 one, shield the test clock of other IP kernel and the test clock of other edge seal unit link, the input/output port in other IP kernel of high resistant DFT interface and the input/output port of other edge seal unit link, make other IP kernel and edge seal unit link all be in dormant state, and then when selected IP kernel can be tested separately, its edge seal unit link also can independently use serial test bus 1 and test clock WCLK.Can realize the input of the original input port test patterns of IP kernel and the output of the original output port test response of IP kernel by this edge seal unit link.Repeat above-mentioned testing procedure and just can finish the independent test of each IP kernel.
Referring to Fig. 3, the test of the internuclear line fault of the above-mentioned IP kernel mechanism of looking for 7 is started working when TEN=1.Each IP kernel edge seal unit link 3 all links to each other with serial test bus 1.Select signal according to the IP kernel that IP kernel selects decoding unit 5 to produce, choosing a certain IP iIn the time of nuclear, also choose respective edges encapsulation unit link 3 iAnd work with clock control cell 4 one, shield the test clock of other edge seal unit link, the input/output port of other edge seal unit link of high resistant, make other edge seal unit link be in dormant state, and then make selected edge seal unit link can use serial test bus 1 and test clock WCLK separately.At this moment, WSI port that at first can be by serial test bus 1 is to this edge seal unit link 3 iAdd the internuclear line fault test of corresponding IP kernel sign indicating number, and this test patterns is displaced to edge seal unit link 3 iLast edge seal unit; Secondly, choose IP I+1The edge seal unit link 3 of nuclear I+1, with IP iNuclear periphery encapsulation unit link 3 iSend to such an extent that signal is displaced to the WSO port of serial test bus 1 by interconnection line; At last, the data that obtain from the WSO port are analyzed, judged IP iExamine to IP I+1The line failure condition of nuclear transmission direction.Because the transmission direction of signal is two-way on the internuclear line of IP kernel, to by IP I+1Examine to IP iThe internuclear line fault test of nuclear transmission direction, it is an inverse process.At first choose IP I+1The edge seal unit link 3 of nuclear I+1, by the WSI port of serial test bus 1 it is added the internuclear line fault test of corresponding IP kernel sign indicating number, and this test patterns is displaced to edge seal unit link 3 I+1Last edge seal unit; Secondly, choose IP iThe edge seal unit link 3 of nuclear i, with IP I+1Nuclear periphery encapsulation unit link 3 I+1Send to such an extent that signal is displaced to the WSO port of serial test bus 1 by interconnection line; At last, the data that obtain from the WSO port are analyzed, judged IP I+1Examine to IP iThe line failure condition of nuclear transmission direction.So just finished IP iNuclear and IP I+1The line fault test of nuclear.Repeat said process, can finish the test of the internuclear line fault of whole IP kernels.The test patterns of the internuclear line fault of above-mentioned IP kernel has four kinds of basic code type: 111111......, 000000......, 101010...... and 010101.......The figure place of test patterns equals the input/output port that IP kernel is selected decoding unit 5 IP kernel of choosing.

Claims (12)

1、一种集成电路片上系统中故障的测试系统，不仅能用于完成集成电路片上系统中各个IP(Intellectual Property)核的测试，还能用于完成IP间互连线的测试；它是为完善集成电路片上系统可测试而增加的电路，其特征在于：其电路由IP核串行测试总线(1)、并行测试总线(2)、IP核边缘封装单元链路(3)、时钟控制单元(4)与IP核选择译码单元(5)组成；电路中：串行测试总线(1)有外接扫描链路的输入输出引脚(WSI、WSO)，而片内输出连接内部各个IP核的边缘封装单元链路(3)；并行测试总线(2)有一组外接测试总线信号输入引脚(TBI)和一组外接测试总线信号输出引脚(TBO)，而在片内与内部各个IP核的DFT接口连接；边缘封装单元链路(3)有一个外接封装单元扫描使能信号输入引脚(WSE)，而片内输出连接串行测试总线(1)；时钟控制单元(4)有一个外接系统工作时钟信号输入引脚(CLK)、一个外接测试使能信号输入引脚(TEN)、一个外接IP核测试时钟信号输入引脚(IPTCLK)和一个外接边缘封装单元链路测试时钟信号输入引脚(WCLK)，而片内输出连接内部各个IP核和各个IP核周围的边缘封装单元链路(3)；IP核选择译码单元(5)有一组外接IP核选择码信号输入引脚(IPSB)和一个外接测试使能信号输入引脚(TEN)，而片内输出连接内部时钟控制单元(4)。1. A test system for faults in integrated circuit on-chip systems, not only can be used to complete the test of each IP (Intellectual Property) core in integrated circuit on-chip systems, but also can be used to complete the test of interconnection lines between IPs; it is for Improve the testable and increased circuit of the integrated circuit system on chip, and it is characterized in that: its circuit is composed of IP core serial test bus (1), parallel test bus (2), IP core edge packaging unit link (3), clock control unit (4) Composed with the IP core selection decoding unit (5); in the circuit: the serial test bus (1) has input and output pins (WSI, WSO) for external scan links, and the on-chip output is connected to each internal IP core The edge packaging unit link (3); the parallel test bus (2) has a set of external test bus signal input pins (TBI) and a set of external test bus signal output pins (TBO), and each IP on-chip and internal The DFT interface of the core is connected; the edge package unit link (3) has an external package unit scan enable signal input pin (WSE), and the on-chip output is connected to the serial test bus (1); the clock control unit (4) has An external system working clock signal input pin (CLK), an external test enable signal input pin (TEN), an external IP core test clock signal input pin (IPTCLK) and an external edge package unit link test clock signal The input pin (WCLK), and the on-chip output connects each internal IP core and the edge packaging unit link (3) around each IP core; the IP core selection decoding unit (5) has a group of external IP core selection code signal input leads Pin (IPSB) and an external test enable signal input pin (TEN), while the on-chip output is connected to the internal clock control unit (4). 2、根据权利要求1所述的集成电路片上系统中故障的测试系统，其特征在于所述的串行测试总线(1)由一根输入总线WSI、一根输出总线WSO和2N个三态门组成，其中，N为集成电路片上系统中所含IP核的个数；每一个IP核的边缘封装单元链路(3)均通过两个三态门(W1、W2)与串行测试总线相连接。2, the test system of fault in the integrated circuit system on chip according to claim 1, it is characterized in that described serial test bus (1) is made of an input bus WSI, an output bus WSO and 2N three-state gates wherein, N is the number of IP cores contained in the integrated circuit system on chip; the edge packaging unit link (3) of each IP core is connected to the serial test bus through two tri-state gates (W1, W2) connect. 3、根据权利要求1所述的集成电路片上系统中故障的测试系统，其特征在于所述的并行测试总线(2)有用来连接各个IP核内部DFT接口部分的一组测试总线输入信号(TBI0、TBI1、TBI2、TBI3、TBI4)和一组测试总线输出信号(TBO0、TBO1)。根据各个IP核所采用的DFT方法的不同，并行测试总线(2)与其内部DFT接口的连接结构也不同：对于采用内建自测试法的IP核，并行测试总线(2)通过六个三态门(B1、B2、B3、B4、B5、B6)与之连接；对于采用边缘扫描法的IP核，并行测试总线(2)通过四个三态门(T1、T2、T3、T4)与之连接；对于采用扫描法的IP核，并行测试总线(2)通过三个三态门(S1、S2、S3)与之连接。3, the test system of fault in integrated circuit system on chip according to claim 1, it is characterized in that described parallel test bus (2) has one group of test bus input signal (TBI0) that is used to connect each IP core internal DFT interface part , TBI1, TBI2, TBI3, TBI4) and a set of test bus output signals (TBO0, TBO1). According to the different DFT methods adopted by each IP core, the connection structure of the parallel test bus (2) and its internal DFT interface is also different: for the IP core using the built-in self-test method, the parallel test bus (2) passes through six tri-state The gates (B1, B2, B3, B4, B5, B6) are connected to it; for the IP core using the edge scan method, the parallel test bus (2) is connected to it through four tri-state gates (T1, T2, T3, T4) connection; for the IP core using the scan method, the parallel test bus (2) is connected to it through three tri-state gates (S1, S2, S3). 4、根据权利要求1所述的集成电路片上系统中故障的测试系统，其特征在于所述的电路中各个IP核周围的边缘封装单元链路(3)是将IP核各个输入输出端口上所加边缘封装单元(WC)的wsi和wso端口串接而成；第一个边缘封装单元的wsi端口连接串行测试总线(1)的输入总线WSI；前一个边缘封装单元的wso端口连接后一个边缘封装单元的wsi端口；最后一个边缘封装单元的wso端口连接串行测试总线(1)的输出总线WSO；各个IP核边缘封装单元链路中包含两种不同连接形式的边缘封装单元WC1、WC2；其中，WC1的do端口连接IP核的输入端口，而WC2的di端口连接IP核的输出端口。4, the test system of fault in the integrated circuit system on chip according to claim 1, it is characterized in that the edge encapsulation unit link (3) around each IP core in the described circuit is that each input and output port of IP core The wsi and wso ports of the edge package unit (WC) are connected in series; the wsi port of the first edge package unit is connected to the input bus WSI of the serial test bus (1); the wso port of the previous edge package unit is connected to the latter The wsi port of the edge packaging unit; the wso port of the last edge packaging unit is connected to the output bus WSO of the serial test bus (1); each IP core edge packaging unit link contains edge packaging units WC1 and WC2 of two different connection forms ; Among them, the do port of WC1 is connected to the input port of the IP core, and the di port of WC2 is connected to the output port of the IP core. 5、根据权利要求4所述的集成电路片上系统中故障的测试系统，其特征在于所述的边缘封装单元是IEEE组织提出的一个标准电路，它由两个二路选择器(M1、M2)和一个D触发器(D1)组成。5, the test system of fault in integrated circuit system on chip according to claim 4, it is characterized in that described edge encapsulation unit is a standard circuit proposed by IEEE organization, and it consists of two two-way selectors (M1, M2) and a D flip-flop (D1). 6、根据权利要求1所述的集成电路片上系统中故障的测试系统，其特征在于时钟控制单元(4)由一个非门E1和3N个二输入与门组成，其中，N为集成电路片上系统中所含IP核的个数；对应于每一个IP核和其边缘封装单元链路，其时钟控制电路部分均由三个二输入与门(C1、C2、C3)组成。6. The test system for faults in the integrated circuit system on chip according to claim 1, characterized in that the clock control unit (4) is composed of a NOT gate E1 and 3N two-input AND gates, wherein N is the integrated circuit system on chip The number of IP cores contained in it; corresponding to each IP core and its edge packaging unit link, its clock control circuit part is composed of three two-input AND gates (C1, C2, C3). 7、根据权利要求1所述的集成电路片上系统中故障的测试系统，其特征在于其IP核选择译码单元(5)根据集成电路片上系统中所使用IP核数目的不同采用一种可变的电路结构，当集成电路片上系统中有N个IP核时，则IP核选择译码单元(5)将会有一个测试使能信号输入端口(TEN)、m＝log2 N个IP核选择码信号输入端口(m取上整数)和2m个IP核选择信号输出端口；电路由2m个非门和2m个(1+m)输入与门组成；当集成电路片上系统中有小于等于16个IP核时，其电路应有四个IP核选择码信号输入端口(IPSB0、IPSB1、IPSB2和IPSB3)、一个测试使能信号输入端口(TEN)和十六个IP核选择码信号输出端口(SIP1、SIP2、SIP3、SIP4、SIP5、SIP6、SIP7、SIP8、SIP9、SIP10、SIP11、SIP12、SIP13、SIP14、SIP15和SIP16)；电路由8个非门(U1、U2、U3、U4、U5、U6、U7和U8)，十六个五输入与门(U9、U10、U11、U12、U13、U14、U15、U16、U17、U18、U19、U20、U21、U22、U23和U24)组成。7. The test system for faults in the integrated circuit system on chip according to claim 1, characterized in that its IP core selection decoding unit (5) adopts a variable When there are N IP cores in the integrated circuit system on chip, then the IP core selection decoding unit (5) will have a test enable signal input port (TEN), m=log 2 N IP core selections Code signal input port (m takes the upper integer) and 2 m IP core selection signal output ports; the circuit is composed of 2 m NOT gates and 2 m (1+m) input AND gates; when there are less than or equal to When there are 16 IP cores, the circuit should have four IP core selection code signal input ports (IPSB0, IPSB1, IPSB2 and IPSB3), one test enable signal input port (TEN) and sixteen IP core selection code signal output ports (S IP1 , S IP2 , S IP3 , S IP4 , S IP5 , S IP6 , S IP7 , S IP8 , S IP9 , S IP10, S IP11 , S IP12 , S IP13 , S IP14 , S IP15 and S IP16 ); The circuit consists of 8 NOT gates (U1, U2, U3, U4, U5, U6, U7 and U8), sixteen five-input AND gates (U9, U10, U11, U12, U13, U14, U15, U16, U17, U18, U19, U20, U21, U22, U23 and U24). 8、一种采用权利要求1所述测试系统的集成电路片上系统中故障的测试方法，其特征在于其测试寻访机制包含IP核独立测试寻访机制(6)和IP核核间连线故障的测试寻访机制(7)。8, a kind of test method that adopts the fault in the integrated circuit system on chip system of test system described in claim 1, it is characterized in that its test search and visit mechanism comprises the test of IP core independent test search and visit mechanism (6) and the connection fault between IP core core Search Mechanism (7). 9、根据权利要求8所述的集成电路片上系统中故障的测试方法，其特征在于所述的IP核独立测试寻访机制(6)是通过并行测试总线(2)，并行连接不同IP核的DFT接口，其中不包含DFT的测试时钟端口，根据IP核选择译码单元(5)产生的IP核选择信号，选中相应的IP核，并与时钟控制单元(4)一起作用，屏蔽其它IP核的测试时钟，高阻其它IP核DFT接口中的输入输出端口，使其它IP核处于休眠状态，进而使被选中IP核能在独自使用并行测试总线(2)和测试时钟(IPTCLK)的情况下进行单独测试，其测试图形为该IP核原来的测试图形，无需重新生成；重复上述操作来完成对所有IP核内部单元的测试。9, the test method of fault in the integrated circuit system on chip according to claim 8, it is characterized in that described IP core independent test search mechanism (6) is by parallel test bus (2), the DFT of parallel connection different IP cores The interface, which does not include the test clock port of DFT, selects the corresponding IP core according to the IP core selection signal generated by the IP core selection decoding unit (5), and works together with the clock control unit (4) to shield other IP cores. The test clock, high-impedance input and output ports in the DFT interface of other IP cores, makes other IP cores in a dormant state, so that the selected IP cores can independently use the parallel test bus (2) and test clock (IPTCLK). Test, the test pattern is the original test pattern of the IP core, no need to regenerate; repeat the above operations to complete the test of all the internal units of the IP core. 10、根据权利要求9所述的集成电路片上系统中故障的测试方法，其特征在于若某IP核的DFT方法为扫描法，除通过并行测试总线(2)完成对应IP核测试码和测试响应的输入输出外，还需通过串行测试总线(1)和该IP核的边缘封装单元链路(3)完成IP核原始输入输出端口相应测试码和测试响应的输入输出；根据IP核选择译码单元(5)产生的IP核选择信号，在选中某一IP核的同时，也选中相应的边缘封装单元链路，并与时钟控制单元(4)一起作用，屏蔽其它IP核的测试时钟和其它边缘封装单元链路的测试时钟，高阻其它IP核DFT接口中的输入输出端口和其它边缘封装单元链路的输入输出端口，使其它IP核和边缘封装单元链路均处于休眠状态，进而使被选中IP核进行单独测试的同时，其边缘封装单元链路也独立使用串行测试总线(1)和测试时钟(WCLK)；通过此边缘封装单元链路实现IP核原始输入端口测试码的输入和IP核原始输出端口测试响应的输出。10, the test method of fault in integrated circuit system on chip according to claim 9, it is characterized in that if the DFT method of certain IP core is scanning method, except completing corresponding IP core test code and test response by parallel test bus (2) In addition to the input and output of the IP core, it is also necessary to complete the input and output of the corresponding test code and test response of the original input and output ports of the IP core through the serial test bus (1) and the edge packaging unit link (3) of the IP core; The IP core selection signal generated by the code unit (5) selects the corresponding edge encapsulation unit link while selecting a certain IP core, and works together with the clock control unit (4) to shield the test clocks and signals of other IP cores. The test clocks of other edge encapsulation unit links, the input and output ports in the DFT interface of other high-impedance IP cores and the input and output ports of other edge encapsulation unit links make other IP cores and edge encapsulation unit links all in a dormant state, and then When the selected IP core is tested separately, its edge encapsulation unit link also independently uses the serial test bus (1) and the test clock (WCLK); realizes the original input port test code of the IP core by this edge encapsulation unit link Input and output of the IP core raw output port test response. 11、根据权利要求8所述的集成电路片上系统中故障的测试方法，其特征在于所述的IP核核间连线故障的测试寻访机制(7)是每个IP核边缘封装单元链路(3)都与串行测试总线(1)相连；根据IP核选择译码单元(5)产生的IP核选择信号，在选中某一IPi核的同时，也选中相应的边缘封装单元链路(3i)，并与时钟控制单元(4)一起作用，屏蔽其它边缘封装单元链路的测试时钟，高阻其它边缘封装单元链路的输入输出端口，使其它边缘封装单元链路处于休眠状态，进而使被选中边缘封装单元链路能单独使用串行测试总线(1)和测试时钟(WCLK)：此时，首先通过串行测试总线(1)的WSI端口对该边缘封装单元链路3i加入相应的IP核核间连线故障测试码，并将此测试码移位至边缘封装单元链路3i的最后一个边缘封装单元；其次，选中IPi+1核的边缘封装单元链路(3i+1)，将IPi核边缘封装单元链路3i通过互连线传送来得信号移位至串行测试总线(1)的WSO端口；最后，对从WSO端口获得的数据进行分析，判断IPi核至IPi+1核传输方向的连线故障情况；因为IP核核间连线上信号的传输方向是双向的，对于由IPi +1核至IPi核传输方向的核间连线故障测试，其是一逆过程；首先，选中IPi+1核的边缘封装单元链路(3i+1)，通过串行测试总线(1)的WSI端口对其加入相应的IP核核间连线故障测试码，并将此测试码移位至边缘封装单元链路3i+1的最后一个边缘封装单元；其次，选中IPi核的边缘封装单元链路(3i)，将IPi+1核边缘封装单元链路3i+1通过互连线传送来得信号移位至串行测试总线(1)的WSO端口；最后，对从WSO端口获得数据进行分析，判断IPi+1核至IPi核传输方向的连线故障情况，这样就完成了IPi核与IPi+1核的核间连线故障测试；重复上述过程，完成全部IP核核间连线故障的测试。11, the method for testing of failure in integrated circuit system on chip according to claim 8, it is characterized in that the test seeking mechanism (7) of wiring failure between described IP core is each IP core edge encapsulation unit link ( 3) are all connected with the serial test bus (1); according to the IP core selection signal produced by the IP core selection decoding unit (5), when selecting a certain IP core, also select the corresponding edge encapsulation unit link ( 3 i ), and work together with the clock control unit (4) to shield the test clocks of other edge packaging unit links, and high-impedance input and output ports of other edge packaging unit links, so that other edge packaging unit links are in a dormant state, And then make the selected edge encapsulation unit link can use serial test bus (1) and test clock (WCLK) separately: at this moment, at first by the WSI port of serial test bus (1) to this edge encapsulation unit link 3 i Add the corresponding IP core inter-core connection failure test code, and shift this test code to the last edge encapsulation unit of the edge encapsulation unit link 3 i ; secondly, select the edge encapsulation unit link of the IP i+1 core ( 3 i+1 ), the signal shifted by the IP i core edge packaging unit link 3 i through the interconnection line is transferred to the WSO port of the serial test bus (1); finally, the data obtained from the WSO port is analyzed, Judging the connection failure of the transmission direction from IP i core to IP i+1 core; because the transmission direction of the signal on the connection between IP cores is bidirectional, for the inter-core transmission direction from IP i +1 core to IP i core The connection fault test is a reverse process; first, select the edge packaging unit link (3 i+1 ) of the IP i+1 core, and add the corresponding IP core to it through the WSI port of the serial test bus (1) Inter-core connection failure test code, and shift this test code to the last edge packaging unit of edge packaging unit link 3 i+1 ; secondly, select the edge packaging unit link (3 i ) of IP i core, and place The IP i+1 core edge packaging unit link 3 i+1 shifts the signal transmitted through the interconnection line to the WSO port of the serial test bus (1); finally, analyze the data obtained from the WSO port to judge the IP i+ 1 core to IP i -core transmission direction connection failure, thus completing the inter-core connection fault test between IP i core and IP i+1 core; repeat the above process to complete the test of all IP core connection faults . 12、根据权利要求11所述的集成电路片上系统中故障的测试方法，其特征在于所述的IP核核间连线故障的测试码有四种基本码型：111111......、000000......、101010......和010101......；测试码的位数等于IP核选择译码单元(5)所选中IP核的输入输出端口数。12. The method for testing faults in integrated circuit on-chip systems according to claim 11, characterized in that the test codes for the faults in the connection between the IP cores have four basic patterns: 111111..., 000000..., 101010... and 010101...; the number of bits of the test code is equal to the number of input and output ports of the IP core selected by the IP core selection decoding unit (5).
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