CN100518045C - A Method for Realizing Mutual Synchronization of Clocks - Google Patents

Abstract

The method applies a programming logic component FPGA chip and a local high speed working clock, by the method of sampling count, multiple input clocks are counted and measured, the result of the measurement is processed with weight average computation. According the result of the computation and the local high-speed clock, the synchroization clock standard related with the multiple input clocks is copied. This clock standard will be sent to the locked loop of master/slave synchronization to supply the system with the clocks of all frequency.

Description

A Method for Realizing Mutual Synchronization of Clocks

technical field

The invention relates to a clock synchronization method in a communication network, in particular to a clock synchronization method in a mesh topology communication network or a special network with special requirements on node invulnerability.

Background technique

In the communication network of mesh topology, each switching node is in the same position, there is no master-slave distinction between nodes, and the distribution of clocks is a mesh structure. In this case, the generation of clocks of each node is not suitable for master-slave synchronization. way, but should adopt the way of mutual synchronization. Since there is no master node in the mutual synchronization network, there is no situation that the clock of the entire network loses lock after the master node is destroyed. After any node is destroyed, the clock stability can still be maintained, and the reliability is greatly improved.

The principle of traditional mutual synchronization is shown in Figure 1. Usually, the clock of each node is generated by a multi-input phase-locked loop, and the input reference clock signals of other nodes are compared in phase, and their weighted average is taken to control the voltage. Oscillator frequency output, when the system is running normally, the clock source clock of each switching node is always in a dynamic adjustment process, but the adjustment step size is getting smaller and smaller, and finally the whole network clock is stable around a frequency, thus Control the slip code and slip rate within the required range. The biggest problem of the traditional mutual synchronization implementation method is that the software and hardware for its implementation are highly complex, and usually require the participation of CPU and software.

Contents of the invention

The object of the present invention is to solve the above-mentioned problems, and propose a method for realizing mutual synchronization of clocks, which can simply generate mutual synchronous local working clocks.

Technical solution of the present invention:

A method for realizing clock mutual synchronization is characterized in that it adopts a programmable logic device FPGA and a local high-speed working clock, utilizes the high-speed local clock to count and measure a plurality of input reference clock references by sampling and counting, and Perform weighted average calculation on the measurement results, recover a mutually synchronous clock reference related to each input reference clock according to the calculated results and the local high-speed clock, and then send the clock reference to a master-slave synchronization lock in the usual sense Phase loop, master-slave synchronous phase-locked loop multiplies the frequency to generate the synchronous working clock required by the local node switch, thus transforming the complex mutual synchronization process into a simple master-slave synchronization process.

The present invention adopts a programmable logic device FPGA and a local high-speed working clock, completes the measurement of multiple input reference clocks through the method of sampling and counting, performs weighted average calculation on the measurement results, and restores a clock related to each input reference clock. Mutual synchronization clock reference, and then send the clock reference to a master-slave synchronization phase-locked loop in the usual sense to obtain various frequency clocks required by the local system, thus converting the complex mutual synchronization process into simple master-slave synchronization process. The invention provides a method for simply generating mutually synchronous working clocks, which greatly simplifies the complexity of traditional mutually synchronous clock generation, thereby facilitating debugging, production and maintenance.

Description of drawings

Fig. 1 is a schematic diagram of generation of clocks of each node in the traditional mutual synchronization mode.

Fig. 2 is a realization block diagram of generating mutually synchronous local clocks in the present invention.

FIG. 3 is a schematic diagram of sampling and counting of an input reference clock by a high-speed working clock in the present invention.

Fig. 4 is a diagram of a method for generating a mutually synchronous clock reference in the present invention.

Detailed ways

The method for realizing clock mutual synchronization of the present invention is shown in Fig. 2, and it is divided into two parts, programmable logic device FPGA part and traditional master-slave synchronous phase-locked loop part.

The FPGA part mainly uses the high-speed local clock to count and measure multiple input reference clock benchmarks, and performs weighted average calculation on the measurement results. According to the calculated result and the local high-speed clock, a mutually synchronous clock reference related to each input reference clock is recovered. Figure 2 and Figure 3 show the schematic diagrams of the FPGA part to realize the above functions.

The function of the traditional master-slave synchronous phase-locked loop is mainly based on the mutually synchronous clock reference output by the FPGA in Figure 2, and multiplies the frequency to obtain the synchronous working clock required by the local node switch.

In each node device of network communication, the clock reference sent by the system to the local node is usually a lower frequency clock (other high-speed clock references can be converted into a lower frequency clock by a simple frequency division method). A high-speed working clock is used locally to count and measure the period of each input clock reference. In consideration of practical application, the frequency difference between the clock references of each input is very small, in order to improve the resolution of measurement, a method of counting multiple clock cycles (set as M cycles in the present invention) can be used. As shown in Figure 3:

Assuming that the frequency of the high-speed clock is f, the input reference frequencies are: f0+Δf1, f0+Δf2...f0+Δfn, where f=K*f0, then the minimum frequency difference that can be distinguished by clock counting can be calculated by the following formula :

M/f0-M/(f0+Δf1)＝1/f (Formula 1)

inferred:

Δf1＝f0/(M*K-1) (Formula 2)

Considering f>>f0, it can be approximated as:

Δf1≈f0/(M*K) (Formula 3)

From Equation 3, it can be known that by adjusting the values of M and K, the clock difference of any precision can be obtained. Of course, considering the limitation of the working clock rate of the FPGA, the value of K cannot be infinitely increased, and the value of M can be increased. , providing the computational precision of the clock.

Through the above method, it can be obtained: the count value (num0+Δnum_i) of each reference clock reference relative to the high-speed clock sampling within M clock cycles, where num0=M*K, weighted average calculation is performed on all Δnum_i, then The final required value of Δnum can be obtained, and (num0+Δnum) at this time is the count value obtained by high-speed sampling within M cycles of the averaged mutually synchronous clock reference.

A specific example is given below, as a reference for specific design, it is assumed that the frequency of the local working clock is 66MHz, and the input reference clock base is 8KHz. In this example, K=8250, and the value of M is 64, then 64 cycles of 8KHz reference are counted and sampled, and the minimum resolvable frequency difference is about 2ppm. The FPGA in Figure 2 uses Altera's EP1K50FC256-3, and the phase-locked loop uses an ordinary analog phase-locked loop TRU050GCLGA 16.384/2.048 to recover the 2.048M or 16.384M clock required by the system.

A specific example is given below, as a reference for specific design, it is assumed that the frequency of the local working clock is 66MHz, and the input reference clock base is 8KHz. In this example, K=8250, and the value of M is 64, then 64 cycles of 8KHz reference are counted and sampled, and the minimum resolvable frequency difference is about 2ppm. The FPGA in Figure 2 uses Altera's EP1K50FC256-3, and the phase-locked loop uses an ordinary analog phase-locked loop TRU050GCLGA 16.384/2.048 to recover the 2.048M or 16.384M clock required by the system.

From the values of the local high-speed clock f and (num0+Δnum), the mutually synchronous reference clocks can be recovered by the following method. Figure 4 vividly describes the recovery process.

Build a counter with ((M*K)/2+Δnum/2-M) as the cycle threshold value in the FPGA of Figure 2 . The clock input of the counter adopts the local high-speed clock: whenever a rising edge from the local high-speed clock (frequency f) is received, the value of the counter is added to M.

In addition, build a comparator in the FPGA. When the above counter count value is greater than or equal to ((M*K)/2+Δnum/2-M), the current counter value and the cycle threshold are subtracted, and the obtained difference is Value, assigned to the counter as the initial value of the next count. At the same time, another output register is driven to perform a flip, and the value of this output register is the clock reference after the average processing that needs to be obtained. Considering the fluctuation of the network clock, the high-speed clock should continuously sample the clock references of various channels, and periodically update the threshold value of the counter in Figure 4 in real time to ensure that the generated mutual synchronization reference can correctly reflect the current network clock condition.

The mutually synchronous clock reference obtained by the method of the present invention has no restriction on the frequency deviation of the input clock reference in principle, and the correct mutual synchronization reference can be obtained by properly adjusting the values of M and K. In actual application, it is mainly limited by the pulling range of the master-slave synchronous phase-locked loop voltage-controlled crystal oscillator in Figure 2. In the above example, the pulling range of TRU050GCLGA16.384/2.048 is about 50ppm.

Claims (2)

1, a kind of method that realizes the clock mutually synchronization, the high speed operation clock that it is characterized in that its employing a slice programmable logic device and a this locality, utilize local clock at a high speed a plurality of input reference clock benchmark to be carried out count measurement by the method for sample count, and measurement result is weighted average calculating operation, recover a mutually synchronization clock reference relevant according to calculated result with local high-frequency clock with each input reference clock, give a phase-locked loop that the principal and subordinate is synchronous with this mutually synchronization clock reference again, the synchronous frequency multiplication of phase locked loop of principal and subordinate goes out the work clock of the required various frequencies of local node switch, thereby realizes the mutually synchronization process of each input reference clock and local clock;

Wherein, described as follows with the detailed process that local high-frequency clock recovers a mutually synchronization clock reference relevant with each input reference clock according to calculated result: establishing local high-frequency clock is f, the result of weighted average computing is Δ num, in programmable logic device, make up one with ((M*K)/2+ Δ num/2-M) counter as the cycle threshold values, wherein M is the number of clock cycle, K is the multiple of local high-frequency clock frequency based on input reference frequency f 0, local high-frequency clock is adopted in the clock input of counter, when receiving rising edge that local high-frequency clock comes, the value of counter just adds M, in programmable logic device, make up a comparator simultaneously, when the count value of described counter during more than or equal to ((M*K)/2+ Δ num/2-M), drive an output register and carry out once inside out, the value of described output register is the mutually synchronization clock reference relevant with each input reference clock.

2,, it is characterized in that the high-frequency clock of described this locality adopts a plurality of cycles of described a plurality of input reference clock benchmark that it is carried out count measurement by the described a kind of method that realizes the clock mutually synchronization of claim 1.

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