CN100524680C - Semiconductor wafer including semiconductor chips divided by scribe lines and process-monitoring electrode pads formed on the scribe lines - Google Patents
Semiconductor wafer including semiconductor chips divided by scribe lines and process-monitoring electrode pads formed on the scribe lines Download PDFInfo
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- CN100524680C CN100524680C CNB2006800030284A CN200680003028A CN100524680C CN 100524680 C CN100524680 C CN 100524680C CN B2006800030284 A CNB2006800030284 A CN B2006800030284A CN 200680003028 A CN200680003028 A CN 200680003028A CN 100524680 C CN100524680 C CN 100524680C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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Abstract
A semiconductor wafer has scribe lines dividing the semiconductor wafer into a matrix of a plurality of semiconductor chips. The semiconductor wafer includes a polysilicon layer, a poly-metal interlayer insulating film formed on the polysilicon layer, and a first metal wiring layer formed on the poly-metal interlayer insulating film. The semiconductor wafer includes a process-monitor electrode pad formed on a dicing area of the scribe line. The process-monitor electrode pad has a width greater than a width of the dicing area. The process-monitor electrode pad includes a contact hole formed in the poly-metal insulating film for connecting the first metal wiring layer to the poly-silicon layer.
Description
Technical field
The present invention relates to semiconductor wafer, more specifically relate to the semiconductor wafer that has a plurality of semiconductor chips of being divided by scribe line and be formed at the process-monitor electrode on this scribe line.
Background technology
At the typical slice process of semiconductor wafer (section target) that is used for dividing a plurality of semiconductor chips from semiconductor wafer, the annular blade high speed rotating with the diamond particles that for example is attached to it, and contact is on the scribe line that is formed on the semiconductor wafer.By being contacted with the rotating blade on the scribe line, semiconductor wafer is sliced into a plurality of semiconductor chips.In order to obtain better to cut into slices performance, optimize various parameters.These parameters comprise for example blade thickness, blade rotary speed, platform speed and notch depth.
Semiconductor wafer has various films and is formed at hierarchy on the silicon substrate, forms with uniform material with respect to the thickness direction of semiconductor wafer.More specifically, semiconductor wafer comprises the metal line that is formed by metal material, and this metal material mainly comprises aluminum (extensively being used as the wiring of semiconductor chip).The material of this metal line has the characteristic different with the silicon materials of silicon substrate.
In addition, semiconductor wafer has the process monitoring instrument on the scribe line of being located at semiconductor wafer, is used to check the performance of the semiconductor chip of semiconductor wafer.This process monitoring instrument comprises the process-monitor electrode that is used to assess by the electrology characteristic of the semiconductor device of process-monitor.This process-monitor electrode is also formed by metal material.Therefore, in the technology of section semiconductor wafer, comprise that the hierarchy of silicon substrate, dielectric film and metal material is cut into slices.
Figure 15 A and 15B show near the diagram of conventional semiconductor wafer scribe line.Figure 15 A is the plan view of conventional semiconductor wafer.Figure 15 B is the cross section view along Figure 15 A line W-W intercepting.
LOCOS (local oxidation of silicon) oxidation film 17 is formed on the semiconductor substrate 15.BPSG (boron phosphorus silicate glass) film 19 is formed on the LOCOS oxidation film 17.
The first metal wiring layer 21-1 is formed on the bpsg film 19.The first metal wiring layer 21-1 is placed in one and forms in the zone of process-monitor electrode pad 31.In addition, in the zone shown in the figure, the first metal wiring layer 21-1 forms along the annular of semiconductor chip 3 peripheries.
The first interlayer dielectric 23-1 is formed on the bpsg film 19, and also is formed on the first metal wiring layer 21-1.Through hole is formed in the zone that has formed process-monitor electrode pad 31 in the first interlayer dielectric 23-1 on the first metal wiring layer 21-1.In addition, in annular through-hole is formed at the first interlayer dielectric 23-1 on the first metal wiring layer 21-1 along semiconductor chip 3 peripheries.
The second metal wiring layer 21-2 is formed on the first interlayer dielectric 23-1.The second metal wiring layer 21-2 place in the zone that forms process-monitor electrode pad 31 with and through hole in.In addition, in the zone shown in the figure, the second metal wiring layer 21-2 forms annular along semiconductor chip 3 peripheries.
The second interlayer dielectric 23-2 is formed on the first interlayer dielectric 23-1, and also is formed on the second metal wiring layer 21-2.Through hole is formed in the zone that has formed process-monitor electrode pad 31 in the second interlayer dielectric 23-2 on the second metal wiring layer 21-2.In addition, in annular through-hole is formed at the second interlayer dielectric 23-2 on the second metal wiring layer 21-2 along semiconductor chip 3 peripheries.
The 3rd metal wiring layer 21-3 is formed on the second interlayer dielectric 23-2.The 3rd metal wiring layer 21-3 places on the second interlayer dielectric 23-2 in the zone that forms process-monitor electrode pad 31, with and through hole in.In addition, in the zone shown in the figure, the 3rd metal wiring layer 21-3 forms annular along semiconductor chip 3 peripheries on the second interlayer dielectric 23-2 and in this through hole.
Final protective layer 25 be formed at that the second interlayer dielectric 23-2 goes up and the 3rd interlayer wiring layer 21-3 on.The bonding pad opening part is formed in this final protective layer 25 in the zone that forms process-monitor electrode pad 31.Thus, the surface of the 3rd metal wiring layer 21-3 is in and exposes state.
Be positioned at semiconductor chip 3 peripheries neighbouring above-mentioned metal wiring layer 21-1,21-2 and 21-3 and form retaining ring 21 together.
In slice process, a plurality of films that be difficult to usually once to cut into slices (cutting) formed by different materials, and this section is tending towards causing forming the stained problem of metal.Usually, because it is relatively little to be positioned at the process-monitor semiconductor device size of scribe line, be the situation of the blade of 20-50 μ m for for example adopting thickness, this process-monitor semiconductor device can be cut into slices up hill and dale and not have any metal stained.Simultaneously, because the process-monitor electrode pad has the above width of at least 60 μ m, the width of this process-monitor electrode pad will be greater than the thickness (width of break area) of this blade.This causes the stained problem of metal.
Be applied to the situation of the design rule that is called half micron technology of layer 2-3 wiring layer for employing, can overcome the problems referred to above by adjusting slice process.
Yet, continuing in recent years and still, the trend that forms the multi-layer metal wiring layer significantly increases, because semiconductor device fabrication becomes meticulousr size (it is not uncommon for example, making the semiconductor device with 7-8 layer wiring layer).Therefore, be located on the scribe line as the situation of process-monitor electrode pad for the multi-layer metal wiring layer, the metal film that is included in the process-monitor electrode pad causes metal stained.
In addition, continuing in recent years and still, the whole bag of tricks of dielectric film planarization techniques is used to solve the depth of focus problem of using in the photoetching technique situation.The leveling method on dielectric film surface for example can be to use CMP (chemico-mechanical polishing) method, perhaps adopts bpsg film as the film between polysilicon layer and the metal level.Bpsg film is made by CVD (chemical vapour deposition (CVD)) method, and this bpsg film is by boron and phosphorus are covered the dielectric film that forms in the silicon oxide layer.By increasing the concentration of boron and phosphorus, the surface of dielectric film can be by leveling rightly.Therefore increase the concentration of boron and phosphorus to reduce the size of semiconductor device.
Yet the present inventor finds, when the concentration increase of boron in the bpsg film and phosphorus, and bonding the dying down of (more specifically, this bpsg film and be used as aluminium alloy base plate and have between dystectic titanium film) between bpsg film and the titanium film.This is because the increase of boron and phosphorus concentration not only promotes leveling, and has reduced the asperity of bpsg film simultaneously.This has caused the loss of contact area between bpsg film and the metal film.Therefore, meticulous more by increasing the semiconductor device that boron and the concentration of phosphorus makes, then the stained possibility of the metal of generation process-monitor electrode is bigger in slice process.As a result, the section of semiconductor wafer becomes more difficult.
An example that prevents this problem is disclosed in the Japan Patent spy and opens communique No.2005-191334.The Japan Patent spy opens communique No.2005-191334 and discloses a kind of process-monitor electrode pad, and it places semiconductor chip inside, makes the semiconductor device that only is used for process-monitor be placed in scribe line.Therefore, this electrode pad will can not hinder slice process.
Yet, owing to this method places the process-monitor electrode pad in the semiconductor chip, so this semiconductor chip forms big size.This has increased manufacturing cost.Placing this supplemantary electrode pad in the semiconductor chip is key issue, especially for the semiconductor core flake products with a large amount of electrode pads, because the chip size of product is to determine according to the limit of distance between the electrode pad.
Shown in Figure 15 B, the retaining ring that is formed by metal material can place between semiconductor chip and the scribe line, is used for preventing that semiconductor chip inside is in the slice process damaged.Yet by this process-monitor electrode pad is placed semiconductor chip inside, this process-monitor electrode pad need exceed retaining ring and monitor semiconductor device with contact process.This is the task of being difficult to finish, because the part of the retaining ring that is formed by metal material will be cut off undesirably to reach this task.If this part of retaining ring is cut off, then provide the purpose of this retaining ring then to lose.
The Japan Patent spy opens communique No.2005-191334 and also discloses an example, and it places semiconductor chip inside with the process-monitor electrode pad, and not only this process-monitor electrode pad is used for process-monitor but also as the electrode pad of semiconductor chip.
Yet, since do not have usually between the number of being located at the semiconductor chip that is used for process-monitor on the scribe line in each product and the number of electrode pad related, so position that is difficult to adjust the position that places the semiconductor device on the scribe line and is used for the electrode pad of product.In addition, when using the process-monitor device to carry out electrical measurement, the probe that each product needed is separated in this example.In addition, this example and unresolved above-mentioned retaining ring problem.
The Japan Patent spy opens communique No.2005-191334 and also discloses an example, and it places process-monitor electrode pad and semiconductor device in the scribe line, does not still put in the break area (cuing off the zone) at scribe line.
Yet this example requires the scribing live width.This has reduced to cut off from semiconductor wafer the number of the semiconductor chip of (section).As a result, manufacturing cost increases.
Summary of the invention
Overall goal of the present invention provides a kind of semiconductor wafer, and it has been eliminated basically because the restriction of correlation technique and the one or more problems due to the shortcoming.
The features and advantages of the present invention will state in following specification, and part becomes apparent from this specification and accompanying drawing, perhaps can put into practice the present invention and known by the instruction that provides according to specification.Target of the present invention and other feature and advantage can realize and obtain by the semiconductor wafer of pointing out particularly with comprehensive, clear, succinct and strict term in specification, so that those of ordinary skills can put into practice the present invention.
In order to obtain these and other advantages according to the object of the invention, describe with generality as here embodied, embodiments of the invention provide a kind of semiconductor wafer of scribe line that it is divided into the matrix of a plurality of semiconductor chips that has, this semiconductor wafer comprises polysilicon layer, be formed at the polysilicon-metal interlevel dielectric film on this polysilicon layer, and be formed at first metal wiring layer on this polysilicon-metal interlevel dielectric film, this semiconductor wafer is characterised in that and comprises: be formed at the process-monitor electrode pad on the break area of this scribe line, the width of this process-monitor electrode pad is greater than the width of this break area, and this process-monitor electrode pad comprises and is formed at the contact hole that is used for this first metal wiring layer is connected to this polysilicon layer in this polysilicon-metal-oxide.
In semiconductor wafer according to the present invention, this contact hole can not be formed in this break area.
In semiconductor wafer according to the present invention, this semiconductor wafer can further comprise second wiring layer that is formed on this first wiring layer, and wherein this first wiring layer is not formed in this break area.
In the semiconductor wafer according to the embodiment of the invention, this polysilicon-metal interlevel dielectric film can be a bpsg film.
In addition, the invention provides a kind of semiconductor wafer of scribe line that it is divided into the matrix of a plurality of semiconductor chips that has, this semiconductor wafer with muti-layered metallic line structure comprises that three-layer metal wiring layer, this semiconductor wafer are characterised in that and comprise at least: be formed at the process-monitor electrode pad on the break area of this scribe line, the width of this process-monitor electrode pad is greater than the width of this break area, and this process-monitor electrode pad comprises the metal wiring layer of one deck at least of this muti-layered metallic line structure; Wherein the metal wiring layer that descends most of this multi-layer metal wiring layer structure is not formed in this process-monitor electrode pad.
In the semiconductor wafer according to the embodiment of the invention, this process-monitor electrode pad can only comprise the metal wiring layer of going up most of this Miltilayer wiring structure.
In the semiconductor wafer according to the embodiment of the invention, this process-monitor electrode pad can comprise going up metal wiring layer most and be formed at this and going up metal wiring layer under the metal wiring layer most of this muti-layered metallic line structure.
In the semiconductor wafer according to the embodiment of the invention, all metal wiring layers of this muti-layered metallic line structure are not formed at below the metal wiring layer of this process-monitor electrode pad in the break area of scribe line.
In the semiconductor wafer according to the embodiment of the invention, this muti-layered metallic line structure can comprise bpsg film, and wherein the metal wiring layer that descends most of this muti-layered metallic line structure is formed on this bpsg film.
Description of drawings
Figure 1A is near the plan view that illustrates according to the scribe line of the semiconductor wafer of first embodiment of the invention;
Figure 1B is the cross section view along the line A-A intercepting of Figure 1A;
Fig. 2 is the plan view that illustrates according to the general structure of the semiconductor wafer of the embodiment of the invention;
Fig. 3 A is the plan view that illustrates according to the part in the process-monitor zone in the scribe line of the embodiment of the invention;
Fig. 3 B is the cross section view along the B-B intercepting of Fig. 3 A line;
Fig. 4 A is the photo of the semiconductor wafer of the polysilicon layer that is formed at process-monitor electrode pad below according to having of the embodiment of the invention and contact hole;
Fig. 4 B is the photo of conventional semiconductor wafer;
Fig. 5 A is near the plan view that illustrates according to the scribe line of the semiconductor wafer of another embodiment of the present invention;
Fig. 5 B is the cross section view along the C-C intercepting of Fig. 5 A line;
Fig. 5 C is the cross section view along the D-D intercepting of Fig. 5 A line;
Fig. 6 A is near the plan view that illustrates according to the scribe line of the semiconductor wafer of another embodiment of the present invention;
Fig. 6 B is the cross section view along the line E-E intercepting of Fig. 6 A;
Fig. 6 C is the cross section view along the line F-F intercepting of Fig. 6 A;
Fig. 7 A is near the plan view that illustrates according to the scribe line of the semiconductor wafer of another embodiment of the present invention;
Fig. 7 B is the cross section view along the line G-G intercepting of Fig. 7 A;
Fig. 7 C is the cross section view along the line H-H intercepting of Fig. 7 A;
Fig. 8 A is near the plan view that illustrates according to the scribe line of the semiconductor wafer of another embodiment of the present invention;
Fig. 8 B is the cross section view along the line I-I intercepting of Fig. 8 A;
Fig. 8 C is the cross section view along the line J-J intercepting of Fig. 8 A;
Fig. 9 A is near the plan view that illustrates according to the scribe line of the semiconductor wafer of another embodiment of the present invention;
Fig. 9 B is the cross section view along the line K-K intercepting of Fig. 9 A;
Fig. 9 C is the cross section view along the line L-L intercepting of Fig. 9 A;
Figure 10 A is near the plan view that illustrates according to the scribe line of the semiconductor wafer of another embodiment of the present invention;
Figure 10 B is the cross section view along the line M-M intercepting of Figure 10 A;
Figure 10 C is the cross section view along the line N-N intercepting of Figure 10 A;
Figure 11 A is near the plan view that illustrates according to the scribe line of the semiconductor wafer of another embodiment of the present invention;
Figure 11 B is the cross section view along the line O-O intercepting of Figure 11 A;
Figure 11 C is the cross section view along the line P-P intercepting of Figure 11 A;
Figure 12 A is near the plan view that illustrates according to the scribe line of the semiconductor wafer of another embodiment of the present invention;
Figure 12 B is the cross section view along the line Q-Q intercepting of Figure 12 A;
Figure 12 C is the cross section view along the line R-R intercepting of Figure 12 A;
Figure 13 A is near the plan view that illustrates according to the scribe line of the semiconductor wafer of another embodiment of the present invention;
Figure 13 B is the cross section view along the line R-R intercepting of Figure 13 A;
Figure 13 C is the cross section view along the line S-S intercepting of Figure 13 A;
Figure 14 A is near the plan view that illustrates according to the scribe line of the semiconductor wafer of another embodiment of the present invention;
Figure 14 B is the cross section view along the line U-U intercepting of Figure 14 A;
Figure 14 C is the cross section view along the line V-V intercepting of Figure 14 A;
Figure 15 A is near the plan view that illustrates according to the scribe line of conventional semiconductor wafer;
Figure 15 B is the cross section view along the line W-W intercepting of Figure 15 A;
Figure 16 A is near the plan view that illustrates according to the scribe line of the semiconductor wafer of second embodiment of the invention;
Figure 16 B is the cross section view along the line A-A intercepting of Figure 16 A;
Figure 17 is near the plan view that illustrates according to the scribe line of the semiconductor wafer of second embodiment of the invention;
Figure 18 A is the plan view that illustrates according to the part in process-monitor zone in the scribe line of one embodiment of the invention;
Figure 18 B is the cross section view along the line B-B intercepting of Figure 18 A;
Figure 19 A is the plan view that illustrates according to the part in process-monitor zone in the scribe line of another embodiment of the present invention;
Figure 19 B is the cross section view along the line C-C intercepting of Figure 19 A;
Figure 20 A is the plan view that illustrates according to the part in process-monitor zone in the scribe line of another embodiment of the present invention;
Figure 20 B is the cross section view along the line D-D intercepting of Figure 20 A;
Figure 20 C is the cross section view along the line E-E intercepting of Figure 20 A;
Figure 21 A is the plan view that illustrates according to the part in process-monitor zone in the scribe line of another embodiment of the present invention;
Figure 21 B is the cross section view along the line F-F intercepting of Figure 21 A; And
Figure 21 C is the cross section view along the line G-G intercepting of Figure 21 A.
Embodiment
Describe the present invention in detail based on embodiment shown in the figure.
[first embodiment]
Figure 1A and 1B are the indicative icon that is used to describe according to the semiconductor wafer 1 of the embodiment of the invention.More specifically, Figure 1A is near the plan view of scribe line that semiconductor wafer 1 is shown, and Figure 1B is the cross section view along the line A-A intercepting of Figure 1A.Fig. 2 is the plan view that illustrates according to the general structure of the semiconductor wafer 1 of the embodiment of the invention.Fig. 3 A and 3B are the indicative icon that is used to describe according to the part that places the process-monitor device on the scribe line of the embodiment of the invention.More specifically, Fig. 3 A is the plan view that the part of this process-monitor device is shown, and Fig. 3 B is the cross section view along the B-B intercepting of Fig. 3 A line.Semiconductor wafer 1 according to the embodiment of the invention has the three-layer metal wire structures.
As shown in Figure 2, semiconductor wafer 1 has a plurality of semiconductor chips 3 of being divided and be arranged to matrix by scribe line 5.The width of scribe line 5 is 100 μ m in this example.Shown in Figure 1A, scribe line 5 has process-monitor zone 7, is furnished with a plurality of semiconductor devices (hereinafter being called " process-monitor semiconductor device ") 9 that are used for process-monitor and a plurality of electrode pads (hereinafter being called " process-monitor electrode pad ") 11 that are used for process-monitor on this process-monitor zone 7.The planar dimension of process-monitor electrode pad 11 for example is 70 μ m * 70 μ m.The central area of scribe line 5 is the zone (hereinafter being called " break area 13 ") of cut into slices (cutting) in slice process.The width of break area 13 be substantially equal to be used to the to cut into slices thickness of blade of semiconductor wafer 1.For example, be the situation of the blade of 20-40 μ m for the used thickness scope, the width of break area is 20-40 μ m.
The cross section structure of semiconductor wafer 1 then, is described with reference to Figure 1B.In this example, LOCOS oxidation film 17 is formed on the semiconductor substrate 15 that is formed by silicon materials.Polysilicon layer 18 is formed on the LOCOS oxidation film 17 in the zone that will form process-monitor electrode pad 11 (hereinafter being called " the process-monitor electrode pad forms the zone ") 1000.Bpsg film 19 (that is polysilicon-metal interlevel dielectric film) is formed on the LOCOS oxidation film 17 that comprises the zone that is formed with polysilicon layer 18.
A plurality of contact holes 20 are formed in the bpsg film 19 in this process-monitor electrode pad forms zone 1000.In this example, 2500 contact holes 20 (vertical 50 holes * horizontal 50 holes) are formed in the bpsg film 19 in the process-monitor electrode pad forms zone 1000.For convenience former of contact hole shown in Figure 1B 20 thereby be omitted.In this example, each contact hole 20 has the area of plane of 0.4 μ m * 0.4 μ m.It is described that yet the number, layout and the size that are noted that contact hole 20 are not limited to this example.
In the process-monitor electrode pad formed zone 1000, the first metal wiring layer 21-1 was formed in the contact hole 20 that reaches bpsg film 19 on the bpsg film 19.In addition, in the zone shown in the figure, the first metal wiring layer 21-1 forms annular along the periphery of semiconductor chip 3.The first metal wiring layer 21-1 also can be formed at other zones of semiconductor wafer 1 and go up (not shown among Figure 1B).The first metal wiring layer 21-1 comprises high melting point metal film (for example, titanium film), is formed with aluminium alloy film (for example, AlSiCu film) on this high melting point metal film.
The first interlayer dielectric 23-1 is formed on the bpsg film 19 that comprises the zone that is formed with the first metal wiring layer 21-1 on it.The first interlayer dielectric 23-1 has and comprises for example hierarchy of NSG (undoped silicate glass) film, SOG (spin-coating glass) film and NSG film.In the process-monitor electrode pad formed zone 1000, through hole was formed in the first interlayer dielectric 23-1 on the first metal wiring layer 21-1.In annular through-hole also is formed at the first interlayer dielectric 23-1 on the first metal wiring layer 21-1 along semiconductor chip 3 peripheries.
In the process-monitor electrode pad forms zone 1000, the second metal wiring layer 21-2 be formed at that the first interlayer dielectric 23-1 goes up and the through hole of the first interlayer dielectric 23-1 in.In addition, in the zone shown in the figure, the second metal wiring layer 21-2 forms annular along semiconductor chip 3 peripheries.The second metal wiring layer 21-2 also can be formed at other zones of semiconductor wafer 1 and go up (not shown among Figure 1B).The second metal wiring layer 21-2 also can for example be formed by the titanium film that is formed with the AlSiCu film on it.
The second interlayer dielectric 23-2 is formed on the first interlayer dielectric 23-1 that comprises the zone that is formed with the second metal wiring layer 21-2 on it.The second interlayer dielectric 23-2 also has and comprises for example hierarchy of NSG film, sog film and NSG film.In the process-monitor electrode pad formed zone 1000, through hole was formed in the second interlayer dielectric 23-2 on the second metal wiring layer 21-2.In annular through-hole also is formed at the second interlayer dielectric 23-2 on the second metal wiring layer 21-2 along semiconductor chip 3 peripheries.
In the process-monitor electrode pad forms zone 1000, the 3rd metal wiring layer 21-3 be formed at that the second interlayer dielectric 23-2 goes up and the through hole of the second interlayer dielectric 23-2 in.In addition, in the zone shown in the figure, the 3rd metal wiring layer 21-3 forms annular along semiconductor chip 3 peripheries.The 3rd metal wiring layer 21-3 also can be formed at other zones of semiconductor wafer 1 and go up (not shown among Figure 1B).The 3rd metal wiring layer 21-3 also can for example be formed by the titanium film that is formed with the AlSiCu film on it.
Comprise that along what semiconductor chip 3 peripheries formed first, second hierarchy with the 3rd metal wiring layer 21-1,21-2 and 21-3 is the retaining ring 21 that is used for protective semiconductor chip 3 inside.
LOCOS oxidation film 17, bpsg film 19, the first interlayer dielectric 23-1, the second interlayer dielectric 23-2 and final diaphragm 25 are all removed two end (along the Width of scribe line 5) with ribbon-like manner.In this example, the width that is removed the end is 10 μ m.By remove two ends of LOCOS oxidation film 17, bpsg film 19, the first interlayer dielectric 23-1, the second interlayer dielectric 23-2 and final diaphragm 25 along scribe line 5 Widths, can prevent that the crackle that is formed in the interlayer dielectric from arriving semiconductor chip 3 when this break area 13 of section.Yet notice that semiconductor wafer 1 of the present invention is not limited to remove along scribe line 5 Widths the structure of two ends.
Then, with reference to figure 3A and 3B process-monitor zone 7 is described.In Fig. 3 B, omitted being included in the description of bpsg film 19, the first interlayer dielectric 23-1, the second interlayer dielectric 23-2 and final diaphragm 25 in the semiconductor chip 3.
In Fig. 3 A, two active area 27a, 27b form source electrode and the drain electrode on the semiconductor substrate region surface that is centered on by LOCOS oxidation film 17.The gate electrode of being made by polysilicon 29 is formed between two active area 27a, the 27b on the semiconductor substrate in the zone by gate insulating film.Two active area 27a, 27b and gate electrode 29 form transistor (that is, the process-monitor semiconductor device 9) together.This transistor is positioned at break area and the different part of process-monitor electrode pad 11 place parts.In Fig. 3 A example shown, transistor is between process-monitor electrode pad 11a and process-monitor electrode pad 11b.The two ends of polygate electrodes 29 form and extend across LOCOS oxidation film 17.
The first metal wiring layer 21-1a of process- monitor electrode pad 11a, 11b, 11c, 21-1b, 21-1c are formed on the bpsg film 19 continuously.The first metal wiring layer 21-1a, 21-1b, 21-1c have the width range of 2 μ m to 3 μ m.Although first metal wiring layer 21-1a that extends from process- monitor electrode pad 11a and 11b and the part of 21-1b are positioned at break area 13 (as shown in Figure 3A), the position of the first metal wiring layer 21-1a and 21-1b is not limited to position shown in Fig. 3 A.
An end that is positioned at the first metal wiring layer 21-1a of active area 27a top is electrically connected to active area 27a by the contact hole 20 that is formed at bpsg film 19.The other end of the first metal wiring layer 21-1a is connected to process-monitor electrode pad 11a (the first metal wiring layer 21-1a of process-monitor electrode pad 11a).
An end that is positioned at the first metal wiring layer 21-1b of active area 27b top is electrically connected to active area 27b by the contact hole 20 that is formed at bpsg film 19.The other end of the first metal wiring layer 21-1b is connected to process-monitor electrode pad 11b (the first metal wiring layer 21-1b of process-monitor electrode pad 11b).
An end that is positioned at the first metal wiring layer 21-1c of gate electrode 29 tops is electrically connected to gate electrode 29 by the contact hole 20 that is formed at bpsg film 19.The other end of the first metal wiring layer 21-1c is connected to process-monitor electrode pad 11c (the first metal wiring layer 21-1c of process-monitor electrode pad 11c).
Forming in the zone 1000 with process- monitor electrode pad 11a, 11b and the corresponding process-monitor electrode pad of 11c, the second metal wiring layer 21-2a, 21-2b, 21-2c are formed on the first interlayer dielectric 23-1, and the 3rd metal wiring layer 21-3a, 21-3b, 21-3c are formed on the second interlayer dielectric 23-2.
Be formed in the bpsg film 19 below the process-monitor electrode pad 11 (11a, 11b, 11c) owing to be used to connect the contact hole 20 of the first metal wiring layer 21-1 (21-1a, 21-1b, 21-1c) and polysilicon layer 18, the contact area of bpsg film 19 upper surfaces and the first metal wiring layer 21-1 (21-1a, 21-1b, 21-1c) can reduce.In addition, can prevent that the first metal wiring layer 21-1 (21-1a, 21-1b, 21-1c) from peeling off, even be positioned at process-monitor electrode pad 11 (11a, 11b, 11c) under the situation of break area 13 of scribe line 5.Can prevent that thus metal is stained.Yet note, the invention is not restricted to make to descend most metal wiring layer to be formed at the structure on the bpsg film.
In addition, because process-monitor electrode pad 11 is arranged to comprise the break area of scribe line 5, therefore need not to increase the size of semiconductor chip 3 or the width of scribe line 5.
Because a plurality of contact holes 20 are formed in the bpsg film 19 of process-monitor electrode pad 11 belows, bpsg film 19 can contact by contact hole 20 inwalls with the first metal wiring layer 21-1.Can prevent peeling off of the first metal wiring layer 21-1 thus.
In addition, compare with the process-monitor electrode pad that only has the single metal wiring layer that is formed in the superiors, process-monitor electrode pad 11 more may prevent test during (monitoring) semiconductor wafer probe pierce through the problem of process-monitor electrode pad.This is to be formed by three metal wiring layer 21-1,21-2,21-3 because of process-monitor electrode pad 11.
Fig. 4 A and 4B photo for after the break area of section semiconductor wafer, being absorbed.Fig. 4 A is the photo of the semiconductor wafer of the polysilicon layer that is formed at process-monitor electrode pad below according to having of the embodiment of the invention and contact hole.Fig. 4 B is the photo of conventional semiconductor wafer.
Fig. 4 A shows that process-monitor electrode pad 11 does not all peel off on the semiconductor wafer 1 of the present invention.Yet the process-monitor electrode pad 11 that Fig. 4 B shows more than 90% peels off, and considerably less process-monitor electrode pad 11 remains on the semiconductor wafer.
Therefore, the present invention can reduce to form in the process-monitor electrode pad the stained possibility of metal.
Although contact hole 20 is formed in the break area 13 in the above embodiment of the present invention, contact hole 20 can alternatively be formed at the zone interior (seeing Fig. 5 A-5C) of break area 13 outsides.Because the first metal wiring layer 21-1 is connected to polysilicon layer 18 by the contact hole 20 that is formed in the zone (hereinafter being called " zones of different ") outside the break area 13, after slice process, do not find peeling off of the first metal wiring layer 21-1 in this zones of different.In addition, because the first metal wiring layer 21-1 in the break area 13 is thoroughly crushed, therefore can in break area, not find peeling off of the first metal wiring layer 21-1.In addition, since near the stress that are formed at the process-monitor electrode pad 11 due to the first metal wiring layer 21-1 in the contact hole 20 can reduce.Thus, can further reduce the stained formation of metal.
Except forming in the zone of break area 13 outsides (zones of different) the contact hole 20, polysilicon layer 18 can also be formed in this zones of different (seeing Fig. 6 A-6C).Because the first metal wiring layer 21-1 is connected to polysilicon layer 18 by the contact hole 20 that is formed in this zones of different, after slice process, can not find peeling off of the first metal wiring layer 21-1 in this zones of different.In addition, because the first metal wiring layer 21-1 in the break area 13 is thoroughly crushed, therefore can in break area, not find peeling off of the first metal wiring layer 21-1.In addition, when section, can reduce by near the stress the process-monitor electrode pad 11 due to the polysilicon layer 18.Thus, can further reduce the stained formation of metal.
Except forming in the zone of break area 13 outsides (zones of different) the contact hole 20, the first metal wiring layer 21-1 can also be formed in this zones of different (seeing Fig. 7 A-7C).Compare with the situation in the first metal wiring layer 21-1 is formed at break area 13, near the stress the process-monitor electrode pad 11 that is caused by the first metal wiring layer 21-1 when section can reduce.Thus, can further reduce the stained formation of metal.
In addition, as mentioned above, between bpsg film and titanium film (metal substrate), exist weak bonding.For example, have the situation of the combination of the weak bonding polysilicon-metal interlevel dielectric film and first metal wiring layer, can reduce the stained formation of metal for use.That is to say, comprise that for polysilicon-metal interlevel dielectric film the bpsg film 19 and the first metal wiring layer 21-1 comprise the situation of the substrate of titanium film, can reduce the stained formation of metal.
Except forming in the zone of break area 13 outsides (zones of different) the first metal wiring layer 21-1, shown in Fig. 7 A-7C, polysilicon layer 18 also can be formed in this zones of different (seeing Fig. 8 A-8C).When section, can reduce by near the stress the process-monitor electrode pad 11 due to the polysilicon layer 18.Thus, can further reduce the stained formation of metal.
Although the above embodiment of the present invention is described as having a plurality of contact holes 20 that are formed at process-monitor electrode pad 11 belows, can form single contact hole 20 but not a plurality of contact hole 20 (seeing Fig. 9 A-9C).
The exemplary configurations of employing shown in Fig. 9 A-9C, the area of the first metal wiring layer 21-1 contact bpsg film 19 of process-monitor electrode pad 11 can reduce.Correspondingly, even place situation on the break area 13 of scribe line 5 for process-monitor electrode pad 11, can prevent that still this first metal wiring layer 21-1 from peeling off.Can reduce the stained formation of metal thus.
In addition, because the process-monitor electrode pad 11 shown in Fig. 9 A-9C is arranged in the break area 13 of scribe line 5, the width of the size of semiconductor chip 3 and scribe line 5 can reduce.
In addition, realize the contact between the bpsg film 19 and the first metal wiring layer 21-1 and the big area of the first metal wiring layer 21-1 will be contacted with polysilicon layer 18 that by the inwall of contact hole 20 then the exemplary configurations shown in Fig. 9 A-9C can prevent peeling off of the first metal wiring layer 21-1.
Although the exemplary configurations of Fig. 9 A-9C has the contact hole 20 in break area of being formed at 13, contact hole 20 alternatively can be formed in the zone (zones of different) of break area 13 outsides, shown in Figure 10 A-10C.Because the first metal wiring layer 21-1 is connected to polysilicon layer 18 by the contact hole 20 that is formed in the zone (zones of different) outside the break area 13, after slice process, can not find peeling off of the first metal wiring layer 21-1 in this zones of different.In addition, because the first metal wiring layer 21-1 in the break area 13 is thoroughly crushed, therefore can in break area, not find peeling off of the first metal wiring layer 21-1.In addition, since near the stress that are formed at the process-monitor electrode pad 11 due to the first metal wiring layer 21-1 in the contact hole 20 can reduce.Thus, can further reduce the stained formation of metal.
Except forming in the zone of break area 13 outsides (zones of different) the contact hole 20, polysilicon layer 18 can also be formed in this zones of different (seeing Figure 11 A-11C).Because the first metal wiring layer 21-1 is connected to polysilicon layer 18 by the contact hole 20 that is formed in this zones of different, after slice process, can not find peeling off of the first metal wiring layer 21-1 in this zones of different.In addition, because the first metal wiring layer 21-1 in the break area 13 is thoroughly crushed, therefore can in break area, not find peeling off of the first metal wiring layer 21-1.In addition, when section, can reduce by near the stress the process-monitor electrode pad 11 due to the polysilicon layer 18.Thus, can further reduce the stained formation of metal.
Except forming in the zone of break area 13 outsides (zones of different) the contact hole 20, the first metal wiring layer 21-1 can also be formed in this zones of different (seeing Figure 12 A-12C).Compare with the situation in the first metal wiring layer 21-1 is formed at break area 13, near the stress the process-monitor electrode pad 11 that is caused by the first metal wiring layer 21-1 when section can reduce.Thus, can further reduce the stained formation of metal.
In addition, have the situation of the combination of the weak bonding polysilicon-metal interlevel dielectric film and first metal wiring layer, can reduce the stained formation of metal for use.That is to say, comprise that for polysilicon-metal interlevel dielectric film the bpsg film 19 and the first metal wiring layer 21-1 comprise the situation of the substrate of titanium film, can reduce the stained formation of metal.
Except forming in the zone of break area 13 outsides (zones of different) the first metal wiring layer 21-1, shown in Figure 12 A-12C, polysilicon layer 18 also can be formed in this zones of different (seeing Figure 13 A-13C).When section, can reduce by near the stress the process-monitor electrode pad 11 due to the polysilicon layer 18.Thus, can further reduce the stained formation of metal.
Although the above embodiment of the present invention has the first metal wiring layer 21-1 that is formed at contact hole 20 inside, the invention is not restricted to this structure.For example, different with first metal wiring layer 21-1 metal materials can be formed at contact hole 20 inside (seeing Figure 14 A-14C).For example, the tungsten material can be formed at contact hole 20 inside.
The exemplary configurations of employing shown in Figure 10 A-14C, the area of the first metal wiring layer 21-1 contact bpsg film 19 of process-monitor electrode pad 11 can reduce.Correspondingly, even place situation on the break area 13 of scribe line 5 for process-monitor electrode pad 11, can prevent that still this first metal wiring layer 21-1 from peeling off.Can reduce the stained formation of metal thus.
In addition, because process-monitor electrode pad 11 is arranged in the break area 13 of scribe line 5, the width of the size of semiconductor chip 3 and scribe line 5 can reduce.
The said structure that forms the metal material different with the first metal wiring layer 21-1 in (a plurality of) contact hole 20 can be applied to the exemplary configurations shown in Fig. 5 A-13C.In these cases, can prevent peeling off of the first metal wiring layer 21-1 according to the mode identical with Fig. 5 A-13C exemplary configurations.Can reduce the stained formation of metal thus.
Although the above embodiment of the present invention has the second metal wiring layer 21-2 in break area of being formed at 13, the second metal wiring layer 21-2 alternatively can be formed at the regional (not shown) of break area 13 outsides.Correspondingly, when slice process monitoring electrode pad 11, only the 3rd metal wiring layer 21-3 that goes up most of metal wiring layer 21 is cut into slices.Therefore can reduce the stained formation of metal.
Although the above embodiment of the present invention has the semiconductor wafer 1 of the three-layer metal of being formed with wiring layer structure (that is, having the structure of three metal wiring layers), semiconductor wafer 1 of the present invention is not limited to this structure.For example, semiconductor wafer 1 can have single metal routing layer structure, bimetallic wiring layer structure or have the structure of metal wiring layer more than four layers.
[second embodiment]
Figure 16 A and 16B are for describing the indicative icon according to the semiconductor wafer 101 of the embodiment of the invention.More specifically, Figure 16 A is near the plan view that illustrates the scribe line 105 of semiconductor wafer 101, and Figure 16 B be the cross section view that intercepts along Figure 16 A line A-A.Figure 17 is the plan view that illustrates according to the general structure of the semiconductor wafer 101 of the embodiment of the invention.Figure 18 A and 18B are the indicative icon that places the process-monitor device on the scribe line that is used to describe according to the embodiment of the invention.More specifically, Figure 18 A is the plan view that the part of process-monitor device is shown, and Figure 18 B is the cross section view along Figure 18 A line B-B intercepting.Semiconductor wafer 101 according to the embodiment of the invention has three-layer metal wiring layer structure.
As shown in figure 17, semiconductor wafer 101 has a plurality of semiconductor chips 103 of being divided and be arranged to matrix by scribe line 105.The width of scribe line 105 is 100 μ m in this example.Shown in Figure 16 A, scribe line 105 has process-monitor zone 107, is furnished with a plurality of semiconductor devices (hereinafter being called " process-monitor semiconductor device ") 109 that are used for process-monitor and a plurality of electrode pads (hereinafter being called " process-monitor electrode pad ") 111 that are used for process-monitor on this process-monitor zone 107.The planar dimension of process-monitor electrode pad 111 for example is 70 μ m * 70 μ m.The central area of scribe line 105 is the zone (hereinafter being called " break area 113 ") of cut into slices (cutting) in slice process.The width of break area 113 be substantially equal to be used to the to cut into slices thickness of blade of semiconductor wafer 101.For example, be the situation of the blade of 20-40 μ m for the used thickness scope, the width of break area 113 is 20-40 μ m.
The cross section structure of semiconductor wafer 101 then, is described with reference to Figure 16 B.In this example, LOCOS oxidation film 117 is formed on the semiconductor substrate 115 that is formed by silicon materials.Bpsg film 119 (that is polysilicon-metal interlevel dielectric film) is formed on the LOCOS oxidation film 117.
The first metal wiring layer 121-1 is formed on the bpsg film 119.The first metal wiring layer 121-1 is not formed at process-monitor electrode pad 111 belows.In zone shown in Figure 16 B, the first metal wiring layer 121-1 forms annular along the periphery of semiconductor chip 103.The first metal wiring layer 121-1 also can be formed at other zones of semiconductor wafer 101 and go up (not shown among Figure 16 B).The first metal wiring layer 121-1 comprises high melting point metal film (for example, titanium film), is formed with aluminium alloy film (for example, AlSiCu film) on this high melting point metal film.
The first interlayer dielectric 123-1 is formed on the bpsg film 119 that comprises the zone that is formed with the first metal wiring layer 121-1 on it.The first interlayer dielectric 123-1 has and comprises for example hierarchy of NSG (silicate glass undopes) film, SOG (spin-coating glass) film and NSG film.In annular through-hole is formed at the first interlayer dielectric 123-1 on the first metal wiring layer 121-1 along semiconductor chip 103 peripheries.
The second metal wiring layer 121-2 is formed on the first interlayer dielectric 123-1.The second metal wiring layer 121-2 is formed in the zone that is formed with process-monitor electrode pad 111.In addition, in the zone shown in the figure, the second wiring layer 121-2 is formed on first interlayer dielectric and in the through hole of the first interlayer dielectric 123-1.The second metal wiring layer 121-2 also is formed at other zones (not shown among Figure 16 B) of semiconductor wafer 101.The second metal wiring layer 121-2 also can be formed by the titanium film that for example is formed with the AlSiCu film on it.
The second interlayer dielectric 123-2 is formed on the first interlayer dielectric 123-1 that comprises the zone that is formed with the second metal wiring layer 121-2 on it.The second interlayer dielectric 123-2 also has and comprises for example hierarchy of NSG film, sog film and NSG film.In the process-monitor electrode pad formed zone 1000 (being formed with the zone of process-monitor electrode pad 111 on it), through hole was formed in the second interlayer dielectric 123-2 on the second metal wiring layer 1-2.In annular through-hole also is formed at the second interlayer dielectric 123-2 on the second metal wiring layer 121-2 along semiconductor chip 103 peripheries.
The 3rd metal wiring layer 121-3 be formed at that the second interlayer dielectric 123-2 goes up and the through hole of the second interlayer dielectric 123-2 in.In addition, in the zone shown in the figure, the 3rd metal wiring layer 121-3 forms annular along semiconductor chip 103 peripheries.The 3rd metal wiring layer 121-3 also can be formed at other zones of semiconductor wafer 101 and go up (not shown among Figure 16 B).The 3rd metal wiring layer 121-3 also can for example be formed by the titanium film that is formed with the AlSiCu film on it.
Comprise that along what semiconductor chip 103 peripheries formed first, second hierarchy with the 3rd metal wiring layer 121-1,121-2 and 121-3 is the retaining ring 121 that is used for protective semiconductor chip 103 inside.
LOCOS oxidation film 117, bpsg film 119, the first interlayer dielectric 123-1, the second interlayer dielectric 123-2 and final diaphragm 125 are all removed two end (along the Width of scribe line 105) with ribbon-like manner.In this example, the width that is removed the end is 10 μ m.By remove two ends of LOCOS oxidation film 117, bpsg film 119, the first interlayer dielectric 123-1, the second interlayer dielectric 123-2 and final diaphragm 125 along scribe line 105 Widths, the crackle that can prevent to be formed at when the section of this break area 113 in the interlayer dielectric arrives semiconductor chip 103.Yet notice that semiconductor wafer 101 of the present invention is not limited to remove along scribe line 105 Widths the structure of two ends.
Then, with reference to figure 18A and 18B process-monitor zone 107 is described.In Figure 18 B, omitted being included in the description of bpsg film 119, the first interlayer dielectric 123-1, the second interlayer dielectric 123-2 and final diaphragm 125 in the semiconductor chip 103.
In Figure 18 A, two active area 127a, 127b form source electrode and the drain electrode on the semiconductor substrate region surface that is centered on by LOCOS oxidation film 117.The gate electrode of being made by polysilicon 129 is formed between two active area 127a, the 127b on the semiconductor substrate in the zone by gate insulating film.Two active area 127a, 127b and gate electrode 129 form transistor (that is, the process-monitor semiconductor device 109) together.This transistor is positioned at break area and the different part of process-monitor electrode pad 111 place parts.In Figure 18 A example shown, transistor is between process-monitor electrode pad 111a and process-monitor electrode pad 111b.The two ends of polygate electrodes 129 form and extend across LOCOS oxidation film 117.One of end is directed near the process-monitor electrode pad 111c except break area 113 parts.
The first metal wiring layer 121-1a, 121-1b, 121-1c have for example width range of 2 μ m to 3 μ m.
Place the end of the first metal wiring layer 121-1a on the active area 127a to be electrically connected to active area 127a by contact hole.The other end of the first metal wiring layer 121-1a places near the process-monitor electrode pad 111a except break area 113 parts.
Place the end of the first metal wiring layer 121-1b on the active area 127b to be electrically connected to active area 127b.The other end of the second metal wiring layer 121-1b places near the process-monitor electrode pad 111b except break area 113 parts.
Near the first metal wiring layer 121-1c in placing the process-monitor electrode pad 111c on gate electrode 129 ends (Figure 18 A be hidden in the second metal wiring layer 121-2c after) is electrically connected to gate electrode 129 by contact hole.
The second metal wiring layer 121-2a, 121-2b, 121-2c are formed on the first interlayer dielectric 123-1.
The second metal wiring layer 121-2a forms continuously in the relevant position that the process-monitor electrode pad forms on the zone and the first metal wiring layer 121-1a, and this second metal wiring layer 121-2a is electrically connected to the first metal wiring layer 121-1a by through hole.
The second metal wiring layer 121-2b forms continuously in the relevant position that the process-monitor electrode pad forms on the zone and the first metal wiring layer 121-1b, and this second metal wiring layer 121-2b is electrically connected to the first metal wiring layer 121-1b by through hole.
The second metal wiring layer 121-2c forms continuously in the relevant position that the process-monitor electrode pad forms on the zone and the first metal wiring layer 121-1c, and this second metal wiring layer 121-2c is electrically connected to the first metal wiring layer 121-1c by through hole.
The second metal wiring layer 121-1a that protrudes from process- monitor electrode pad 111a, 111b, 111c, the part of 121-1b, 121-1c for example have, and scope is the width of 2 μ m to 3 μ m.
The 3rd metal wiring layer 121-3a, 121-3b, 121-3c are formed on the second interlayer dielectric 123-2.
Be formed at the process-monitor electrode pad and form the 3rd interior metal wiring layer 121-3a of zone (wherein being formed with the zone of process-monitor electrode pad 111a), be electrically connected to the second metal wiring layer 121-2a by through hole.
Be formed at the process-monitor electrode pad and form the 3rd interior metal wiring layer 121-3b of zone (wherein being formed with the zone of process-monitor electrode pad 111b), be electrically connected to the second metal wiring layer 121-2b by through hole.
Be formed at the process-monitor electrode pad and form the 3rd interior metal wiring layer 121-3c of zone (wherein being formed with the zone of process-monitor electrode pad 111c), be electrically connected to the second metal wiring layer 121-2c by through hole.
Because being formed with second with process-monitor electrode pad 111 compares with the semiconductor chip 103 of the second wiring layer 121-2 and 121-3, be formed with still less metal level according to the process-monitor electrode pad 111 of second embodiment of the invention, therefore can reduce the stained formation of metal, even place the situation in the break area 113 of scribe line 105 for process-monitor electrode pad 111.
In addition, because process-monitor electrode pad 111 is arranged to comprise the break area 113 of scribe line 105, therefore do not need to increase the size of semiconductor chip 103 or the width of scribe line 105.
In addition, compare with the process-monitor electrode pad that only has the single metal wiring layer that is formed in the superiors, process-monitor electrode pad 111 more may prevent test during (monitoring) semiconductor wafer probe pierce through the problem of process-monitor electrode pad.This is because process-monitor electrode pad 111 has the second metal wiring layer 121-2 that forms the 3rd metal wiring layer 121-3 that goes up metal wiring layer most and be formed at the 3rd metal wiring layer 121-3 below.
In addition, being formed in the break area situation under the process-monitor electrode pad with first metal wiring layer compares, owing to be not formed with the first metal wiring layer 121-1 under the first and second metal wiring layer 121-2, the 121-3 of process-monitor electrode pad 111, near the stress that puts on when slice process the process-monitor electrode pad 111 can reduce.Can reduce the stained formation of metal thus.
Although the first metal wiring layer 121-1 (that is, descending metal wiring layer most) is formed on the bpsg film 19, process-monitor electrode pad 111 does not comprise this first metal wiring layer 121-1.Therefore, the process-monitor electrode pad 111 that takes place when strengthening leveling by the impurity concentration that increases bpsg film 19 problem of peeling off can be prevented.Yet note, be not limited to make to descend most metal wiring layer to be formed at the structure on the bpsg film according to the semiconductor wafer of the embodiment of the invention.
Because a plurality of contact holes 120 are formed in the bpsg film 119 under the process-monitor electrode pad 111, this bpsg film 119 can contact by the inwall of contact hole 120 with the first metal wiring layer 121-1.Can prevent peeling off of the first metal wiring layer 121-1 thus.
Although the above embodiment of the present invention has the process-monitor electrode pad 111 that is formed with the 3rd metal wiring layer 121-3 and the second metal wiring layer 121-2, but this process-monitor electrode pad 111 can only be formed with the 3rd metal wiring layer 121-3 (that is, going up metal wiring layer most).By process-monitor electrode pad 111 only being formed with the 3rd metal wiring layer 121-3,, therefore can further reduce the stained formation of metal because only a metal wiring layer experiences slice process.
In the above embodiment of the present invention of being explained of reference Figure 16-18, the first metal wiring layer 121-1 is not formed at the process-monitor electrode pad 111 times.Yet, in another embodiment, the first metal wiring layer 121-1a, 121-1b can be formed at the zone that places outside the break area 113 (promptly, zones of different) under Nei process-monitor electrode pad 111a, the 111b, the electricity that is used to obtain under process-monitor electrode pad 111a, the 111b connects.
In addition, in yet another embodiment of the present invention, can provide the first metal wiring layer 121-1a, 121-1b thus by in break area 113, forming the metal line pattern under process-monitor electrode pad 111a, the 111b.In this case, the first metal wiring layer 121-1a, 121-1b have for example width of 2-3 μ m (live width).Have abundant width, this first metal wiring layer 121 owing to form the metal line pattern of the first metal wiring layer 121-1a, 121-1b less than break area 113
-1a, 121-1b do not influence slice process.
Figure 20-21 illustrated embodiment can application drawing 19A and 19B shown in structure, wherein process-monitor electrode pad 111 only is formed with the 3rd metal wiring layer 121-3.
Although the above embodiment of the present invention has the semiconductor wafer 101 of the three-layer metal of being formed with wiring layer structure (that is, having the structure of three-layer metal wiring layer), semiconductor wafer 101 of the present invention is not limited to this structure.For example, semiconductor wafer 101 can have the structure of metal wiring layer more than four layers.
For example, semiconductor wafer 101 can be formed with four layers of metal wiring structure, and wherein three of this process-monitor electrode pad 111 upper stratas are formed with metal line.Can realize above-mentioned advantage of the present invention thus.Particularly, by on bpsg film, forming first metal wiring layer, can obtain these advantages more significantly.
In addition, in the semiconductor wafer 101 with the metal wiring structure more than four layers, process-monitor electrode pad 111 can be formed with the two-layer metal wiring layer of going up most of going up metal wiring layer or only being formed with semiconductor wafer 101 of semiconductor wafer 101.
In addition, the invention is not restricted to these embodiment, can carry out changes and improvements not deviating under the scope situation of the present invention.
The application is based on Japan of submitting to Japan Patent office on November 24th, 2005 and on January 13rd, 2006 at first to file No.2005-339456 and 2006-006742, and its full content is hereby expressly incorporated by reference.
Claims (4)
1. semiconductor wafer, has the scribe line that described semiconductor wafer is divided into the matrix of a plurality of semiconductor chips, described semiconductor wafer comprises polysilicon layer, be formed at the polysilicon-metal interlevel dielectric film on the described polysilicon layer and be formed at first metal wiring layer on described polysilicon-metal interlevel dielectric film, and described semiconductor wafer is characterised in that and comprises:
Be formed at the process-monitor electrode pad on the break area of described scribe line, the width of described process-monitor electrode pad is greater than the width of described break area, and described process-monitor electrode pad comprises and is formed at the contact hole that is used for described first metal wiring layer is connected to described polysilicon layer in described polysilicon-metal interlevel dielectric film.
2. semiconductor wafer as claimed in claim 1 is characterized in that described contact hole is not formed in the described break area.
3. semiconductor wafer as claimed in claim 1 is characterized in that further comprising second metal wiring layer that is formed on described first metal wiring layer, and wherein said first metal wiring layer is not formed in the described break area.
4. semiconductor wafer as claimed in claim 1 is characterized in that described polysilicon-metal interlevel dielectric film is a bpsg film.
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| DE102016113837B4 (en) | 2016-07-27 | 2022-01-13 | Infineon Technologies Ag | Semiconductor device, method of testing a semiconductor device and method of forming a semiconductor device |
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