CN100527094C

CN100527094C - Method and apparatus for capturing temporary memory data

Info

Publication number: CN100527094C
Application number: CNB2007101373752A
Authority: CN
Inventors: 谢正立; 杨正国
Original assignee: Via Technologies Inc
Current assignee: Via Technologies Inc
Priority date: 2007-07-25
Filing date: 2007-07-25
Publication date: 2009-08-12
Anticipated expiration: 2027-07-25
Also published as: CN101082879A

Abstract

The invention is a method and device for capturing register data, which is applied to a computer system, wherein the computer system comprises a central processing unit and a chip set, and the device comprises: a trigger signal generator; a user address register; a data transfer register and a user interface, and the method comprises the following steps: firstly, a trigger signal is sent to the chip set in response to the occurrence of an event; secondly, sending an interrupt signal to the central processing unit to enable the central processing unit to call a processing routine; then the processing routine reads data from the specific temporary memory of the computer system pointed by the address data according to the address data and stores the data in the data transfer temporary memory; and finally, providing the user interface to read the data in the data transfer register, wherein the processing routine carries out data reading operation according to the service completion flag and the transaction request status flag stored in the handshake register.

Description

The obtaining scratch memory data method and apparatus

Technical field

The present invention is a kind of obtaining scratch memory data method and apparatus, and finger is applied to the obtaining scratch memory data method and apparatus on the computer system especially.

Background technology

Debug (debug) is the important operation in design process of computer system software/hardware/firmware, is exactly to read that the numerical value in all kinds of working storages inspects for the debug personnel in the computer system and a main operation is arranged in the debug program.And all be to be executed in the operating system application program under the environment of normal operation in order to the debugging tool software of checking all kinds of working storages in the computer system now, for example common kerneldebugger of Microsoft.But thus, the problem that is taken place before operating system is finished loading and normal operation also can't be finished by this type of debugging tool software and check.And when undesired situation takes place operating system (for example operating system is worked as machine), known debugging tool software also will can't work orderly thereupon decommissioning.

For instance, before operating system loads, the Basic Input or Output System (BIOS) of computer system (BIOS) selftest (POST) program of can starting shooting, in order to suitably the logic element that comprises CPU (central processing unit), chipset etc. in the computer system being carried out initialized operation, and the program of start selftest (POST) is made up of a plurality of step.But in the program of start selftest (POST), produce phenomenon when machine, existing known debugging tool software also can't read the numerical value of all kinds of working storages in the computer system, so the reason that can't take place leading to errors be analyzed, and the source code content that can only inspect Basic Input or Output System (BIOS) (BIOS) is come the location of mistakes.

In addition, even when operating system has been finished loading but taken place when the machine phenomenon afterwards, the known debugging tool software of running under operating system environment also will can't read the numerical value of all kinds of working storages in the computer system thereupon decommissioning.Therefore how to improve above-mentioned any means known disappearance, for developing fundamental purpose of the present invention.

Summary of the invention

The present invention is a kind of obtaining scratch memory data method, is applied on the computer system, and this computer system includes CPU (central processing unit) and chipset, and it comprises the following step: send trigger pip to this chipset in response to incident takes place; This chipset sends look-at-me to this CPU (central processing unit), this CPU (central processing unit) is carried out handled routine; This processing routine goes in the specific working storage of this address date this computer system pointed reading of data and unloading in data transfer temporary storage according to address date; And provide user's interface to read data in this data transfer temporary storage, wherein, this processing routine is to hold in the working storage according to friendship that flag is finished in stored service and the transaction request state flags carries out data read operation.

According to above-mentioned conception, obtaining scratch memory data method of the present invention, wherein the specification of this trigger pip can be SERIRQ signal, gpi signal or EXTSMI# signal.

According to above-mentioned conception, obtaining scratch memory data method of the present invention, wherein this specific working storage can be this CPU (central processing unit) inside working storage, PCI configuration working storage or be defined in the storage space address or the inputoutput space address on working storage.

According to above-mentioned conception, obtaining scratch memory data method of the present invention, wherein this address date is deposited in user's address register, and this address date in this user's address register can utilize this user's interface to set.

According to above-mentioned conception, obtaining scratch memory data method of the present invention, wherein this user's interface host computer of can be thumb-acting switch and/or having display.

According to above-mentioned conception, obtaining scratch memory data method of the present invention, wherein this incident can be that a certain step in the start self test program of this computer system is when finishing, when a certain predetermined period time arrives or the user triggers.

According to above-mentioned conception, obtaining scratch memory data method of the present invention, wherein this look-at-me of sending of this chipset is a system management interrupt signal, and this CPU (central processing unit) just enters System Management Mode and call out this processing routine that is arranged in BIOS chip.

According to above-mentioned conception, obtaining scratch memory data method of the present invention, wherein this processing routine is to read this address date from the address date working storage.

According to above-mentioned conception, obtaining scratch memory data method of the present invention, wherein this processing routine data read operation of carrying out comprises the following step: judge whether this transaction request state flags is configured to " 1 ", if, just reading of data and be stored to this data transfer temporary storage in this specific working storage that points to according to this address date, then this transaction request state flags is removed and be " 0 ", judge that then this service finishes flag and whether be configured to " 1 ", if flag is finished in this service is removed to " 0 " and jump out this processing routine and this System Management Mode; And this service finish flag then to get back to previous step rapid for " 0 " if judge.

According to above-mentioned conception, obtaining scratch memory data method of the present invention, wherein to hold working storage be that read/write is once removed the formula working storage in this friendship, when the relative position of holding working storage to this friendship when this processing routine writes " 1 ", just can with this transaction request state flags maybe this service finish flag and remove and be " 0 ".

Another aspect of the invention is a kind of obtaining scratch memory data device, be applied on the computer system, this computer system includes CPU (central processing unit) and chipset, this obtaining scratch memory data device comprises: the trigger pip generator, it is to send trigger pip to this chipset in response to incident takes place, send look-at-me to this CPU (central processing unit) in order to trigger this chipset, handle routine and this CPU (central processing unit) is carried out; User's address register, this processing routine are to go reading of data in the specific working storage of this address date this computer system pointed according to the address date in this user's address register; Data transfer temporary storage, the data of reading from this specific working storage for this processing routine store; And user's interface, signal is connected to this data transfer temporary storage, this user's address register and this trigger pip generator, its be used for reading in this data transfer temporary storage data and to this user's address register and this trigger pip generator input data; And hand over and hold working storage, this friendship is held the working storage service of having deposited and is finished flag and transaction request state flags, and this processing routine finishes flag according to this service and this transaction request state flags carries out data read operation.

According to above-mentioned conception, obtaining scratch memory data device of the present invention, wherein the specification of this trigger pip can be SERIRQ signal, gpi signal or EXTSMI# signal.

According to above-mentioned conception, obtaining scratch memory data device of the present invention, wherein this specific working storage can be this CPU (central processing unit) inside working storage, PCI configuration working storage or be defined in the storage space address or the inputoutput space address on working storage.

According to above-mentioned conception, obtaining scratch memory data device of the present invention, wherein this address date in this user's address register can utilize this user's interface to set.

According to above-mentioned conception, obtaining scratch memory data device of the present invention, wherein this user's interface host computer of can be thumb-acting switch and/or having display.

According to above-mentioned conception, obtaining scratch memory data device of the present invention, wherein this incident can be that a certain step in the start self test program of this computer system is when finishing, when a certain predetermined period time arrives or the user triggers.

According to above-mentioned conception, obtaining scratch memory data device of the present invention, wherein this look-at-me of sending of this chipset is a system management interrupt signal, and this CPU (central processing unit) just enters System Management Mode and call out this processing routine that is arranged in BIOS chip.

According to above-mentioned conception, obtaining scratch memory data device of the present invention, wherein this processing routine data read operation of carrying out comprises the following step: judge whether this transaction request state flags is configured to " 1 ", if, just reading of data and be stored to this data transfer temporary storage in this specific working storage that points to according to this address date, then this transaction request state flags is removed and be " 0 ", judge that then this service finishes flag and whether be configured to " 1 ", if flag is finished in this service is removed to " 0 " and jump out this processing routine and this System Management Mode; And this service finish flag then to get back to previous step rapid for " 0 " if judge.

According to above-mentioned conception, obtaining scratch memory data device of the present invention, wherein to hold working storage be that read/write is once removed the formula working storage in this friendship, when the relative position of holding working storage to this friendship when this processing routine writes " 1 ", just can with this transaction request state flags maybe this service finish flag and remove and be " 0 ".

According to above-mentioned conception, obtaining scratch memory data device of the present invention, wherein to hold the circuit of working storage be can be integrated in this chipset for this trigger pip generator, this user's address register, this data transfer temporary storage, this friendship.

Description of drawings

The present invention must pass through following graphic and explanation, in order to do getting more deep understanding:

Fig. 1, it is that the present invention improves debugging system that any means known develops to be applied to function block schematic diagram in the computer system.

Fig. 2, it is a debug hardware cell built-in function block schematic diagram of the present invention.

Fig. 3, the job step process flow diagram when its processing routine that is built in BIOS chip in being is carried out.

Fig. 4, it is the job step schematic flow sheet that software and hardware two parts of the present invention are carried out after integrated.

Each the element line formula that is comprised during the present invention is graphic is as follows:

CPU (central processing unit) 10 chipsets 11

BIOS chip 12 debugging systems 13

Debug hardware cell 131 is handled routine 132

Bus 110 debug hardware cells 131

Start selftest sign indicating number working storage 1310 trigger pip generators 1311

User's address register 1312 data transfer temporary storage 1313

Working storage 1314 user's interfaces 1315 are held in friendship

Embodiment

See also Fig. 1, it is that the present invention improves debugging system that any means known develops to be applied to function block schematic diagram in the computer system, wherein CPU (central processing unit) 10, chipset 11 and BIOS chip 12 are indispensable hardware of computer system and firmware, the debugging system 13 that the present invention developed then comprises the exploitation of two parts, first is a debug hardware cell 131, it is to carry out signal transmission by bus 110 and chipset 11, second portion then be can in be built in the processing routine (handler routine) 132 of BIOS chip 12.Below both details and running is elaborated.

At first, debug hardware cell 131 can be finished with the form of pci bus element or lpc bus element, and meaning is that bus 110 available PCI buses or lpc bus are finished.Debug hardware cell 131 built-in function block schematic diagrams are then shown in Fig. 2, it includes start selftest sign indicating number working storage (POSTcode register) 1310, trigger pip generator 1311, user's address register 1312, data shift (dump) working storage 1313, (handshake) working storage 1314 and user's interface 1315 are held in friendship, the selftest sign indicating number working storage (POST code register) 1310 of wherein starting shooting is used for capturing the start selftest sign indicating number (POST code) that is transmitted on the bus 110, start selftest sign indicating number (POST code) representative start self test program is accomplished to the code of that step, and the start selftest sign indicating number (POST code) in the start selftest sign indicating number working storage (POSTcode register) 1310 can be read by user's interface 1315.

As for 1311 of trigger pip generators is to send system management interrupt (System Management Interrupt in response to incident takes place, abbreviation SMI) trigger pip is to chipset 11, and then make chipset 11 send this system management interrupt (SMI) to CPU (central processing unit) 10, allow CPU (central processing unit) 10 enter System Management Mode (System Management Mode, be called for short SMM) and call out the processing routine 132 that is arranged in BIOS chip 12.And the implementation of this trigger pip needs basically in response to chipset 11 supported specifications, and can be gpi signal, EXTSMI# signal or SERIRQ signal etc., as for above-mentioned incident can be that a certain step of start in the self test program is when finishing, or a certain predetermined period time when arriving, or the user is when triggering or the like.

User's address register 1312 then provides to the user and inserts address date, this address date is to point to specific working storage, and the inside working storage that this specific working storage can be a CPU (central processing unit) 10, PCI dispose working storage or be defined in some storage space address (memory space address) or inputoutput space address (IO space address) on working storage.So specific working storage according to address date computer system pointed, this processing routine (handler routine) 132 is able to reading of data from specific working storage, and see that from the angle of handling routine 1312 of user's address registers are a read-only working storage (read-only register).

Data transfer temporary storage (dump register) 1313 then provides handles the data that routine (handlerroutine) 132 unloadings are read from specific working storage.Hold 1314 of working storages in order to deposit two flag value as for friendship, one is that (service_complete) flag is finished in service, another is transaction request state (Transaction_Request) flag, and this friendship is held the preferable read/write that can be of working storage 1314 and once removed (read/write-one-clear) formula working storage and finish.

Providing the user as for 1315 user's interfaces carries out the numerical value input or observes the numerical value of wherein depositing above-mentioned all kinds of working storages, user's interface 1315 that its available thumb-acting switch (DIP SWITCH) is finished carries out the work of numerical value input, and, just can observe the numerical value that debug hardware cell 131 is read by user's interface 1315 that a host computer with display is finished.And above-mentioned start selftest sign indicating number working storage (POST code register) 1310, trigger pip generator 1311, user's address register 1312, data shift (dump) working storage 1313 and hand over and hold (handshake) working storage 1314 and all can be integrated in the chipset, or finish in the device outside being independent of computer system with user's interface 1315 together.

See also Fig. 3 again, job step process flow diagram when its processing routine 132 that is built in BIOS chip 12 in being is carried out, at first, step 31 is for judging whether transaction request state (Transaction_Request) flag sets " 1 " for earlier, if, just reading of data in the working storage that enters step 32 and point to according to the address date in the address register 1312, enter after the step 33 just the data storing that will read to data transfer temporary storage (dump register), step 34 then is to remove the transaction request state flags to be " 0 ", the judgement (step 35) whether the service that enters then finishes, (i.e. service finish flag be made as " 1 ") then enters the flag that step 36 service of removing finishes and jumps out and handle routine 132 and System Management Mode if "Yes", if "No" is then got back to step 31.Thus, the present invention handles routine 132 and just can carry out the operation of reading data in the address date working storage pointed after calling out.And when handing over when holding working storage 1314 and once removing (read/write-one-clear) formula working storage for read/write, the relative position that 132 need of processing routine are held working storage 1314 to this friendship writes " 1 ", just can remove and be " 0 " removing flag that transaction request state flags or service finish, can simplify the complexity of software program code.

The job step schematic flow sheet that above-mentioned software and hardware two parts are carried out after integrated then as shown in Figure 4, at first, step 41 is for allowing the user utilize user's interface 1315 to set address date in this user's address register 1312 (the transaction request state flags also need be set to 1 simultaneously), step 42 is for to send trigger pip to chipset 11 by trigger pip generator 1311 then, and chipset just sends this system management interrupt (SMI) to CPU (central processing unit) 10, allows CPU (central processing unit) 10 enter System Management Mode (SMM) and call treatment routine 132 is carried out the operation of above-mentioned Fig. 3.Then enter step 43, whether user's decision has been that last working storage reads service, if "Yes" is carried out setting up of transaction request state (Transaction_Request) flag after then can being made as " 1 " (step 44) by the flag that user's interface 1315 is finished service (service_complete) again to step 45, if "No" then jumps directly to step 45 and carries out setting up of transaction request state (Transaction_Request) flag.As for step 46 item is to judge transaction request state (Transaction_Request) flag whether remove by processed routine 132, if "Yes" is just taken data (step 47) away from data transfer temporary storage (dump register) 1313, judge item again that in step 48 service finishes whether the flag of (service_complete) is " 1 " then, if also jumping out, "Yes" constipation bundle whole operation handles routine 132 and System Management Mode, if "No" rebound step 42 more then.

Thus, the input that the user holds working storage 1314 and user's address register 1312 by 1315 pairs of friendships of user's interface, just can determine whether will enter in System Management Mode and the processing routine 132, and to carry out the acquisition of working storage content on that address, whether to jump out the decision of System Management Mode and processing routine 132 in addition.And owing to System Management Mode can be moved outside the operating system in being independent of, and hardware of the present invention also can be independent of and goes back independent operation outside the computer system, therefore the present invention can improve any means known disappearance really, but, develop fundamental purpose of the present invention so can reach even do not load as yet or all normal operations during computer down in operating system.And but the present invention's widespread use is to the various computer system, so the present invention must be appointed by those skilled in the art and executes that the craftsman thinks and be to modify right neither taking off as attached claim Protector that scope is desired as all.

Claims

1. A method for acquiring temporary register data, applied to a computer system, the computer system comprising a central processing unit and a chipset, comprising the following steps:

Send a trigger signal to the chipset in response to an event;

the chipset sends an interrupt signal to the central processing unit, causing the central processing unit to call a processing routine;

According to the specific register of the computer system pointed to by the address data, the processing routine reads data from the specific register and transfers it to the data transfer register; and

providing a user interface to read the data in the data transfer register,

Wherein, the processing routine performs the data reading operation according to the service completion flag and the transaction request status flag stored in the handshake register.

2. The register data acquisition method according to claim 1, wherein the address data is stored in the user address register, and the address data in the user address register can use the user interface to make settings.

3. The method for retrieving register data according to claim 1, wherein the event can be when a certain step in the POST procedure of the computer system ends, when a certain predetermined cycle time arrives, or when the user trigger.

4. The method for retrieving register data according to claim 1, wherein the interrupt signal sent by the chipset is a system management interrupt signal, and the central processing unit enters the system management mode and calls the SoC located in the BIOS The processing routine in to read the address data from the address data register.

5. The scratchpad data retrieval method according to claim 1, wherein the data reading operation performed by the processing routine comprises the following steps:

Determine whether the transaction request status flag is set to "1", if so, read data from the specific register pointed to by the address data and store it in the data transfer register, and then the transaction request status Clearing the flag to "0", then judging whether the service completion flag is set to "1", if so, clearing the service completion flag to "0" and jumping out of the processing routine and the system management mode; and

If it is judged that the service completion flag is "0", then return to the previous step;

Wherein the handshake register is a read/write-one-clear register, when the processing routine writes "1" to the relative position of the handshake register, the transaction request status flag or The service completion flag is cleared to "0".

6. A temporary register data acquisition device, applied to a computer system, the computer system includes a central processing unit and a chipset, and the temporary register data acquisition device includes:

a trigger signal generator, which sends a trigger signal to the chipset in response to the occurrence of an event, for triggering the chipset to send an interrupt signal to the central processing unit, so that the central processing unit calls a processing routine;

A user address register, providing the processing routine to read data from a specific register of the computer system pointed to by the address data according to the address data in the user address register;

a data transfer register for storing data read by the processing routine from the specific register; a user interface for signal connection to the data transfer register, the user address register and the trigger signal a generator, which is used to read data in the data transfer register and input data to the user address register and the trigger signal generator; and

The handshake register stores a service completion flag and a transaction request status flag, and the processing routine performs a data reading operation according to the service completion flag and the transaction request status flag.

7. The register data acquisition device according to claim 6, wherein the specific register can be an internal register of the central processing unit, a PCI configuration register, or a register defined in memory space address or input and output A scratchpad at a space address.

8. The register data acquisition device according to claim 6, wherein the address data in the user address register can be set by using the user interface.

9. The temporary register data acquisition device according to claim 6, wherein the event can be when a certain step in the POST procedure of the computer system ends, when a certain predetermined cycle time arrives, or when the user trigger.

10. The register data acquisition device according to claim 6, wherein the interrupt signal sent by the chipset is a system management interrupt signal, and the central processing unit enters the system management mode and calls the system chip located in the basic input output output The processing routine in .

11. The register data acquisition device according to claim 6, wherein the data reading operation performed by the processing routine comprises the following steps: