CN100530156C - Control method and device between master-salve module - Google Patents

Abstract

The invention discloses a control method between master and slave modules, comprising a host controller, a master module and at least one slave module, the master module is connected to the host controller and the slave module respectively, and the master controller Sending the control instruction to the slave module through the master module includes the following steps: setting the corresponding relationship between the control instruction and the destination address; the host controller selects and sends the control instruction to the slave module according to the corresponding relationship Sending an instruction to the corresponding destination address; the master module sends the destination address of the instruction to the slave module through an address line. The embodiment of the present invention assigns different instruction information to different address information, and uses addresses as control instructions, so that control instructions can be transmitted between modules through address lines, effectively reducing the control complexity between modules.

Description

A control method and device between master and slave modules

technical field

The invention relates to the technical field of electronic equipment, in particular to a control method and device between master and slave modules.

Background technique

With the continuous improvement of electronic equipment manufacturing technology, a large number of electronic equipment adopt the structure of host + interface card, so that not only can different interface cards be inserted into the host to achieve different functions, but also can be replaced by replacing the interface when the system fails. Card faults can be quickly found. For a simple example, if the image of a computer cannot be displayed, the graphics card of the computer can be replaced to detect whether the graphics card of the computer is faulty, so as to quickly find out where the fault is. And the structure of the host + interface card is also conducive to the upgrade of the system. The system only needs to replace the corresponding interface card to realize the upgrade of the corresponding function, instead of replacing the entire system, which greatly reduces the maintenance cost of the system. At present, a large number of communication devices also adopt the structure of host + interface card, such as switches, routers, security devices (firewalls), etc., so the management or communication of the host to the interface card is very important.

In the prior art, the management communication of the host computer to the interface card is managed or communicated through a serial bus or a parallel bus, such as through an IIC (Inter-Integrated Circuit bus, internal integrated circuit bus) bus, an SPI (serial peripheral interface, serial Peripheral device interface) bus, UART (Universal Asynchronous Receiver/Transmitter, Universal Asynchronous Receiver Receiver) serial port and other serial buses for control and communication.

As shown in Figure 1, it is the schematic diagram that main frame and interface card are connected by IIC serial bus in the prior art, respectively have an IIC serial interface on main frame and interface card, main frame and interface card communicate with each other by respective IIC serial interface The other party transmits data and control signaling. The host and the interface card only need two lines to complete the control and communication, one DATA data line is used for data transmission and one CLK clock line is used to indicate when the data line is valid data. The host sends a specific binary-coded pulse signal through the CLK clock line, and the interface card analyzes the received binary-coded pulse signal to obtain the command issued by the host. For example, the bus signal is initiated by a START signal and completed by a STOP signal, which is generated by leaving the CLK clock line high and sending a 1 to 0 transition on the DATA data line. The end signal is generated by leaving the CLK clock line high and sending a 0 to 1 transition on the DATA data line, and the start and end signals must appear in pairs. Although the structure of the SPI bus and the UART serial port are not exactly the same as the IIC bus, their principles are basically similar.

The disadvantage of using the serial bus is that the main control chip on the host and the interface card must have a serial interface at the same time, so it has certain limitations. When the interface card is replaced and upgraded, only the interface card with a serial interface can be selected. If the host computer and the interface card do not have the corresponding serial interface, you can use a programmable logic device instead of the corresponding serial interface, for example, use CPLD (complex programmable logical device, complex programmable logic device) to simulate the serial interface, because CPLD A large number of multipliers generated need to occupy a large number of macro cells inside the CPLD, so it will take up more logic resources, which is difficult for ordinary CPLDs. If you want to use an FPGA (Field Programmable Gate Array, Field Programmable Gate Array) with more gates It will greatly increase the cost. And because the serial interface control commands rely on the CLK clock line to send out, the timing of the serial interface is very complicated and difficult to program.

As shown in Figure 2, it is a schematic diagram of connecting a host computer and an interface card through a bidirectional parallel bus in the prior art. There is a parallel interface respectively on the host computer and the interface card, and the host computer and the interface card carry out data and control with the other party through their respective parallel interfaces signaling transmission. The bidirectional parallel bus transmits signals in a bit-parallel and byte-serial bidirectional asynchronous manner, including address lines, control lines, and data lines. The host makes the selection of the interface card effective through the control line, and sends the destination address of the data to the interface card through the address line, because each bit of data in the parallel interface requires a line, so it will occupy more pin resources, such as 8 bits The address just needs 8 address lines, will occupy 8 pins of the connector between host computer and interface card. Moreover, the bidirectional parallel bus communication is adopted, and the communication protocol is very complicated, which makes it difficult to realize.

Contents of the invention

The problem to be solved by the present invention is to provide a control method and device between the master and slave modules, which adopts a simple communication protocol and a unidirectional parallel bus to solve the problems of complex design and high difficulty in implementation in the prior art.

In order to achieve the above purpose, an embodiment of the present invention proposes a control method between master and slave modules, which is applied to a master including a master controller, a master module, and at least one slave module, and the master module is respectively connected to the master controller. The host controller is connected to the slave module, and the host controller sends a control command to the slave module through the master module, including the following steps: setting the corresponding relationship between the control command and the destination address; the master module receiving the master The instruction issued by the controller, the destination address of the instruction is the control instruction issued by the host controller to the slave module; the master module sends the destination address of the instruction to the slave module through the address line module.

Wherein, the setting the corresponding relationship between the control instruction and the destination address specifically includes: setting the corresponding relationship between the control instruction and the destination address according to the physical address allocated by the host controller to the master module; The above corresponding relationship is saved in the module.

Wherein, according to the physical address assigned by the host controller to the master module, setting the corresponding relationship between the control instruction and the destination address further includes: assigning an address area to the slave module according to the upper bits of the physical address, different slave modules assign Different address areas; setting the corresponding relationship between the destination address in the address area and the corresponding slave module control instruction.

Wherein, the master module sending the destination address of the instruction to the slave module through the address line further includes, the master module parses the destination address of the instruction to obtain the slave module ID; the master module obtains the slave module ID according to the slave module ID Send the destination address to the corresponding slave module through the address line.

Wherein, after the master module sends the destination address of the instruction to the slave module through the address line, the following steps are further included: the slave module decodes the destination address sent by the master module to obtain the control instruction; The slave module operates according to the control instruction.

Wherein, the master module analyzing the destination address of the instruction to obtain the slave module ID specifically includes: the master module analyzing the upper bits of the destination address to obtain the slave module ID.

Wherein, the master module and the slave module are programmable logic devices.

On the other hand, an embodiment of the present invention also provides a host, including a host controller, a master module, and at least one slave module, the master module is connected to the host controller and the slave module respectively, and the host controller The host controller issues control instructions to the slave module through the master module, and the host controller is used to select the destination address corresponding to the control instruction issued to the slave module according to the corresponding relationship between the control instruction and the destination address. Send instructions; the master module is used to receive the instructions issued by the host controller, and send the destination address of the instructions to the slave module through the address line; the slave module sends the instruction according to the master module The destination address is decoded to obtain the control instruction and execute the control instruction.

Wherein, at least the host controller and the slave module both include a correspondence storage sub-module for storing the correspondence between the control instruction and the destination address, and the correspondence is based on the host controller being the The physical address assigned by the main module is set to get.

Wherein, the main module includes a destination address resolution submodule and a destination address delivery submodule, the destination address resolution submodule is used to resolve the destination address of the instruction issued by the host controller to obtain the slave module ID; The destination address sending sub-module is used to send the destination address to the corresponding slave module through the address line according to the slave module ID parsed by the destination address resolution sub-module.

Wherein, the slave module includes a decoding submodule and an instruction execution submodule, the decoding submodule is used to decode the destination address sent by the master module to obtain a control instruction; the instruction execution submodule, It is used to operate according to the control instruction obtained by the decoding sub-module.

Wherein, the master module and the slave module are programmable logic devices.

The technical solution of the embodiment of the present invention has the following advantages. The embodiment of the present invention assigns different control instructions to different physical addresses, and uses the address as the control instruction, so that the control instructions can be transmitted through the address lines between the modules without requiring Set complex timing control between modules to effectively reduce the complexity of control between modules.

Description of drawings

Fig. 1 is the schematic diagram that host computer and interface card are connected by IIC serial bus in the prior art;

Fig. 2 is the schematic diagram that host computer and interface card are connected by bidirectional parallel bus in the prior art;

FIG. 3 is a structural diagram of a host computer according to an embodiment of the present invention;

FIG. 4 is a flowchart of a control method between master and slave modules according to Embodiment 1 of the present invention.

Detailed ways

The embodiment of the present invention assigns different instruction information to the address information transmitted by the address lines, that is, transmits corresponding instruction information through the address lines between the modules, so as to achieve the purpose of the master controller controlling the slave modules through the master module. The embodiment of the present invention proposes to divide the physical address of the main module into blocks, and assign different address space blocks to different modules. Different address information in the address space blocks assigned to the modules means different instruction information for the modules. . Among them, the physical address of the main module is allocated by the host controller, and only the modules allocated with the physical address can communicate with the host controller, and the host controller cannot send instructions to the modules without the physical address. For example, the physical address 0X2001 0040-0X2001 006F represents the command information for the interface card a where the slave module a is located, and the physical address 0X2001 0041 represents the command to close all SFP (Small Form-factor Pluggables) ports on the interface card a; Address 0X2001 0044 represents the command to close SFP port 3 on interface card a.

The control method between the master-slave modules proposed by the embodiment of the present invention can not only solve the problem of the control of the host to the interface card in the prior art, but also can be used for any slave modules that are not connected to the host controller bus through the method proposed by the embodiment of the present invention method to control. The control command issued by the host controller is forwarded to the slave module through the address lines of the master module and the slave module, so as to realize the control of the slave module by the host controller.

In order to facilitate the description of the following embodiments of the present invention, the embodiments of the present invention will expand the above examples and use this as a basis to describe the following embodiments. However, it cannot be considered as a limitation to the embodiment of the present invention, because the physical addresses assigned to the main module by different host controllers are also different, and can also be controlled according to the number of interface cards inserted on the host and the control of the interface cards. The number of instructions requests a physical address from the host controller. Therefore, any changes about the physical address and the number of control instructions should be covered by the scope of the embodiments of the present invention.

In order to facilitate the description of the following embodiments, the embodiment of the present invention assumes that the host controller assigns physical addresses to the main module as 0X2001 0000-0X2001 00FF, a total of 256 address spaces. The entire address space above can be divided into different areas according to the high bits of the physical address. Each area corresponds to a different interface card. interface card can require the host controller to allocate more physical addresses):

address space Assignment instructions 0X2001 0000～0X2001 003F main module 0X2001 0040～0X2001 006F Slave module on interface card 1 0X2001 0070～0X2001 009F Slave module on interface card 2 0X2001 00A0～0X2001 00CF Slave module on interface card 3 0X2001 00D0～0X2001 00FF Slave module on interface card 4

Set the corresponding relationship between physical addresses and control instructions according to the above-mentioned divided address space blocks. Each physical address corresponds to a different control instruction, as shown in the following table:

address space Control instruction Remark 0X2001 0041 Disable all SFP ports on interface card 1 0X2001 0042 Disable SFP port 1 on interface card 1 0X2001 0043 Disable SFP port 2 on interface card 1 0X2001 0044 Disable SFP port 3 on interface card 1 0X2001 0045 Disable SFP port 4 on interface card 1 0X2001 0046 Read the status of the SFP on the interface card 1 0X2001 0047 Read SFP_TXFault on interface card 1 0X2001 0048 Read SFP_RXLOS on interface card 1 0X2001 0049 Read interface card 1PCB information 0X2001 004A Read interface card 1 ID information 0X2001 004B Read the contents of the interface card 1CPLD interrupt register ... ...

Among them, the above-mentioned entire address space is firstly divided into different areas according to the high bits of the physical address, and the modes corresponding to different interface cards are distributed for each area, which is only one of the preferred implementation modes of the embodiment of the present invention. When the number of cards is small, there is no need to divide the address space blocks, and the corresponding relationship between the physical address and the control instruction can be directly defined. The purpose of dividing the address space blocks is for the master module to easily distinguish which interface card the master controller sends to the slave module. After the module receives the command from the host controller, it only needs to judge which interface card it is sent to according to the high bit of the destination address. After obtaining the ID of the slave module on the interface card, it directly sends the destination address to the slave module. .

Below in conjunction with accompanying drawing and embodiment, the specific embodiment of the present invention is described in further detail:

As shown in FIG. 3 , it is a structural diagram of the host computer according to the embodiment of the present invention. The host computer includes a host controller 11, a master module 22 and at least one slave module 33, wherein the host controller 11 is connected to the master module 22, and the master module 22 is connected to all slave modules. The modules 33 are connected, and the host controller 11 sends control instructions to the slave modules 33 through the master module 22 . For example, the master module 22 is regarded as an interface module on the host, responsible for sending the control instructions of the host controller 11 to the slave module 33; the slave module 33 is regarded as an interface module on the interface card, responsible for receiving and executing the control of the host controller Instructions, so each interface card has a corresponding slave module connected to the master module on the host. As shown in FIG. 3 , the above-mentioned master module 22 and slave module 33 are connected by a unidirectional parallel bus, which are control lines, address lines and data lines respectively, and the control line is 1 bit, which is only used to send corresponding chip selection signals. Because the main module 22 is mainly to realize the control of the slave module 33, the data line between the master module 22 and the slave module 33 can also adopt a one-way mode, if the master module 22 needs to return data to the slave module 33, it can pass through the PCI bus (PeripheralComponent Interconnect, external device interconnection) implementation. Wherein, the main module 22 and the slave module 33 can be MCU (Micro Controller Unit, microcontroller), programmable logic devices and other hardware units that can obtain the allocated physical address and perform communication processing, but since the MCU has its own independent control Instructions, so a better implementation is to select programmable logic devices as the master module 22 and the slave module 33, such as CPLD, FPGA and the like.

The core idea of the embodiment of the present invention is that the main module 22 controls the slave module 33 connected to it through the address line according to the control command issued by the host controller 11. There are many ways to complete the control of the master module 22 on the slave module 33, such as host control The device 11 issues ordinary control commands to the master module 22, and the master module 22 converts the control command into a corresponding physical address according to the correspondence between the control command and the destination address, and sends it to the slave module 33 through the address line to complete the pairing. The slave module 33 is controlled. The present invention proposes a preferred implementation mode. The host controller 11 converts the control instruction into a corresponding destination address according to the correspondence between the above physical address and the control instruction, and sends an instruction to the main module 22 according to the destination address. The main module After receiving the instruction, the destination address of the instruction is forwarded to the slave module 33 through the address line, and after the slave module 33 receives the destination address forwarded by the master module 22 through the address wire, the destination address will also be converted into corresponding and execute the control instructions, so as to realize the control of the slave module 33 by the master controller 11.

First, according to the physical address assigned by the host controller 11 to the master module 22, the corresponding relationship between the physical address and the control instruction is defined; The physical address corresponding to the relationship selection sends an instruction, wherein the destination address of the instruction represents the control instruction issued by the host controller 11, and the instruction issued by the host controller 11 to the main module 22 is not the focus of the embodiment of the present invention. The specific content of is irrelevant to the embodiment of the present invention, for example, the content of the command may be empty. For example, the physical address allocated by the host controller 11 to the main module is 0X2001 0000～0X2001 00FF, a total of 256 address spaces, then the above-mentioned address spaces can correspond to 256 control instructions, and the host controller 11 can control the main module 22 according to the above-mentioned control instructions. and controlled from module 33. For example, physical address 0X2001 0044 is defined as an instruction to close SFP port 3 on interface card 1 where module 33 is located; physical address 0X2001 00D1 is defined as an instruction to close all SFP ports on interface card 4. In this way, when the host controller 11 needs to close the SFP port 3 on the slave module 33, it will send an instruction to the physical address 0X200100D1, and the master module 22 will control the slave module according to the destination address of the instruction after receiving the instruction sent by the host controller 11. 33. The slave module 33 decodes the destination address sent by the master module 22 through the address line, obtains the control instruction, and executes the control instruction. For example, receive the 0X2001 00D1 that master module 22 sends by address line from module 33, then obtain the control instruction of " closing all SFP ports on the interface card 4 " after decoding, then this slave module 33 executes the above-mentioned decoded Control instruction.

Wherein, preferably, when there are multiple interface cards in the host, after the main module 22 receives the instruction from the host controller 11, it will resolve which interface card the instruction from the host controller 11 is issued to according to the destination address of the instruction. on the slave module 33, that is, resolve the ID of the slave module; and send the destination address to the slave module 33 through the address line. Of course, the above-mentioned implementation mode of the present invention is only a preferred embodiment, and it can also be completed in other forms, for example, the instruction issued by the host controller 11 to the master module 22 carries the ID of the slave module, and the master module 22 can use the ID of the slave module after receiving the instruction. The slave module ID carried in this command sends the destination address. Therefore, the main module 22 includes a destination address resolution submodule 221, a destination address delivery submodule 222 and a corresponding relationship preservation submodule 223, and the destination address resolution submodule 221 is used to resolve the destination address of the command sent by the host controller 11 to obtain the slave module ID , the destination address resolution submodule 221 obtains the slave module ID according to the corresponding relationship between the destination address and the control instruction stored in the correspondence preservation submodule 223; The module ID sends the destination address to the corresponding slave module through the address line. The embodiment of the present invention also proposes a mode of detecting the high bits of the destination address to obtain the slave module ID, because when dividing the area block, the corresponding relationship between the physical address and the interface card will be divided according to the high bits of the physical address, for example, 0X2001 0040-0X2001006F means for The control command of interface card 1; 0X2001 0070-0X2001 009F represents the control command for interface card 2. Therefore, the master module only needs to detect the high bit of the destination address of the instruction issued by the host controller to obtain the slave module ID.

Wherein, the slave module 33 includes a decoding sub-module 331, an instruction execution sub-module 332 and a corresponding relationship preservation sub-module 333, and the decoding sub-module 331 is used to decode the destination address sent by the master module 22 to obtain a control instruction, decode The sub-module 331 obtains the control command issued by the host controller according to the correspondence between the destination address and the control command stored in the correspondence saving sub-module 333 . The instruction execution sub-module 332 is used to operate according to the control instruction obtained by the decoding sub-module 331 . For example, the address sent by the master module 22 through the address line is 0X20010046, then the slave module 33 will save the corresponding relationship stored in the submodule 333 according to the corresponding relationship after receiving the address and obtain the control command to read the in-position state of the SFP, the interface The slave module of the card 1 will perform this operation, and feed back the presence status of the SFP to the master module 22 through the data line, and then the master module 22 forwards it to the host controller 11 .

Through the description of the above embodiment, it can be seen that by setting the corresponding relationship between the physical address and the control instruction in the embodiment of the present invention, the master-slave module can transmit the corresponding control instruction through the address line to achieve the purpose of controlling the slave module, thus effectively It reduces the communication complexity between the host and the interface card where the slave module is located.

As shown in FIG. 4 , it is a flow chart of the control method between the master and slave modules in Embodiment 1 of the present invention, including a host controller, a master module and at least one slave module, wherein the master module is connected to the host controller and the slave module respectively, The host controller sends control instructions to the slave modules connected to the master module through the master module, wherein there may be multiple slave modules connected to the master module. Among them, a better implementation mode is to select a programmable logic device as the master module and the slave module, such as CPLD, FPGA and the like. This embodiment comprises the following steps:

Step S401, setting the corresponding relationship between the physical address and the control command. For different main modules, the host controller may assign different physical addresses. Therefore, as a preferred implementation, it is necessary to set the corresponding relationship between the physical address and the control command, so that After the module receives the destination address through the address line, it can know the control command of the host controller. In the embodiment of the present invention, the corresponding relationship needs to be set only after the main module is assigned to different physical addresses, and the corresponding relationship only needs to be set in order, and the subsequent steps can use the corresponding relationship, and it is not necessary to set the corresponding relationship before each control command is issued. Both set the corresponding relationship between the control command and the destination address. As a preferred solution, at least the above-mentioned corresponding relationship is stored on the master controller and the slave module, the master controller selects the destination address of the command according to the corresponding relationship, and the slave module decodes according to the above-mentioned corresponding relationship to obtain the corresponding control command. The master module does not need to save the above corresponding relationship, for example, if a master module corresponds to a slave module, after the master module receives the instruction from the host controller, it can directly forward the destination address of the instruction to the slave module through the address line , without the master module judging which slave module needs to be forwarded to.

The embodiment of the present invention also proposes an optimization method for the above method of setting the corresponding relationship between the control command and the destination address. Firstly, the host controller can first assign the physical address of the master module according to the high bits of the physical address, and according to the individual address of the slave module The data is divided into different address areas, each address area corresponds to a different slave module, and the corresponding relationship between the destination address and the corresponding slave module control command is set in the address area. For example, 0X2001 0040-0X2001 006F represents the control command for interface card 1; 0X20010070-0X2001 009F represents the control command for interface card 2. In this way, after the master module receives the command from the host controller, it can judge which interface card the control command is to be sent to according to the high bit of the command destination address. Therefore, it only needs to read the high bit address information and confirm the slave module ID. , the master module directly forwards the received address information to the interface card where the slave module is located through the address line.

Step S402, the host controller converts the control command to be sent to the slave module into a corresponding destination address according to the corresponding relationship between the control command and the destination address, and sends the command to the destination address. The instruction is different from the control instruction to be sent by the host controller, and the instruction is not the focus of the embodiment of the present invention, and the specific content of the instruction has nothing to do with the embodiment of the present invention. The purpose of this command is to let the master module know the destination address of the command, which is what the host controller actually sends to the slave module, so the content of the command can also be empty.

Step S403, the main module receives the command issued by the host controller, and analyzes the destination address of the command. If there are many interface cards connected to the master module, the master module also needs to judge which interface card the slave module should forward the destination address to after parsing the destination address, that is, the master module also needs to resolve the destination address based on the destination address Slave module ID. The embodiment of the present invention proposes an optimized way to carry the information of the slave module ID through the high bits of the destination address, so that the master module can obtain the information of the slave module ID only by judging the high bits of the destination address. Of course, if the physical address of the master module is not divided into regions, the master module can also obtain the ID information of the slave module according to all destination addresses. The above method is only for the case where there are many interface cards connected to the master module. If the master module is only connected to the interface card where one slave module is located, the master module does not need to perform the above steps, and directly forwards the resolved destination address to the interface The slave module of the card can be used. Of course, the host controller can also add the ID of the slave module to the command sent to the master module. After the master module parses the command of the host controller and obtains the corresponding ID of the slave module, it forwards the destination address of the command to the corresponding slave module. Can.

Step S404, the master module sends the resolved destination address to the corresponding slave module according to the slave module ID. After the master module resolves the ID of the slave module, it will forward the destination address of the instruction issued by the host controller to the slave module, thereby completing the issuance of the control instruction from the host controller to the slave module.

Step S405, the slave module decodes the destination address sent by the master module through the address line, obtains the corresponding control command, and performs corresponding operations according to the control command. For example, the address received by the slave module of interface card 1 through the address line is 0X2001 0048, which means that the operation that the host controller needs to perform on interface card 1 is to read SFP_RXLOS on interface card 1. After parsing the instruction, the slave module will read the SFP_RXLOS on the interface card 1, and feed back the result to the master module, and the master module will send it to the host controller, so as to complete the host controller's operation on the interface card where the slave module is located.

Through the above-mentioned embodiment, it is possible to assign different instruction information to different addresses, and use the address as a control instruction, so that the control instructions can be transmitted between the modules through the address line, effectively reducing the control complexity between the modules, and providing the host controller with The management of the interface card provides a simple and effective method.

The above is only a preferred embodiment of the present invention, it should be pointed out that, for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, and these improvements and modifications can also be made. It should be regarded as the protection scope of the present invention.

Claims (12)

1, a kind of control method of principal and subordinate's intermodule, it is characterized in that, be applied to comprise console controller, primary module and at least one is from the main frame of module, described primary module links to each other from module with described with described console controller respectively, described console controller issues steering order to described from module by described primary module, may further comprise the steps:

The corresponding relation of steering order and destination address is set;

Described console controller is selected describedly to send instructions under module controls is instructed corresponding destination address with being handed down to according to described corresponding relation;

Described primary module is handed down to the destination address of described instruction described from module by address wire.

2, the control method of principal and subordinate's intermodule according to claim 1 is characterized in that the described corresponding relation that steering order and destination address are set specifically comprises:

According to described console controller is the corresponding relation that physical address that described primary module distributes is provided with steering order and destination address;

At least at described console controller with describedly from module, preserve above-mentioned corresponding relation.

3, as the control method of principal and subordinate's intermodule as described in the claim 2, it is characterized in that, is that the corresponding relation that physical address that described primary module distributes is provided with steering order and destination address further comprises according to described console controller:

High position according to described physical address is described from the module assignment address area, and is different from the different address area of module assignment;

Destination address and corresponding corresponding relation from the module controls instruction in the described address area are set.

4, the control method of principal and subordinate's intermodule as claimed in claim 1 or 2 is characterized in that, described primary module is handed down to the destination address of instruction and describedly further comprises from module by address wire,

The destination address that described primary module is resolved described instruction obtains from module I D;

Described primary module is handed down to described destination address corresponding to module according to described from module I D by address wire.

5, the control method of principal and subordinate's intermodule as claimed in claim 1 or 2 is characterized in that, is handed down to the destination address of instruction described after module, further comprising the steps of by address wire at described primary module:

Describedly the destination address that described primary module sends is deciphered controlled instruction from module;

Describedly operate according to described steering order from module.

6, as the control method of principal and subordinate's intermodule as described in the claim 4, it is characterized in that the destination address that described primary module is resolved described instruction obtains specifically comprising from module I D:

The high position that described primary module is resolved described destination address obtains described from module I D.

7, the control method of principal and subordinate's intermodule according to claim 1 is characterized in that, described primary module and described be programmable logic device (PLD) from module.

8, a kind of main frame, it is characterized in that comprise console controller, primary module and at least one from module, described primary module links to each other from module with described with described console controller respectively, described console controller issues steering order to described from module by described primary module

Described console controller is used for selecting describedly to send instructions under the corresponding destination address of the steering order of module with being handed down to according to the corresponding relation of steering order and destination address;

Described primary module is used to receive the instruction that described console controller issues, and is handed down to the destination address of described instruction described from module by address wire;

Describedly the destination address that described primary module sends is deciphered from module, controlled instruction, and operate according to described steering order.

9, as main frame as described in the claim 8, it is characterized in that, at least described console controller and describedly include corresponding relation from module and preserve submodule, be used to preserve the corresponding relation of described steering order and described destination address, described corresponding relation is that the physical address setting that described primary module distributes obtains according to described console controller.

10, as main frame as described in claim 8 or 9, it is characterized in that described primary module comprises that destination address analyzing sub-module and destination address issue submodule,

Described destination address analyzing sub-module, the destination address that is used to resolve the instruction that described console controller issues obtains from module I D;

Described destination address issues submodule, is used for being handed down to described destination address corresponding to module by address wire according to what described destination address analyzing sub-module was resolved from module I D.

11, as main frame as described in claim 8 or 9, it is characterized in that, describedly comprise decoding submodule and instruction implementation sub-module from module,

Described decoding submodule is used for the destination address that described primary module sends is deciphered controlled instruction;

Described instruction implementation sub-module is used for operating according to the described steering order that described decoding submodule obtains.

12, as main frame as described in the claim 8, it is characterized in that, described primary module and described be programmable logic device (PLD) from module.

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