CN100561712C - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The invention discloses a kind of manufacture method of semiconductor device, comprising: form the grid with sidewall spacers on Semiconductor substrate, described sidewall spacers comprises silicon oxide layer and silicon nitride layer; In described Semiconductor substrate, form source region and drain region, and form metal silicide on described grid, source region and surface, drain region; Remove the silicon nitride layer in the described sidewall spacers; Form etching stop layer at the substrate surface that comprises described grid, source region and drain region; At described etching stop layer surface deposition dielectric layer.The present invention can improve the filling quality in the space of pmd layer between grid.

Description

Semiconductor device and manufacturing method thereof

technical field

The invention relates to the technical field of semiconductor manufacturing, in particular to a complementary metal oxide semiconductor device (CMOS) and a manufacturing method thereof.

Background technique

With the rapid development of semiconductor device manufacturing technology, the density of devices in integrated circuits is getting higher and higher, and the critical dimensions of devices have reached the deep submicron stage. In this case, new challenges are presented for the space filling process between components. FIG. 1 is a schematic diagram illustrating a conventional semiconductor device and its formation process. As shown in Figure 1, when the back end of line (BEOL) of the process line forming the interconnection layer starts, it usually needs to be formed in the MOS transistor and the interconnection layer formed in the front end of line (FEOL) of the process line. A dielectric layer 20 is deposited between the lowermost layer 18 of the metal, and the dielectric layer 20 is called a pre-metal dielectric (PMD). The connection hole 16 is formed in the dielectric layer 20 by etching a through hole and filling it with a metal material. The gate 14 of the MOS transistor is connected to the metal connection line 19 in the interconnection layer 18 through the connection hole 16 (the source and the drain are also connected accordingly), and the connection line 19 is connected to the upper layer interconnection through a dual-damascene structure. Even layers.

A method for forming a PMD layer is introduced in Chinese patent application No. 200510077686.5. Before forming the PMD layer, CMOS transistors are formed at the front end of the process line. Firstly, a semiconductor substrate 10 is provided, and n wells and p wells are formed in the substrate 10 for forming NMOS and PMOS. Then a gate oxide layer is deposited on the surface of the substrate 10, and then a polysilicon layer is deposited on the surface of the gate oxide layer. The polysilicon layer is patterned and the polysilicon is etched to form the gate 12 of the NMOS transistor and the gate 14 of the PMOS transistor. Then light doping with low dose ion implantation is performed on both sides of the gates 12 and 14 to form shallow junctions. Next, silicon oxide and silicon nitride are deposited on the surface of the substrate 10 and the gate, and sidewall spacers (offset spacers) 15 are formed by dry etching, followed by high-dose ion implantation on both sides of the gate 12 and 14 heavily doped to form a source region 17 and a drain region 11 . Then deposit a self-alignment barrier layer and etch the self-alignment barrier layer on the surface of the gate 12 and 14, the source region 17 and the drain region 11, deposit metal nickel or cobalt, and after annealing, the gate 12 and 14, the source region A metal silicide 13 is formed on the surface of the region 17 and the drain region 11, and then a contact hole etching stop layer 21 is deposited. In the next process step, utilize plasma-enhanced chemical vapor deposition (HDP-CVD) or subatmospheric pressure chemical vapor deposition (SACVD) process to deposit PMD layer 20, and utilize chemical mechanical polishing (CMP) process to PMD layer 20 planarization. Since the PMD layer 20 needs to fill the space between the gates 14 and 12 without gaps, the deposition effect of the PMD layer 20 affects the quality of the formation of the subsequent contact hole 16 . When the manufacturing process enters the process node below 90nm, the space distance between the gates 12 and 14 is very narrow, similar to a high aspect ratio trench. In this case, the space filling between the gates 12 and 14 becomes more and more difficult. difficulty.

Contents of the invention

The object of the present invention is to provide a semiconductor device and a manufacturing method thereof, which can improve the quality of the space filling of the PMD layer between the gates.

To achieve the above object, the present invention provides a method for manufacturing a semiconductor device, comprising:

forming a gate with a sidewall spacer on a semiconductor substrate, the sidewall spacer comprising a silicon oxide layer and a silicon nitride layer;

forming a source region and a drain region in the semiconductor substrate, and forming a metal silicide on the surface of the gate, the source region and the drain region;

removing the silicon nitride layer in the sidewall spacers;

forming an etch stop layer on the surface of the substrate including the gate, source region and drain region;

A dielectric layer is deposited on the surface of the etching stop layer.

The silicon nitride layer of the sidewall spacer is removed by wet etching.

The etchant for the wet etching is phosphoric acid, the etching time is 20-600 seconds, and the temperature of the etchant is 120°C-200°C.

The material of the etching stop layer is silicon nitride, silicon oxynitride or silicon nitride containing carbon.

The thickness of the etch stop layer is

The deposition process of the etching stop layer is plasma enhanced chemical vapor deposition.

Accordingly, the present invention provides a semiconductor device, comprising:

a gate formed on a semiconductor substrate, the sidewall of the gate having a silicon oxide layer;

source and drain regions formed in the semiconductor substrate, the surfaces of the gate, source and drain regions having metal silicide; and

an etch stop layer formed on the surface of the gate, source region and drain region;

A dielectric layer formed on the surface of the etching stop layer.

The material of the etching stop layer is silicon nitride, silicon oxynitride or silicon nitride containing carbon.

The thickness of the etch stop layer is

The metal silicide is nickel or cobalt silicide.

Compared with the prior art, the present invention has the following advantages:

In the semiconductor device manufacturing method of the present invention, after the metal silicide is formed in the front section of the process line, the silicon nitride layer in the sidewall spacers on both sides of the gate is selectively removed by using a wet cleaning process. Removing the silicon nitride layer in the wall spacers increases the spacing between gates of CMOS devices. When the PMD layer is deposited in the back section of the process line, due to the increase in the space distance between the gates, the difficulty of filling is reduced, the filling effect and coverage of the PMD layer on the space between the gates are improved, and the deposition of PMD is relaxed. Layer's crafting window. In addition, after removing the sidewall spacers, the method of the present invention deposits silicon nitride on the surface of the device as a contact hole etch stop layer, and the etch stop layer covers the surfaces of the NMOS and PMOS transistors of the CMOS device. On the other hand, it acts as a stress film, covering the surface of NMOS and PMOS transistors, which can adjust the stress of NMOS and PMOS transistors along the channel direction, thereby improving device performance.

Description of drawings

The above and other objects, features and advantages of the present invention will be more apparent by a more specific description of preferred embodiments of the present invention shown in the accompanying drawings. The drawings have not been drawn to scale, emphasis instead being placed upon illustrating the gist of the invention. In the drawings, the thickness of layers and regions are exaggerated for clarity.

1 is a schematic diagram illustrating a conventional semiconductor device and its formation process;

2 to 9 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 10 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

Detailed ways

In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention can be implemented in many ways other than those described here, and those skilled in the art can make similar extensions without departing from the connotation of the present invention. Accordingly, the invention is not limited to the specific implementations disclosed below.

2 to 9 are cross-sectional schematic diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention, and the schematic diagrams are just examples, which should not limit the protection scope of the present invention excessively. As shown in Figure 2, the semiconductor device manufacturing method of the present invention first provides a semiconductor substrate 100, and the substrate 100 can be silicon or silicon germanium (SiGe) of single crystal, polycrystalline or amorphous structure, also can be silicon on insulator (SOI), or may also include other materials such as indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Although several examples of materials from which substrate 100 may be formed are described herein, any material that may serve as a semiconductor substrate falls within the spirit and scope of the present invention. An n-well and a p-well (not shown) are formed in the substrate 100 by a doping process such as an ion implantation process.

Then, a gate oxide layer 110 is formed on the surface of the substrate 100, and the gate oxide layer 110 may be silicon oxide (SiO2) or silicon oxynitride (SiNO). At the process node below 65nm, the material of the gate oxide layer 110 is preferably a high dielectric constant material, such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, Barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, etc. Particularly preferred are hafnium oxide, zirconium oxide and aluminum oxide. Although a few examples of materials that may be used to form gate oxide layer 110 are described here, this layer may be formed from other materials that reduce gate leakage current. The growth method of the gate oxide layer 110 can be any conventional vacuum coating technique, such as atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) ) process, preferably an atomic layer deposition process. In such a process, a smooth atomic interface is formed between the substrate 100 and the gate oxide layer 110 , and a gate dielectric layer with an ideal thickness can be formed.

Next, a polysilicon layer is deposited on the surface of the gate oxide layer, and a polysilicon layer can be deposited on the surface of the substrate by PECVD or high-density plasma chemical vapor deposition (HDP-CVD) process. A hard mask layer, such as silicon nitride, needs to be formed on the surface of the deposited polysilicon layer, and the above-mentioned silicon nitride is usually deposited by PECVD process. Then apply photoresist and pattern the photoresist to define the position of the gate, then use the photoresist and silicon nitride as a mask, and use the plasma etching method to etch the polysilicon layer to form the gate 120 of the NMOS transistor and the PMOS The gate 130 of the transistor. Then remove the remaining photoresist and hard mask silicon nitride, the photoresist is removed by an ashing process, and the hard mask silicon nitride is removed by phosphoric acid wet method.

Next, as shown in FIG. 3 , in order to repair the damage to the sidewalls of the gates 120 and 130 caused by etching and removing silicon nitride, an oxide layer 140 needs to be grown on the surface and both sides of the gates. The above-mentioned oxide layer 140 may be formed using thermal oxidation or ISSG (In Situ Steam Generation). Then low-dose impurity ion implantation is performed on the substrate to form a shallow junction between the source region and the drain region. For the NMOS transistor, the n-type impurity used is phosphorus (P) and arsenic (As); for the PMOS transistor, the used p-type impurity is boron (B). The atoms doped with impurities are ionized, separated, accelerated (acquired kinetic energy), form ion beams, and sweep the surface of the polysilicon layer. The impurity ions physically bombard the surface of the polysilicon layer, enter the surface and stop below the surface. Ion implantation uses gaseous sources doped with impurities, and most gaseous sources use fluorides, such as PF ₅ , AsF ₅ , and BF ₃ .

之间。随后采用等离子增强化学气相淀积工艺(PECVD)在氧化层150表面沉积氮化硅层160，如图5所示。Then, as shown in FIG. 4 , an oxide layer 150 is deposited on the surfaces of the gate electrodes 120 and 130 and the surface of the substrate 100. The oxide layer 150 may be silicon oxide (SiO ₂ ), and silane (SiH ₄ ) and Oxygen O ₂ is deposited and formed by conventional CVD process, and the thickness of this layer is between

between. Subsequently, a silicon nitride layer 160 is deposited on the surface of the oxide layer 150 by plasma enhanced chemical vapor deposition (PECVD), as shown in FIG. 5 .

随后，在自对准阻挡层表面涂布光刻胶并通过显影、定影等光刻工艺构图所述自对准阻挡层，借此界定义金属硅化物形成的位置。接着，利用图案化的光刻胶为掩膜刻蚀所述自对准阻挡层，在自对准阻挡层中对应栅极、源区和漏区的位置处形成开口。接着，在自对准阻挡层表面利用物理溅射的方法沉积金属镍或钴。由于自对准阻挡层起到掩膜的作用，因此所述金属只会与栅极、源区和漏区表面的硅相接触。随后进行热退火，优选快速热退火工艺，以使与栅极、源区和漏区接触的金属与下方的硅发生硅化反应，形成镍或钴的硅化物180。典型退火温度在500～550℃之间。接下来采用湿法清洗去除未发生硅化反应的剩余金属和自对准阻挡层。Etching the silicon nitride layer 160 and the oxide layer 150 by dry etching, such as a reactive ion etching (RIE) process, to form a sidewall spacer with an ON structure, the ON structure includes a silicon oxide 150' and a silicon nitride 170, As shown in Figure 6. In this embodiment, the flow rate of etchant gas in the reaction chamber is 50-400 sccm, the substrate temperature is controlled between 20°C and 90°C, the chamber pressure is 4-80mTorr, and the RF output power of the plasma source is 1500W-2000W. The etchant uses a mixed gas, which includes SF6, CHF3, CF4, chlorine Cl ₂ , oxygen O ₂ , nitrogen N ₂ , helium He and oxygen O ₂ , and other inert gases, such as hydrogen Ar, neon Ne, etc. . Next, high-dose ion implantation is used for heavy doping to form source and drain regions. A self-alignment barrier layer is then formed on the surfaces of the substrate 100, the gates 120 and 130, and the sidewall spacers. The material of the self-aligned barrier layer is preferably silicon-rich oxide, formed by chemical vapor deposition or thermal oxidation, with a thickness of

Subsequently, a photoresist is coated on the surface of the self-alignment barrier layer, and the self-alignment barrier layer is patterned by photolithography processes such as developing and fixing, thereby defining the position where the metal silicide is formed. Next, the self-alignment barrier layer is etched using the patterned photoresist as a mask, and openings are formed in the self-alignment barrier layer at positions corresponding to the gate, the source region and the drain region. Next, metal nickel or cobalt is deposited on the surface of the self-aligned barrier layer by physical sputtering. Since the self-alignment barrier acts as a mask, the metal will only contact the silicon on the surface of the gate, source and drain regions. Then perform thermal annealing, preferably a rapid thermal annealing process, so that the metal in contact with the gate, the source region and the drain region undergoes a silicide reaction with the underlying silicon to form a nickel or cobalt silicide 180 . Typical annealing temperatures are between 500 and 550°C. Next, wet cleaning is used to remove the remaining metal and the self-alignment barrier layer that have not undergone silicidation reaction.

上述刻蚀停止层190一方面作为后续刻蚀连接孔的蚀刻停止层，另一方面起到了应力膜的作用，其覆盖NMOS和PMOS晶体管表面，能够调整NMOS晶体管的栅极120和PMOS晶体管的栅极130下方沿沟道方向的应力，从而提高器件性能。In the next process step, as shown in FIG. 7 , the method of the present invention removes the silicon nitride layer 170 in the previously formed wall spacers. The silicon nitride layer 170 is removed by wet etching, the etching solution used is phosphoric acid (H ₃ PO ₄ ), the etching time is controlled between 20-600 seconds, and the temperature of the etching solution is 120°C-200°C. Then, as shown in FIG. 8 , using CVD process, preferably PECVD, an etch stop layer 190 is deposited on the surface of the substrate 100 including the gates 120 and 130, the source region and the drain region, and the etch stop layer 190 is nitrided. Silicon (Si3N4), silicon oxynitride (SiON) or carbon-containing silicon nitride (nitridedoped carbon, NDC), such as silicon oxynitride carbon (SiOCN), with a thickness of

On the one hand, the above-mentioned etching stop layer 190 is used as an etching stop layer for subsequent etching of connection holes, and on the other hand, it acts as a stress film, which covers the surfaces of NMOS and PMOS transistors, and can adjust the gate electrode 120 of the NMOS transistor and the gate electrode of the PMOS transistor. The stress along the channel direction under the pole 130 can be improved, thereby improving the performance of the device.

Then, a dielectric layer 200 is deposited in-situ on the surface of the etching stop layer 190, as shown in FIG. 9 . The dielectric layer 200 is an inorganic silicon base layer (Inorganic silicon based layer) with a low dielectric constant deposited by chemical vapor deposition, such as silicon oxycarbide (SiCO) or fluorinated silicon glass (FSG), preferably Applied Materials (Applied Materials ) company trademark is black diamond (black diamond) silicon dioxide (SiO2). In a preferred embodiment of the present invention, the method of forming pre-metal low-k dielectric layer 200 uses a heated quasi-atmospheric chemical vapor deposition (SACVD) process involving a carbon-containing organometallic or organosilicon compound, ozone, and a dopant source. Density plasma chemical vapor deposition (HDP-CVD) process. Carbon-containing organometallic or organosilicon compounds may include cyclic siloxanes such as tetramethylcyclotetrasiloxane (TMCTS) or octamethylcyclotetrasiloxane (OMCTS) or other cyclic siloxanes, preferably OMCTS . In the CVD reaction chamber, the wafer is placed on a platform inside the reaction chamber, which includes heating elements, and the platform is controlled by a thermal sensor for controlling the temperature in the reaction chamber. A flow of reactive gases including OMCTS, a mixture of oxygen and helium is introduced into the reaction chamber. The reaction conditions for forming the low dielectric constant dielectric layer 200 are: the flow rate of octamethylcyclotetrasiloxane OMCTS is 1500-3500 mgm; the flow rate of oxygen O2 is 50-500 sccm; the helium He is 0-2000 sccm; the radio frequency power is 300- 1000W; the reaction chamber pressure is 2~10Torr. The dielectric constant of the formed dielectric layer 200 is less than about 3.0. Subsequently, the above-mentioned dielectric layer 200 is planarized by using a CMP process.

所述金属硅化物为镍或钴的硅化物。FIG. 10 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. As shown in FIG. 10 , it includes a semiconductor substrate 100, a gate oxide layer 110 formed on the surface of the substrate 100, gates 120 and 130 formed on the surface of the gate oxide layer 110, and the side walls of the gates 120 and 130 have oxide oxide layers respectively. Silicon layer 150'. The source region and the drain region formed in the semiconductor substrate 100, the metal silicide 180 formed on the surface of the gate, the source region and the drain region; and the substrate 100, the gate 120 and 130, the source region and the drain region The etch stop layer 190 formed on the surface of the region; the dielectric layer 200 formed on the surface of the etch stop layer 190 . Wherein the material of the etching stop layer 190 is silicon nitride, silicon oxynitride or silicon nitride containing carbon, with a thickness of

The metal silicide is nickel or cobalt silicide.

The above descriptions are only preferred embodiments of the present invention, and do not limit the present invention in any form. Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person familiar with the art, without departing from the scope of the technical solution of the present invention, can use the methods and technical content disclosed above to make many possible changes and modifications to the technical solution of the present invention, or modify it into an equivalent implementation of equivalent changes example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the technical solution of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims (7)

1. A method of manufacturing a semiconductor device, comprising: forming a gate with a sidewall spacer on a semiconductor substrate, the sidewall spacer comprising a silicon oxide layer and a silicon nitride layer; forming a source region and a drain region in the semiconductor substrate, and forming a metal silicide on the surface of the gate, the source region and the drain region; removing the silicon nitride layer in the sidewall spacers; forming an etch stop layer on the surface of the substrate including the gate, source region and drain region; depositing a dielectric layer in-situ on the surface of the etching stop layer, Wherein, the reaction conditions for depositing the dielectric layer are: the flow rate of octamethylcyclotetrasiloxane OMCTS is 1500-3500 mgm; the flow rate of oxygen O2 is 50-500 sccm; the helium He is 0-2000 sccm; the radio frequency power is 300 ～1000W; the reaction chamber pressure is 2～10Torr. 2. The method of claim 1, wherein the silicon nitride layer of the sidewall spacer is removed by wet etching. 3. The method according to claim 2, characterized in that: the etching solution of the wet etching is phosphoric acid, the etching time is 20 seconds to 600 seconds, and the temperature of the etching solution is 120°C to 200°C. 4. The method according to claim 1, wherein the etching stop layer is made of silicon nitride or silicon oxynitride. 5. The method according to claim 1, wherein the material of the etching stop layer is silicon nitride containing carbon. 6. The method according to claim 4 or 5, characterized in that: the thickness of the etching stop layer is

7. The method according to claim 6, wherein the deposition process of the etching stop layer is plasma enhanced chemical vapor deposition.

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