CN100562992C - Bump-indexed wafer structure - Google Patents
Bump-indexed wafer structure Download PDFInfo
- Publication number
- CN100562992C CN100562992C CNB2007100900518A CN200710090051A CN100562992C CN 100562992 C CN100562992 C CN 100562992C CN B2007100900518 A CNB2007100900518 A CN B2007100900518A CN 200710090051 A CN200710090051 A CN 200710090051A CN 100562992 C CN100562992 C CN 100562992C
- Authority
- CN
- China
- Prior art keywords
- bump
- projection
- those
- finger
- extensions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 239000010931 gold Substances 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 10
- 239000000758 substrate Substances 0.000 description 8
- 239000011521 glass Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- MVEBDOSCXOQNAR-UHFFFAOYSA-N cyclobutyl(phenyl)methanone Chemical compound C=1C=CC=CC=1C(=O)C1CCC1 MVEBDOSCXOQNAR-UHFFFAOYSA-N 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1405—Shape
- H01L2224/14051—Bump connectors having different shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
The invention relates to a wafer structure with a pointed bump, which mainly comprises a wafer main body and a plurality of finger-shaped bumps. The chip body has a plurality of pads. The finger-shaped bumps are arranged on the chip main body in a protruding mode, each finger-shaped bump is provided with a bump body and an extension portion, the bottom covering area of each bump body is located in the corresponding connecting pad, and the bottom covering area of each extension portion exceeds the corresponding connecting pad. Therefore, more finger-shaped bumps can be arranged at a fine pitch without increasing the size of the chip, and the bonding strength of the bumps is not affected.
Description
Technical field
The present invention relates to a kind of semiconductor chip structure, particularly relate to and a kind ofly can under the condition that does not increase wafer size, dispose more finger-like projections, and do not influence bump bond intensity, can satisfy the chip architecture that the projection high density is arranged the projection definization of demand.
Background technology
Metal coupling, for example golden projection is to be made on the weld pad of integrated circuit (IC) wafer, is beneficial to external electric connection, is convenient to be applied in follow-up with glass flip chip (COG, Chip On Glass) and membrane of flip chip encapsulation semiconductor products such as (COF, Chip On Film).And electric signal is the device that is sent to collocation via the projection that is positioned at these integrated circuit (IC) wafer both sides and substrate lead-in wire, LCD for example, and along with the desired high image quality of display, high-res, the quantity of the projection that wafer is required increases relatively.In addition, other electronic product is under the requirement of microminiaturization, and integrated circuit is complicated also can to make that with microminiaturization projection dwindles at interval.
Seeing also Figure 1 and Figure 2, is schematic cross-section and the end face partial schematic diagram that has known projection chip architecture now.A kind of existing known projection chip architecture 100 mainly comprises a wafer main body 110 and plurality of bump 120 and projection 140.
This wafer main body 110 has an active surface 111 and a sealer 113, and this active surface 111 forms and is provided with a plurality of connection pads 112.Wherein, this sealer 113 is to be formed at this active surface 111 and to have plurality of openings 114, and it is to appear those connection pads 112.
Seeing also shown in Figure 3ly, is the projection end face schematic diagram of existing known projection chip architecture.The size of those perforates 114 is the areas less than those connection pads 112, and the size of those perforates 114 is less than 10 μ mX100 μ m, and wherein the width of those connection pads 112 is about 21 μ m to 31 μ m; Length is about 110 μ m to 140 μ m.
See also Figure 1 and Figure 2; those projections 120; be to be provided with and to protrude on this active surface 111 of this wafer main body 110, and place those perforates 114 of sealer 113, those projections 120 that wherein need high density to arrange are edges 115 of contiguous this wafer main body 110.See also shown in Figure 3ly, in the producing lug technology of in the past manufacture of semiconductor, the bottom area of coverage of those projections 120 is greater than the size of those perforates 114 and less than the area of those connection pads 112, the width of those projections 120 is to be about 15 μ m to 25 μ m; Length is about 100 μ m to 130 μ m.
One projection lower metal layer 130 is to be formed between this sealer 113 and those projections 120 and to be connected those connection pads 112, for the joint of those projections 120.
See also shown in the 2nd figure, those projections 140 are the opposite sides that are arranged at this active surface 111 of this wafer main body 110 and are positioned at this wafer main body 110, and its arranging density is the arranging density that is lower than those projections 120 of another opposite edges 115 usually.When the quantity of those projections 120 was required to increase, the size of those projections 120 was synchronous reduced, and caused the reduction of bump bond intensity.
This shows that above-mentioned existing projection chip architecture obviously still has inconvenience and defective, and demands urgently further being improved in structure and use.In order to solve the problem of above-mentioned existence, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and common product does not have appropriate structure to address the above problem, this obviously is the problem that the anxious desire of relevant dealer solves.Therefore how to found a kind of chip architecture of projection definization of new structure, real one of the current important research and development problem that belongs to, also becoming the current industry utmost point needs improved target.
Because the defective that above-mentioned existing projection chip architecture exists, the inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, and the utilization of cooperation scientific principle, actively studied innovation, in the hope of founding a kind of chip architecture of new projection definization, can improve general existing projection chip architecture, make it have more practicality.Through constantly research, design, and, create the present invention who has practical value finally through after studying sample and improvement repeatedly.
Summary of the invention
Main purpose of the present invention is, overcome the defective that existing projection chip architecture exists, and provide a kind of chip architecture of new projection definization, technical problem to be solved is to make it can dispose more finger-like projection under the condition that does not increase wafer size, and do not influence bump bond intensity, can satisfy the demand that the projection high density is arranged, be very suitable for practicality.
The object of the invention to solve the technical problems realizes by the following technical solutions.The chip architecture of a kind of projection definization that proposes according to the present invention, it comprises: a wafer main body, it has a plurality of connection pads and a sealer, wherein this sealer has a plurality of perforates corresponding to those connection pads, the size of each perforate is the area less than corresponding connection pad, appears those connection pads with the part; And a plurality of finger-like projections, its overshooting shape is arranged on this wafer main body, each finger-like projection has a projection body and an extension, the overlay area, bottom of those projection bodies is to be positioned at those connection pads and greater than those perforates, the overlay area, bottom of those extensions is to exceed outside those connection pads.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The chip architecture of aforesaid projection definization, wherein said those projection bodies are to have consistent contour end face with those extensions.
The chip architecture of aforesaid projection definization, wherein said wafer main body has an edge, and those finger-like projections are to be adjacent to this edge, and those extensions are further from this edge with respect to those projection bodies.
The chip architecture of aforesaid projection definization, the bearing of trend of wherein said those extensions be with this edge vertical each other to.
The chip architecture of aforesaid projection definization, wherein said those projection bodies and those extensions are for wide.
The chip architecture of aforesaid projection definization, the development length of wherein said those extensions are the length 1/4th that is not less than those projection bodies.
The chip architecture of aforesaid projection definization; it includes a projection lower metal layer (UBM) in addition; it is between those finger-like projections and this sealer and is connected to those connection pads that wherein the size of this projection lower metal layer is that essence is equal to the overlay area, bottom of those projection bodies and the overlay area, bottom of those extensions.
The chip architecture of aforesaid projection definization, wherein said those connection pads are to be the aluminium pad, and those finger-like projections are to be golden projection.
The chip architecture of aforesaid projection definization, it includes plurality of bump in addition, and its overshooting shape is arranged on this wafer main body and does not have the extension that surpasses corresponding connection pad.
The present invention compared with prior art has tangible advantage and beneficial effect.By above-mentioned technical scheme, the chip architecture of projection definization of the present invention has following advantage and beneficial effect at least: chip architecture of the present invention utilizes those finger-like projections, can be configured in the limited Waffer edge length greater number, and can not influence bump bond intensity, also not having projection touches and causes short circuit problem, and can meet the demand that advanced projection high density is arranged, be very suitable for practicality.
In sum, the invention relates to a kind of chip architecture of projection definization, mainly comprise a wafer main body and a plurality of finger-like projection.This wafer main body has a plurality of connection pads.Those finger-like projections are that overshooting shape is arranged on this wafer main body, and each finger-like projection has a projection body and an extension, and the overlay area, bottom of those projection bodies is to be positioned at those connection pads, and the overlay area, bottom of those extensions is to exceed outside those connection pads.By this, the present invention can little spacing dispose more finger-like projection under the condition that does not increase wafer size, and does not influence bump bond intensity, can satisfy the demand that the projection high density is arranged.The present invention has above-mentioned plurality of advantages and practical value, no matter it all has bigger improvement on product structure or function, obvious improvement is arranged technically, and produced handy and practical effect, and more existing projection chip architecture has the outstanding effect of enhancement, thereby being suitable for practicality more, and having the extensive value of industry, really is a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 is the schematic cross-section that has known projection chip architecture now.
Fig. 2 is the end face partial schematic diagram that has known projection chip architecture now.
Fig. 3 is the projection end face schematic diagram that has known projection chip architecture now.
Fig. 4 is according to a specific embodiment of the present invention, a kind of schematic cross-section of chip architecture of projection definization.
Fig. 5 is according to a specific embodiment of the present invention, the end face partial schematic diagram of the chip architecture of this projection definization.
Fig. 6 is according to a specific embodiment of the present invention, the finger-like projection end face schematic diagram of the chip architecture of this projection definization.
Fig. 7 is that the chip architecture of this projection definization is engaged to the cross section partial schematic diagram of a substrate according to a specific embodiment of the present invention.
Fig. 8 is according to a specific embodiment of the present invention, shows the cross section entity photo figure that is provided with finger-like bump wafer structure.
100: chip architecture 110: the wafer main body
111: active surface 112: connection pad
113: sealer 114: perforate
115: edge 120: projection
130: projection lower metal layer 140: projection
200: chip architecture 210: the wafer main body
211: active surface 212: connection pad
213: sealer 214: perforate
215: edge 220: the finger-like projection
221: projection body 222: extension
230: projection lower metal layer 240: projection
310: substrate 320: lead-in wire
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, its embodiment of chip architecture, structure, feature and the effect thereof of the projection definization that foundation the present invention is proposed, describe in detail as after.
See also Fig. 4 and shown in Figure 5, Fig. 4 is according to a specific embodiment of the present invention, a kind of schematic cross-section of chip architecture of projection definization; Fig. 5 is the end face partial schematic diagram of the chip architecture of this projection definization.According to a specific embodiment of the present invention, it has disclosed a kind of chip architecture of projection definization.The chip architecture 200 of this projection definization mainly comprises a wafer main body 210 and a plurality of finger-like projection 220 or/and projection 240.
Above-mentioned wafer main body 210 has an active surface 211 and a plurality of connection pad 212 that is formed at this active surface 211.In the present embodiment, those connection pads 212 can be the aluminium pad.Please in conjunction with consulting Figure 6 and Figure 7, those connection pads 212 are generally rectangular, and width is about 8 μ m (micron) to 14 μ m (micron); Length is about 110 μ m to 140 μ m, and the thickness of those connection pads 212 is to be not more than 1.2 μ m.
In addition, see also shown in Figure 4ly, this wafer main body 210 has more a sealer 213 (or claim passivation layer), and this sealer 213 is to have a plurality of perforates 214 corresponding to those connection pads 212, appears those connection pads 212 (as shown in Figure 6) with the part.Wherein, the size of those perforates 214 is to be thin-and-long, and its width can be not more than 10 μ m, and its length can be not more than 100 μ m.The size of each perforate 214 is the areas less than corresponding connection pad 212, so can appear those connection pads 212 in the part.Usually the material of this sealer 213 can be phosphorosilicate glass, polyimides (PI) or benzoyl cyclobutane (BCB) or the like, and the thickness of this sealer 213 is to be not more than 3 μ m usually.
Those above-mentioned finger-like projections 220 are these active surfaces 211 that overshooting shape is arranged at this wafer main body 210, and each finger-like projection 220 has a projection body 221 and an extension 222, so that those finger-like projections 220 can be designed to the rectangular finger-like of configured in parallel.Wherein:
This projection body 221, its shape can be the shape that dwindles as the cuboid that has known projection now or its equal proportion.See also Figure 6 and Figure 7, the overlay area, bottom of those projection bodies 221 is to be positioned at those connection pads 212 and greater than those perforates 214, promptly not exceed corresponding connection pad 212.Wherein the width of those projection bodies 221 is to be not more than 16 μ m, and length is about 100 μ m to 130 μ m.
In the present embodiment, those finger-like projections 220 can be golden projection.In addition, although in the present embodiment, those finger-like projections 220 are the single sides that are arranged in this active surface 211 of this wafer main body 210, but be not limited to, and those finger-like projections 220 also can be arranged in the limit, two opposite sides or the side all around of this active surface 211 of this wafer main body 210.
And, those extensions 222, its overlay area, bottom is to exceed outside those connection pads 212, so that those finger-like projections 220 are outstanding finger-like, to increase the effective bonding area of projection.In the present embodiment, the development length of those extensions 222 is the length 1/4th that can be not less than those projection bodies 221, again with the length 1/2nd that is not less than those projection bodies 221 for good especially.Wherein, the length of those extensions 222 is to be not more than 150 μ m, so that the length of those finger-like projections 220 can be between 130 μ m to 200 μ m.Preferably, those extensions 222 are can be for wide, so that those finger-like projections 220 have monnolithic case with those projection bodies 221.See also shown in Figure 8ly, it is the cross section stereomicroscope photo figure that shows the chip architecture 200 be provided with finger-like projection 220, and those above-mentioned as can be known finger-like projections 220 are can specifically be embodied on the semiconductor wafer.
Please consulting shown in Figure 6ly again, is according to a specific embodiment of the present invention, the finger-like projection end face schematic diagram of the chip architecture of this projection definization.In the present embodiment, this wafer main body 210 can have an edge 215, and those finger-like projections 220 are to be adjacent to this edge 215, and those extensions 222 are further from this edge 215 with respect to those projection bodies 221.The bearing of trend of those extensions 222 be can with this edge 215 vertical each other to.Therefore, those finger-like projections 220 can be arranged in parallel to high-density, reach the effect of the little spacing of projection.
In the present embodiment, this chip architecture 200 is that those finger-like projections 220 can be used as the highdensity output of high pin number of display for a display drives wafer.Please consult shown in Figure 5 again, this chip architecture 200 can include plurality of bump 240 in addition, it is that overshooting shape is arranged on this wafer main body 210 and does not have the extension that surpasses corresponding connection pad, wherein the arranging density of those projections 240 is to be lower than those finger-like projections 220, can be used as the input of the low pin number of display.The shape of those projections 240 can be identical with traditional projection, or can be identical with finger-like projection of the present invention 220.
Seeing also shown in Figure 7ly, is according to a specific embodiment of the present invention, and the chip architecture of this projection definization is engaged to the cross section partial schematic diagram of a substrate.Further specify the application process of this chip architecture 200 below, those finger-like projections 220 are the plurality of leads 320 that can be engaged to a substrate 310, and wherein the thickness of those lead-in wires 320 is to be about 3 μ m to 18 μ m.Preferably, those projection bodies 221 can have consistent contour end face with those extensions 222, are beneficial to engage those lead-in wires 320, and wherein this projection body 221 all is about 10 μ m to 25 μ m with the height of those extensions 222.In the present embodiment, this chip architecture 200 is to can be applicable to membrane of flip chip encapsulation (COF, Chip On Film), and this substrate 310 is to can be a circuit film.In addition, this chip architecture 200 also can be applicable in other semiconductor products, for example glass flip chip (COG, Chip On Glass) product, then this substrate 310 is to can be a glass substrate, and as liquid crystal panel, those lead-in wires 320 are to can be ITO (indium tin oxide target) lead.
Particularly; this chip architecture 200 can include a projection lower metal layer 230 (UBM in addition; UnderBump Metallurgy); it is between those finger-like projections 220 and this sealer 213 and is connected to those connection pads 212 that wherein the size of this projection lower metal layer 230 is that essence is equal to the overlay area, bottom of those projection bodies 221 and the overlay area, bottom of those extensions 222.Usually this projection lower metal layer 230 is that its material can be titanium tungsten/gold (TiW/Au), titanium tungsten/copper/gold (TiW/Cu/Au) or titanium/nickel/gold (Ti/Ni/Au) for sputter forms.
Therefore, chip architecture 200 of the present invention utilizes those finger-like projections 220 can be configured in the limited Waffer edge length greater number, and can not influence bump bond intensity, also not have projection and touch and cause short circuit problem, so can meet the demand that advanced projection high density is arranged.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100900518A CN100562992C (en) | 2007-03-21 | 2007-03-21 | Bump-indexed wafer structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100900518A CN100562992C (en) | 2007-03-21 | 2007-03-21 | Bump-indexed wafer structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101271872A CN101271872A (en) | 2008-09-24 |
| CN100562992C true CN100562992C (en) | 2009-11-25 |
Family
ID=40005698
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2007100900518A Active CN100562992C (en) | 2007-03-21 | 2007-03-21 | Bump-indexed wafer structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100562992C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8729699B2 (en) * | 2011-10-18 | 2014-05-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Connector structures of integrated circuits |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002052646A1 (en) * | 2000-12-22 | 2002-07-04 | Koninklijke Philips Electronics N.V. | Integrated circuit device |
| US20050040543A1 (en) * | 2003-07-31 | 2005-02-24 | Kiyonori Watanabe | Semiconductor device and method of manufacturing same |
| US6878963B2 (en) * | 2001-11-16 | 2005-04-12 | Advanced Semiconductor Engineering, Inc. | Device for testing electrical characteristics of chips |
-
2007
- 2007-03-21 CN CNB2007100900518A patent/CN100562992C/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002052646A1 (en) * | 2000-12-22 | 2002-07-04 | Koninklijke Philips Electronics N.V. | Integrated circuit device |
| US6878963B2 (en) * | 2001-11-16 | 2005-04-12 | Advanced Semiconductor Engineering, Inc. | Device for testing electrical characteristics of chips |
| US20050040543A1 (en) * | 2003-07-31 | 2005-02-24 | Kiyonori Watanabe | Semiconductor device and method of manufacturing same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101271872A (en) | 2008-09-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI434383B (en) | Bonding pad structure and integrated cicruit comprise a pluirality of bonding pad structures | |
| TW200818437A (en) | Chip and manufacturing method thereof | |
| US20090001567A1 (en) | IC chip with finger-like bumps | |
| CN101083238A (en) | Microelectronic element with elastic conductive projection and method of manufacture | |
| TW201135858A (en) | Structure and method of forming pillar bumps with controllable shape and size | |
| CN202394889U (en) | Semiconductor packaging structure | |
| TWI329917B (en) | Semiconductor chip having fine pitch bumps and bumps thereof | |
| CN100562992C (en) | Bump-indexed wafer structure | |
| CN101635290B (en) | Metal Bump Structure and Its Application to Packaging Structure | |
| TWI469288B (en) | Bumped chip and semiconductor flip-chip device applied from the same | |
| CN211125693U (en) | L ED packaging support and packaging structure | |
| TW201044527A (en) | Chip architecture having film-faced metal bumps and semiconductor flip-chip device applied from the same | |
| CN102738087B (en) | Wafer wiring structure | |
| CN100428433C (en) | Structure of Electrical Connection Pads | |
| CN101533816B (en) | Conductive bump structure and chip bonding structure of display panel | |
| CN100580915C (en) | Packaging conductive structure and manufacturing method thereof | |
| TW200837912A (en) | IC chip having finger-like bumps | |
| JP4990711B2 (en) | IC chip manufacturing method and IC chip mounting method | |
| CN102184909A (en) | A structure suitable for connecting chip pins | |
| TWI383460B (en) | Metal bump structure and its application in package structure | |
| CN205231050U (en) | Lead frame pin copper bridge type packaging structure | |
| TWI819644B (en) | Bump structure of chip package to improve wire bonding endurance | |
| TWI263349B (en) | Bonding pads structure of the package | |
| CN2814673Y (en) | Inverted welding packaging structure with low-fusing point large area convex point | |
| TW201707176A (en) | Bump structure of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |