CN100576454C - Gate structure and manufacturing method of non-volatile semiconductor memory - Google Patents

Abstract

A method for fabricating a gate structure, comprising: forming a tunnel oxide layer on a semiconductor substrate; forming discrete metal nano-dots on the tunnel oxide layer by chemical vapor deposition; sequentially forming gates on the discrete metal nano-dots inter-dielectric layer and conductive layer; etching the conductive layer, inter-gate dielectric layer, discrete metal nano-dots and tunnel oxide layer to expose the semiconductor substrate to form a gate structure. The invention also provides a manufacturing method of the non-volatile semiconductor memory. The invention uses a chemical vapor deposition method to simplify the formation of the metal nano-dots and to easily control the size and density of the metal nano-dots.

Description

Gate structure and manufacturing method of non-volatile semiconductor memory

technical field

The invention relates to the field of semiconductor device manufacturing, in particular to a gate structure and a manufacturing method of a non-volatile semiconductor memory.

Background technique

Non-volatile semiconductor memory can still maintain on-chip information after the power supply is turned off; it is electrically erasable and reprogrammable in the system without special high voltage; non-volatile semiconductor memory has the characteristics of low cost and high density. Its unique performance makes it widely used in various fields, including embedded systems, such as PCs and peripherals, telecommunication switches, cellular phones, network interconnection equipment, instrumentation and automotive devices, as well as emerging voice, image, data Storage products such as digital cameras, digital voice recorders and personal digital assistants.

Non-volatile semiconductor memory is generally designed to have a stacked gate (Stack-Gate) structure, which includes a tunnel oxide layer, a floating gate for storing charges or a charge trapping layer, silicon oxide/nitride An inter-gate dielectric layer of silicon/silicon oxide (Oxide-Nitride-Oxide, ONO) structure and a control gate for controlling data access.

The traditional non-volatile memory adopts polysilicon as the floating gate. Taking the flash memory as an example, the manufacturing process of the flash memory in the Chinese patent application No. 200410033268 is shown in FIGS. 1 to 4 . Referring to FIG. 1 , a tunnel oxide layer 102 is formed on a semiconductor substrate 100 by a thermal oxidation method, and the material of the tunnel oxide layer 102 is silicon oxide or silicon oxide-silicon nitride-silicon oxide (ONO). A first conductive layer 104 is formed on the tunnel oxide layer 102. The material of the first conductive layer 104 is, for example, doped polysilicon, and its forming method is, for example, low pressure chemical vapor deposition (LPCVD); on the first conductive layer 104 An inter-gate dielectric layer 106 is formed on it, and the material of the inter-gate dielectric layer 106 is, for example, silicon oxide, silicon oxide/silicon nitride or silicon oxide/silicon nitride/silicon oxide (ONO); A second conductive layer 108 is formed on the inter-dielectric layer 106. The material of the second conductive layer 108 is, for example, doped polysilicon and metal silicide; a top cover layer 110 is formed on the second conductive layer 108 by chemical vapor deposition. , the material of the capping layer 110 is silicon nitride. As shown in Figure 2, a first photoresist layer 112 is formed on the top cover layer 110, and a control grid pattern is defined through exposure and development processes; the top cover layer 110 and the second photoresist layer are etched with the first photoresist layer 112 as a mask. The second conductive layer 108 exposes the inter-gate dielectric layer 106 to form a control gate 108a. As shown in FIG. 3 , continue to etch the inter-gate dielectric layer 106 by dry etching to define the floating gate pattern; remove the first photoresist layer 112 and the top cover layer 110; use the inter-gate dielectric layer 106 as a mask film, etch the first conductive layer 104 and the tunnel oxide layer 102 to expose the semiconductor substrate 100 to form the floating gate 104a; the control gate 108a, the inter-gate dielectric layer 106, the floating gate 104a and the tunnel oxide Layer 102 constitutes a gate structure. Please refer to FIG. 4, and then, using the gate structure as a mask, implant ions into the semiconductor substrate 100 to form the source/drain 101; form spacers 114 on both sides of the gate structure; and finally carry out the subsequent metal wiring process , forming a non-volatile semiconductor memory.

With the continuous increase of integration in integrated circuit manufacturing process, it has become a trend to increase the integration density of non-volatile semiconductor memory. The floating gate made of polysilicon can reduce the lateral leakage of the non-volatile memory, reduce the thickness of the charge-trapping layer of the formed non-volatile memory, and improve the storage capacity of the memory.

The technical scheme of US Patent No. 6774061 uses nano single crystal silicon as the charge trapping layer so that the size of the memory unit can be reduced. In addition, metal nanodots can also be used as a charge-trapping layer. The process of forming metal nano-dots is: forming a silicon oxide layer on the semiconductor substrate; forming a metal layer on the silicon oxide layer by sputtering; performing rapid annealing on the semiconductor substrate with the metal layer to make the metal layer become Orderly distribution of discrete metal nanodots. However, for metals such as titanium or titanium nitride, it is difficult to agglomerate them to form metal nanodots by annealing.

Contents of the invention

The problem to be solved by the invention is to provide a gate structure and a manufacturing method of a non-volatile semiconductor memory, so that the formation of metal nano-dots is simple.

In order to solve the above problems, the present invention provides a method for fabricating a gate structure, comprising: forming a tunnel oxide layer on a semiconductor substrate; forming discrete metal nano-dots on the tunnel oxide layer by chemical vapor deposition; The inter-gate dielectric layer and the conductive layer are sequentially formed on the metal nano-dots; the conductive layer, the inter-gate dielectric layer, the discrete metal nano-dots and the tunnel oxide layer are etched to expose the semiconductor substrate to form the gate structure.

Optionally, the chemical vapor deposition rate is 2 Å/sec to 4 Å/sec, and the deposition time is 3 seconds to 6 seconds.

Optionally, the metal nano-dots have a diameter of 3nm-6nm. The distance between the adjacent metal nano-dots is 3nm-6nm. The material of the metal nano-dots is a metal that can be deposited by chemical vapor deposition. The material of the metal nano-dot is titanium or titanium nitride or tungsten or tungsten nitride or tantalum or tantalum nitride or palladium or molybdenum.

The invention provides a manufacturing method of a non-volatile semiconductor memory, comprising: forming a tunnel oxide layer on a semiconductor substrate; forming discrete metal nano dots on the tunnel oxide layer by chemical vapor deposition; forming discrete metal nano dots on the discrete metal nano The inter-gate dielectric layer and the conductive layer are sequentially formed on the points; the conductive layer, the inter-gate dielectric layer, the discrete metal nano-dots and the tunnel oxide layer are etched to expose the semiconductor substrate to form the gate structure; Form the source/drain in the semiconductor substrate on the side; perform metal wiring to form a non-volatile semiconductor memory.

Optionally, the chemical vapor deposition rate is 2 Å/sec to 4 Å/sec, and the deposition time is 3 seconds to 6 seconds.

Optionally, the metal nano-dots have a diameter of 3nm-6nm. The distance between the adjacent metal nano-dots is 3nm-6nm. The material of the metal nano-dots is a metal that can be deposited by chemical vapor deposition. The material of the metal nano-dot is titanium or titanium nitride or tungsten or tungsten nitride or tantalum or tantalum nitride or palladium or molybdenum.

Compared with the prior art, the invention has the following advantages: discrete metal nano-dots are formed on the tunnel oxide layer by chemical vapor deposition. Since the chemical vapor deposition method has a discontinuous growth period in the initial stage of the growth of metal nano-dots, by controlling the deposition rate, discrete metal nano-dots can be directly obtained, making the formation of metal nano-dots simple; in addition, because no additional heat treatment process is required, Simplify the process steps.

Further, the chemical vapor deposition rate is 2 Å/sec to 4 Å/sec, and the deposition time is 3 seconds to 6 seconds. The rate of chemical vapor deposition is controlled within 2 angstroms/second to 4 angstroms/second, so that the discontinuous growth time of metal nano-dots is relatively long, 3 seconds to 6 seconds, not only easy to form metal nano-dots, but also make the size of metal nano-dots and density better control.

Description of drawings

Fig. 1 to Fig. 4 are the schematic diagrams of making flash memory by existing technology;

FIG. 5 is a flow chart of a specific embodiment of making a gate structure in the present invention;

6 to 9 are schematic diagrams of embodiments of the present invention for fabricating gate structures;

Fig. 10 is a flow chart of a specific embodiment of making a non-volatile memory according to the present invention;

11 to 15 are schematic diagrams of embodiments of the present invention for fabricating non-volatile memory.

Detailed ways

The invention forms discrete metal nano dots on the tunnel oxide layer by chemical vapor deposition. Since the chemical vapor deposition method has a discontinuous growth period in the initial stage of the growth of metal nano-dots, by controlling the deposition rate, discrete metal nano-dots can be directly obtained, making the formation of metal nano-dots simple; in addition, because no additional heat treatment process is required, Simplify the process steps.

Further, the chemical vapor deposition rate is 2 Å/sec to 4 Å/sec, and the deposition time is 3 seconds to 6 seconds. The rate of chemical vapor deposition is controlled within 2 angstroms/second to 4 angstroms/second, so that the discontinuous growth time of metal nano-dots is relatively long, 3 seconds to 6 seconds, not only easy to form metal nano-dots, but also make the size of metal nano-dots and density better control.

The specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

FIG. 5 is a flow chart of a specific embodiment of fabricating a gate structure according to the present invention. As shown in Figure 5, execute step S101 to form a tunnel oxide layer on the semiconductor substrate; execute step S102 to form discrete metal nano-dots on the tunnel oxide layer by chemical vapor deposition; execute step S103 to form discrete metal nano-dots on the discrete An inter-gate dielectric layer and a conductive layer are sequentially formed on the metal nano-dots; step S104 is performed to etch the conductive layer, inter-gate dielectric layer, discrete metal nano-dots and tunnel oxide layer to expose the semiconductor substrate to form a gate structure .

6 to 9 are schematic diagrams of an embodiment of fabricating a gate structure according to the present invention. As shown in FIG. 6, a tunnel oxide layer 202 is formed on a semiconductor substrate 200, and the material of the tunnel oxide layer 202 is silicon oxide, silicon oxide/silicon nitride/silicon oxide (ONO), silicon-rich oxide (SRO) Or silicon oxynitride (SiON), etc. The conventional process for forming the tunnel oxide layer 202 is a thermal oxidation method. In a high-temperature environment, the semiconductor substrate 200 is exposed to an oxygen-containing environment to form the tunnel oxide layer 202 made of silicon oxide. The process is usually carried out in a furnace. implemented in a tube; the thickness of the tunnel oxide layer 202 is 50 angstroms to 70 angstroms.

Discrete metal nano-dots 204 are formed on the tunnel oxide layer 202 by chemical vapor deposition, and the material of the metal nano-dots 204 is metal that can be deposited by chemical vapor deposition. Specific examples include titanium or titanium nitride or tungsten or tungsten nitride or tantalum or tantalum nitride or palladium or molybdenum.

1. If the metal nano-dots 204 made of titanium are formed, when the temperature is 640°C-660°C, the pressure in the reaction chamber is 4Torr-6Torr (1Torr=133.32Pa), and the flow rate into the reaction chamber is 2800sccm- 3200sccm (standard ml/min) of hydrogen reacts with titanium tetrachloride at a flow rate of 40mgm to 60mgm (mg/min) to generate titanium, wherein the deposition rate is 2 angstroms/second to 4 angstroms/second, and the deposition time is 3 seconds to 4 Second.

In this embodiment, the temperature is specifically 640°C, 645°C, 650°C, 655°C or 660°C, etc., preferably 650°C; the pressure of the reaction chamber is specifically 4 Torr, 5 Torr or 6 Torr, etc., preferably 5 Torr; the specific hydrogen flow rate is 2800 sccm, 2900 sccm , 3000sccm, 3100sccm or 3200sccm, etc., preferably 3000sccm; titanium tetrachloride is specifically 40mgm, 50mgm or 60mgm, etc., preferably 50mgm; the deposition rate is specifically for example 2 angstroms/second, 3 angstroms/second or 4 angstroms/second, etc., preferably 2.5 angstroms /sec; the deposition time is specifically 3 seconds, 3.5 seconds or 4 seconds, etc., preferably 3 seconds.

2. If the metal nano-dots 204 made of titanium nitride are formed, when the temperature is 670°C-690°C, the pressure of the reaction chamber is 3Torr-5Torr, and the flow rate into the chemical vapor deposition furnace is 80sccm-120sccm The ammonia gas reacts with titanium tetrachloride at a flow rate of 400mgm to 500mgm to form titanium nitride, wherein the deposition rate is 2 angstroms/second to 4 angstroms/second, and the deposition time is 5 seconds to 6 seconds.

In this embodiment, the temperature is specifically 670°C, 675°C, 680°C, 685°C or 690°C, etc., preferably 680°C; the pressure of the reaction chamber is specifically 3 Torr, 4 Torr or 5 Torr, etc., preferably 4 Torr; the hydrogen flow rate is specifically 80 sccm, 90 sccm , 100sccm, 110sccm or 120sccm etc., preferably 100sccm; Titanium tetrachloride is specifically 400mgm, 420mgm, 440mgm, 450mgm, 460mgm, 480mgm or 500mgm etc., preferably 450mgm; The deposition rate is specifically for example 2 angstroms/second, 3 angstroms/second or 4 Angstrom/second, etc., preferably 3 Angstrom/second; the deposition time is specifically 5 seconds, 5.5 seconds, or 6 seconds, etc., preferably 6 seconds.

The density, size and shape of the metal nano-dots 204 formed by the method described in this embodiment can be adjusted by controlling the process parameters of the chemical vapor deposition method.

In this embodiment, the metal nano-dots 204 have a diameter of 3nm-6nm, for example 3nm, 4nm, 5nm or 6nm. The distance between the adjacent metal nano-dots 204 is 3nm-6nm, for example, 3nm, 4nm, 5nm or 6nm.

In this embodiment, the thickness of the tunnel oxide layer 202 is specifically 50 angstroms, 55 angstroms, 60 angstroms, 65 angstroms or 70 angstroms, preferably 60 angstroms.

As shown in FIG. 7, an inter-gate dielectric layer 206 is formed on the discrete metal nano-dots 204. The material of the inter-gate dielectric layer 206 is, for example, silicon oxide, silicon oxide/silicon nitride or silicon oxide/silicon nitride/ Silicon oxide (ONO), etc.; because the non-volatile semiconductor memory requires that the silicon oxide layer in contact with the metal nano-dots 204 must have good electrical properties, so as to avoid leakage or leakage of the metal nano-dots 204 used to store charges under normal voltage. It is the problem of premature electrical collapse; taking the material of the inter-gate dielectric layer 206 as silicon oxide as an example, a uniform layer of silicon oxide is formed by low-pressure chemical vapor deposition (LPCVD), and the thickness of the silicon oxide is 130 angstroms. ~170 angstroms, the specific thickness is, for example, 130 angstroms, 140 angstroms, 150 angstroms, 160 angstroms or 170 angstroms.

A conductive layer 208 is formed on the intergate dielectric layer 206 by chemical vapor deposition. The material of the conductive layer 208 is, for example, doped polysilicon or metal silicide; a top cover layer 210 is formed on the conductive layer 208 by chemical vapor deposition. , the material of the capping layer 210 is silicon nitride or the like.

As shown in Figure 8, the first photoresist layer 212 is formed on the top cover layer 210 by spin coating, and the control gate pattern is defined through exposure and development processes; Etching the top cap layer 210 and the conductive layer 208 to expose the inter-gate dielectric layer 206 to form the control gate 208a.

As shown in FIG. 9, continue to etch the inter-gate dielectric layer 206 by dry etching to define the trapping charge layer pattern; remove the first photoresist layer 212 and the top cover layer 210; use the inter-gate dielectric layer 206 as a mask , etch the discrete metal nano-dots 204 and the tunnel oxide layer 202 to expose the semiconductor substrate 200 by dry etching to form the charge trapping layer 204a; and the tunnel oxide layer 202 form a gate structure.

In this embodiment, the discrete metal nano-dots 204 are used as the charge-trapping layer of the memory, and the storage capacity is relatively high.

FIG. 10 is a flow chart of a specific embodiment of the invention for fabricating a non-volatile memory. As shown in Figure 10, execute step S201 to form a tunnel oxide layer on the semiconductor substrate; execute step S202 to form discrete metal nano-dots on the tunnel oxide layer by chemical vapor deposition; execute step S203 to form discrete metal nano-dots on the discrete An inter-gate dielectric layer and a conductive layer are sequentially formed on the metal nano-dots; step S204 is performed to etch the conductive layer, inter-gate dielectric layer, discrete metal nano-dots and tunnel oxide layer to expose the semiconductor substrate to form a gate structure ; Execute step S205 to form source/drain in the semiconductor substrate on both sides of the gate structure; execute step S206 to perform metal wiring to form a non-volatile semiconductor memory.

11 to 15 are schematic diagrams of embodiments of the present invention for fabricating non-volatile memory. As shown in FIG. 11, a tunnel oxide layer 302 is formed on a semiconductor substrate 300, and the material of the tunnel oxide layer 302 is silicon oxide, silicon oxide/silicon nitride/silicon oxide (ONO), silicon-rich oxide (SRO) Or silicon oxynitride (SiON), etc. The traditional process for forming the tunnel oxide layer 302 is a thermal oxidation method. In a high-temperature environment, the semiconductor substrate 300 is exposed to an oxygen-containing environment to form the tunnel oxide layer 302 made of silicon oxide. The process is usually carried out in a furnace. implemented in a tube; the thickness of the tunnel oxide layer 302 is 50 angstroms to 70 angstroms.

Discrete metal nano-dots 304 are formed on the tunnel oxide layer 302 by chemical vapor deposition, and the material of the metal nano-dots 304 is metal that can be deposited by chemical vapor deposition. Specific examples include titanium or titanium nitride or tungsten or tungsten nitride or tantalum or tantalum nitride or palladium or molybdenum.

1. If the metal nano-dots 304 made of titanium are formed, when the temperature is 640°C-660°C, the pressure of the reaction chamber is 4Torr-6Torr (1Torr=133.32Pa), and the flow rate into the reaction chamber is 2800sccm- 3200sccm (standard ml/min) of hydrogen reacts with titanium tetrachloride at a flow rate of 40mgm to 60mgm (mg/min) to generate titanium, wherein the deposition rate is 2 angstroms/second to 4 angstroms/second, and the deposition time is 3 seconds to 4 Second.

In this embodiment, the temperature is specifically 640°C, 645°C, 650°C, 655°C or 660°C, etc., preferably 650°C; the pressure of the reaction chamber is specifically 4 Torr, 5 Torr or 6 Torr, etc., preferably 5 Torr; the specific hydrogen flow rate is 2800 sccm, 2900 sccm , 3000sccm, 3100sccm or 3200sccm, etc., preferably 3000sccm; titanium tetrachloride is specifically 40mgm, 50mgm or 60mgm, etc., preferably 50mgm; the deposition rate is specifically for example 2 angstroms/second, 3 angstroms/second or 4 angstroms/second, etc., preferably 2.5 angstroms /sec; the deposition time is specifically 3 seconds, 3.5 seconds or 4 seconds, etc., preferably 3 seconds.

2. If the metal nano-dots 304 made of titanium nitride are formed, when the temperature is 670°C-690°C, the pressure of the reaction chamber is 3Torr-5Torr, and the flow rate into the chemical vapor deposition furnace is 80sccm-120sccm The ammonia gas reacts with titanium tetrachloride at a flow rate of 400mgm to 500mgm to form titanium nitride, wherein the deposition rate is 2 angstroms/second to 4 angstroms/second, and the deposition time is 5 seconds to 6 seconds.

In this embodiment, the temperature is specifically 670°C, 675°C, 680°C, 685°C or 690°C, etc., preferably 680°C; the pressure of the reaction chamber is specifically 3 Torr, 4 Torr or 5 Torr, etc., preferably 4 Torr; the hydrogen flow rate is specifically 80 sccm, 90 sccm , 100sccm, 110sccm or 120sccm etc., preferably 100sccm; Titanium tetrachloride is specifically 400mgm, 420mgm, 440mgm, 450mgm, 460mgm, 480mgm or 500mgm etc., preferably 450mgm; The deposition rate is specifically for example 2 angstroms/second, 3 angstroms/second or 4 Angstrom/second, etc., preferably 3 Angstrom/second; the deposition time is specifically 5 seconds, 5.5 seconds, or 6 seconds, etc., preferably 6 seconds.

The density, size, and shape of the metal nano-dots 304 formed by the method described in this embodiment can be adjusted by controlling the process parameters of the chemical vapor deposition method.

In this embodiment, the metal nano-dots 304 have a diameter of 3nm-6nm, specifically for example 3nm, 4nm, 5nm or 6nm. The distance between the adjacent metal nano-dots 304 is 3nm-6nm, for example, 3nm, 4nm, 5nm or 6nm.

In this embodiment, the thickness of the tunnel oxide layer 302 is specifically 50 angstroms, 55 angstroms, 60 angstroms, 65 angstroms or 70 angstroms, preferably 60 angstroms.

As shown in FIG. 12, an inter-gate dielectric layer 306 is formed on the discrete metal nano-dots 304. The material of the inter-gate dielectric layer 306 is, for example, silicon oxide, silicon oxide/silicon nitride or silicon oxide/silicon nitride/ Silicon oxide (ONO), etc.; because the non-volatile semiconductor memory requires that the silicon oxide layer in contact with the charge-trapping layer must have good electrical properties, so as to avoid leakage or overshoot of the charge-trapping layer used to store charges under normal voltage. The problem of early electrical collapse; taking the material of the inter-gate dielectric layer 306 as silicon oxide as an example, a uniform layer of silicon oxide is formed by low-pressure chemical vapor deposition (LPCVD), and the thickness of the silicon oxide is 130 angstroms to 170 angstroms. Angstroms, specific thickness such as 130 Angstroms, 140 Angstroms, 150 Angstroms, 160 Angstroms or 170 Angstroms.

A conductive layer 308 is formed on the intergate dielectric layer 306 by chemical vapor deposition. The material of the conductive layer 308 is, for example, doped polysilicon or metal silicide; a top cover layer 310 is formed on the conductive layer 308 by chemical vapor deposition. , the material of the capping layer 310 is silicon nitride or the like.

As shown in Figure 13, the first photoresist layer 312 is formed on the top cover layer 310 by the spin coating method, and the control gate pattern is defined through exposure and development processes; the first photoresist layer 312 is used as a mask, and the Etching the top cap layer 310 and the conductive layer 308 to expose the inter-gate dielectric layer 306 to form the control gate 308a.

As shown in FIG. 14 , continue to etch the inter-gate dielectric layer 306 by dry etching to define the trapping charge layer pattern; remove the first photoresist layer 312 and the top cover layer 310; use the inter-gate dielectric layer 306 as a mask , etch the discrete metal nano-dots 304 and the tunnel oxide layer 302 to expose the semiconductor substrate 300 by dry etching to form the charge trap layer 304a; the control gate 308a, the inter-gate dielectric layer 306, and the charge trap layer 304a and the tunnel oxide layer 302 form a gate structure.

In this embodiment, the discrete metal nano-dots 304 are used as the charge-trapping layer of the memory, and the storage capacity is relatively high.

As shown in FIG. 15 , using the gate structure as a mask, ions are implanted into the semiconductor substrate 300 to form a source electrode 311 and a drain electrode 313. The positions of the source electrode 311 and the drain electrode 313 should be guaranteed to be controlled by the control gate 308a, When a voltage is applied to the gate structure composed of the inter-gate dielectric layer 306 , the charge-trapping layer 304 a and the tunnel oxide layer 302 a , a conductive channel can be formed between the source 311 and the drain 313 . In one embodiment, p-type silicon is selected as the semiconductor substrate material, and N-type low-doped ion implantation is performed on the source electrode 311 and the drain electrode 313, and ions such as arsenic ions and phosphorus ions are implanted.

A spacer 314 is formed on the sidewall of the gate structure. The spacer 314 can be made of silicon oxide, silicon nitride, silicon oxynitride and combinations thereof, and the spacer can not only be used to surround the gate structure, but also prevent a larger dose of source and drain implantation from being too close to the channel so that Source-drain punchthrough may occur, preventing short-channel effects, and can also be used to prevent leakage between the gate structure and the source and drain.

An interlayer dielectric layer 316 is deposited on the semiconductor substrate 300, the interlayer dielectric layer 316 covers the gate structure, the source electrode 311 and the drain electrode 313; a penetrating interlayer dielectric layer is formed in the interlayer dielectric layer 316 A contact hole of the drain electrode 313 is exposed; a conductive material is deposited in the contact hole, and the interlayer dielectric layer and the conductive material are polished by a chemical mechanical polishing method. The conductive material is metal tungsten or polysilicon (poly silicon), which plays the role of conducting the circuit in the circuit.

Although the present invention has been disclosed above with preferred embodiments, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (10)

1. A fabrication method of a gate structure, comprising: forming a tunnel oxide layer on the semiconductor substrate; Forming discrete metal nano-dots on the tunnel oxide layer by chemical vapor deposition, the deposition rate of the chemical vapor deposition method is 2 angstroms/second to 4 angstroms/second, and the deposition time is 3 seconds to 6 seconds; sequentially forming an intergate dielectric layer and a conductive layer on discrete metal nano-dots; Etching the conductive layer, inter-gate dielectric layer, discrete metal nano-dots and tunnel oxide layer to expose the semiconductor substrate to form a gate structure. 2 . The method for fabricating the gate structure according to claim 1 , wherein the metal nano-dots have a diameter of 3 nm˜6 nm. 3 . 3 . The method for fabricating the gate structure according to claim 2 , wherein the distance between the adjacent metal nano-dots is 3 nm˜6 nm. 4 . 4 . The method for fabricating the gate structure according to claim 3 , wherein the material of the metal nano-dots is a metal that can be deposited by chemical vapor deposition. 5 . The fabrication method of the gate structure according to claim 4 , wherein the metal nano-dots are made of titanium or titanium nitride or tungsten or tungsten nitride or tantalum or tantalum nitride or palladium or molybdenum. 6. A method for making a non-volatile semiconductor memory, comprising: forming a tunnel oxide layer on the semiconductor substrate; Forming discrete metal nano-dots on the tunnel oxide layer by chemical vapor deposition, the deposition rate of the chemical vapor deposition method is 2 angstroms/second to 4 angstroms/second, and the deposition time is 3 seconds to 6 seconds; sequentially forming an intergate dielectric layer and a conductive layer on discrete metal nano-dots; Etching the conductive layer, inter-gate dielectric layer, discrete metal nano-dots and tunnel oxide layer to expose the semiconductor substrate to form a gate structure; Forming source/drain electrodes in the semiconductor substrate on both sides of the gate structure; Metal wiring is carried out to form a non-volatile semiconductor memory. 7 . The method for fabricating the non-volatile semiconductor memory according to claim 6 , wherein the metal nano-dots have a diameter of 3nm˜6nm. 8 . The manufacturing method of the non-volatile semiconductor memory according to claim 7 , wherein the distance between the adjacent metal nano-dots is 3nm-6nm. 9. The manufacturing method of the non-volatile semiconductor memory according to claim 8, characterized in that, the material of the metal nano-dots is a metal that can be deposited by chemical vapor deposition. 10. The manufacturing method of the non-volatile semiconductor memory according to claim 9, characterized in that, the material of the metal nano-dots is titanium or titanium nitride or tungsten or tungsten nitride or tantalum or tantalum nitride or palladium or molybdenum .

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