CN100593859C

CN100593859C - Techniques for Fabricating Logic Elements Using Multiple Gate Layers

Info

Publication number: CN100593859C
Application number: CN03815544A
Authority: CN
Inventors: 尼马·莫赫莱希; 杰弗里·卢策
Original assignee: SanDisk Corp
Current assignee: SanDisk Technologies LLC
Priority date: 2002-07-02
Filing date: 2003-06-25
Publication date: 2010-03-10
Anticipated expiration: 2023-06-25
Also published as: CN1689168A

Abstract

The present invention describes various techniques for using multiple polysilicon layers in the design and fabrication of various logic elements used in semiconductor devices. According to one embodiment of the present invention, logic gate cell size and memory array cell size can be reduced by using multiple polysilicon layers to fabricate various transistor gates. The present invention's technique of using multiple polysilicon layers to form transistor gates for logic elements provides additional degrees of freedom in fine-tuning transistor parameters such as oxide thickness, threshold voltage, and maximum allowable gate voltage.

Description

Be used to use multiple gate layers to make the technology of logic element

Technical field

In general, the present invention relates to the integrated circuit (IC) chip manufacturing, more specifically, relate to a kind of technology of using the multiple gate layers technology to make logic element.

Background technology

The manufacturing of integrated circuit is usually directed to numerous steps, comprises a design phase, a plurality of dummy run phase and a fabrication stage.During the design phase, by IC design software each logic module of integrated circuit (IC) is integrated among the unified design arrangement figure usually.Then, during a dummy run phase, use and traditional come the testing integrated circuits design such as circuit simulation softwares such as (for example) spice parameter extraction softwares.The example of spice parameter extraction software comprises BSIMPRO (by being positioned at San Jose, the CelestryDesign Techologies Co., Ltd permission of CA) and Aurora (by being positioned at Mountain View, the Synopsys Co., Ltd permission of CA).During the integrated circuit fabrication stage, can be by on this silicon wafer, forming numerous kinds of IC structures forming several layers on the silicon wafer and remove a plurality of delamination area.

Usually, people wish to reduce and relevant cost and the expense of integrated circuit (IC) chip manufacturing.The conventional art that reduces IC chip manufacturing cost relates to deposition and the etching step quantity that minimizing is implemented during the IC chip manufacturing process.For this reason, only making integrated circuit with individual layer institute deposit spathic silicon is conventional practice in the industry.This technology makes manufacturing process uncomplicated relatively and cheap.In fact, in the manufacturing of logic element (it forms the part of integrated circuit), use the single polysilicon layer widely to accept, so that present the most frequently used commercially available circuit simulation software mainly is designed for and use the standard design and the manufacturing technology compatibility of single polysilicon layer.

Figure 1A-C promptly shows the example of the part of traditional integrated circuit (IC) design in graphic.Wherein Figure 1A shows the schematic diagram of a circuit 100, and circuit 100 comprises two transistors that are connected in series (being referred to herein as " cascade transistor circuit ").When including in as the part of the integrated circuit that adopts the traditional IC manufacturing technology, the cascade transistor circuit 100 of Figure 1A can be made shown in Figure 1B.Shown in Figure 1B, circuit part 150 comprises two transistors that are connected in series, and those transistors are to use the single polysilicon layer to make.More specifically, shown in Figure 1B, circuit part 150 comprises two the gate pole part 102a, the 102b that all make with the single polysilicon layer.In addition, circuit part 150 also comprises two oxide layer part 104a, 104b that all make with the single polysilicon layer.Circuit part 150 further comprises a substrate 110 (for example, silicon substrate), and substrate 110 comprises three doped region 105a, the 105b, the 105c that are formed in the doped well region 108.In Figure 1B example illustrated, circuit part 150 has been configured to two nmos pass transistors that are connected in series, and those nmos pass transistors comprise P-well area 108 and N ⁺Doped region 105a-c.This circuit can be used for (for example) and forms various conventional logic elements, for example NOR door, NAND door etc.

Fig. 1 C shows the example of traditional IC design arrangement Figure 170 of cascade transistor circuit shown in Figure 1A.Shown in Fig. 1 C, the conventional art of making cascade transistor circuit 100 is to use single polysilicon layer technology to implement, and wherein gate pole 102a and 102b are formed on the active area 115 of transistor circuit.Each gate pole 102a, 102b are all formed by same polysilicon layer.When adopting traditional term, each gate pole 102a, 102b all can be illustrated as by " polyl (polysilicon 1) " material and constitute, and this is because each gate pole all (that is, poly-t) is formed by identical ground floor deposit spathic silicon in those gate poles.According to traditional design rule, for guaranteeing made circuit operate as normal, each gate pole all needs a separately minimum range 117 among gate pole 102a and the 102b.

Although use standard compliant IC layout of single polysilicon layer and manufacturing technology, these standard techniques need particular design and layout requirement, and this may cause making full use of the space on silicon wafer or the substrate substrate.Therefore, should be appreciated that industry need constantly be improved the integrated circuit (IC) chip manufacturing technology, to adapt to and to utilize emerging new technology.

Summary of the invention

Different embodiment according to the subject invention is set forth the whole bag of tricks, the Apparatus and system that are used for forming a logic element on the integrated circuit of making on the substrate.One first gate structure that is made of one first polysilicon layer is formed on this substrate.Then, second gate structure that is made of one second polysilicon layer is formed on the substrate in a mode, and this mode is formed on the part of first gate structure part of second gate structure, forms an overlapping gate region by this.According to specific embodiment, this logic element can be corresponding to various logical elements or device, for example, and NAND door, AND door, NOR door, OR door, XOR gate, sram cell, latch etc.

According to specific embodiment, logic element of the present invention comprises a circuit part, this circuit part be designed to two be connected in series transistor or, another is chosen as, two transistors that are connected in parallel show identical substantially performance characteristic.In those embodiment, this first gate structure and second gate structure can be equivalent to the transistor gates of this circuit part.In addition, this logic element also can comprise the source electrode that is formed in the substrate and drain doping region, and one be formed at the active area between the source electrode and drain region in the substrate, and wherein this active area is designed for to make between source electrode and the drain region has electric current to flow through.

Should be appreciated that the various technology that use multilayer polysilicon of the present invention forms the transistor gates of logic element can provide the extra degree of freedom aspect the accurate adjustment transistor parameter, these parameters are for example allowed gate voltage etc. for oxide thickness, threshold voltage, maximum.

To the explanation of preferred embodiment of the present invention, will easily know other targets, feature and the advantage of various aspects of the present invention according to hereinafter, hereinafter explanation should be read in conjunction with the accompanying drawings.

Description of drawings

Figure 1A-C shows corresponding to the traditional integrated circuit (IC) design of a series connection transistor circuit and the example of manufacturing technology.

Fig. 2 A shows the part of a logic element that one specific embodiment is made according to the present invention.

Fig. 2 B-2J show a kind of according to the present invention one specific embodiment make the technology of a logic element.

Fig. 2 K shows the alternate embodiment of the part of a logic element that one specific embodiment is made according to the present invention.

Fig. 3 A-D shows the different embodiment of the cascade transistor circuit that can make according to the technology of the present invention.

Fig. 4 shows a kind of vertical view that is used to make the conventional design layout of a SRAM memory cell.

Fig. 5 shows that one can use the example of the SRAM memory cell design layout that the technology of the present invention makes.

Fig. 6 A-C shows corresponding to the traditional integrated circuit (IC) design of a transistor circuit in parallel and the example of manufacturing technology.

Fig. 7 A-D shows the different embodiment of the parallel transistor circuit that can make according to the technology of the present invention.

Embodiment

The present invention sets forth various in the technology that designs and make the multiple polysilicon layer of use in the various logical elements (for example, NAND door, AND door, NOR door, OR door, XOR gate, sram cell, latch etc.) that is used for semiconductor device.According to particular of the present invention, can reduce gate cell size and memory array cell size by using a plurality of polysilicon layers to make various transistor gates.By this kind mode, can realize reducing of integrated circuit chip area by the standard design rule that reduces corresponding to minimum poly-1 to poly-1 spacing.Therefore, for example, the technology of the present invention can realize the layout and/or the design of the overlapping polysilicon chip of not short circuit each other, and this is because can use a multilayer polysilicon manufacturing technology to form different polysilicon chips.According to a specific embodiment, these superimposed sheets can be made of at least two different polysilicon layers, and those polysilicon layers are separated on vertical by at least one insulating barrier (for example a, oxide layer).By this kind mode, can prevent the electrical short of the polysilicon chip that each is overlapping.And the technology that use multilayer polysilicon of the present invention forms the transistor gates of logic element can provide the extra degree of freedom aspect the accurate adjustment transistor parameter, and these parameters are for example allowed gate voltage etc. for oxide thickness, threshold voltage, maximum.

As mentioned above, traditional knowledge is informed the saving grace of the cost minimization that people reduce or will be relevant with making integrated circuit.Usually, a kind of technology that reduces or make this kind cost minimization is that the quantity that will be used to form the polysilicon layer of integrated circuit (IC) logic element minimizes.Recently, (for example be used to make some type memory, flash memory) manufacturing technology has been used a kind of double level polysilicon layer process, wherein different polysilicon layers is deposited on the silicon wafer to form the control gate and the floating gate of flash memory cell at different time.A design of integrated circuit is intended comprising in flash memory and both application-specific of conventional logic elements therein, and for (for example) forms flash memory cell, the manufacturing of integrated circuit (IC) chip may relate to pair of lamina polysilicon layer technology.Yet, during this kind integrated circuit is made, still keeping the conventional practice of using a single polysilicon layer to make the integrated circuit (IC) logic element.People wish that a reason using the design of single polysilicon layer and make integrated circuit (IC) logic element (even comprising at integrated circuit under the situation of flash memory) is because the design of single polysilicon layer circuit is simpler, therefore be easier to usually make, and foozle still less occurs.In addition, as mentioned above, commercially available the most frequently used circuit simulation software is designed to only compatible standard layout and the manufacturing technology of using the single polysilicon layer at present.The incompatible usually a plurality of polysilicon laminar designs of these circuit simulation softwares.

Yet, opposite with the traditional knowledge and the practice, the present invention informs people especially in the application that will make memory element (for example, flash memory, DRAM) and logic element on same integrated circuit (IC) chip, uses multiple polysilicon layer to make the saving grace of logic element.In those were used, people can utilize multiple polysilicon layer technology (for example, being used to make memory element) by designing the logic element that also uses multiple polysilicon layer.

Fig. 2 A shows the part 200 of the logic element that one specific embodiment is made according to the present invention.More specifically, circuit part 200 shown in Fig. 2 A be how according to the present invention one specific embodiment make the example of cascade transistor circuit (for example circuit shown in Figure 1A).According to specific embodiment, circuit part 200 can be used for making various logical elements, for example, and NAND door, AND door, NOR door, OR door, XOR gate, sram cell, latch etc.

Fig. 2 B-2I in graphic shows that one is used to make the specific embodiment of circuit part 200.Fig. 2 B-2I set forth a kind of according to the present invention one specific embodiment make the technology of a logic element.In the example shown in Fig. 2 B-2I, suppose that a silicon wafer is used for manufacturing one integrated circuit (IC) chip.In the preparation of IC chip manufacturing process, the available p-section bar of some part material of silicon wafer mixes, and forms a P-trap 208 thus.

Shown in Fig. 2 B, one first oxide layer 204a ' is formed on the surface of silicon wafer 210.After forming this first oxide layer 204a ', can on this first oxide layer, deposit one first polysilicon (poly-1) layer 202a '.Then, can remove or the several regions of etching poly-1 layer 202a ', form the first polysilicon layer part 202a by this, shown in Fig. 2 C.After forming the first polysilicon layer part 202a, can remove the several regions of the first oxide layer 204a ', to form one first oxide layer 204a by this, shown in Fig. 2 D.According to a specific embodiment, the formation of polysilicon layer and oxide layer and/or removal can use the known traditional IC chip fabrication techniques of person of ordinary skill in the field to realize.

Shown in Fig. 2 E and 2F, can on the several portions that comprises

part

202a and 204a of this silicon wafer, form and/or deposit one second oxide layer 204b ' and one second polysilicon (poly-2) layer 202b ' then.Shown in Fig. 2 G, can remove the several regions of poly-2 layer, to form the second polysilicon layer part 202b.Afterwards, can remove institute's favored area of this second oxide layer, to form the first oxide layer part 204b, shown in Fig. 2 H.Shown in Fig. 2 I, can adopt (for example) traditional ion embedding technology to form doped

region

205a and 205b then.According to specific embodiment, those doped

regions

205a and 205b can use such as n-section bar material such as arsenic and mix.Perhaps, can mix with a n-section bar material in zone 208, and forming a N-trap, and regional 205a and 205b can be with the doping of p-section bar material.

When being configured to two nmos pass transistors that are connected in series, circuit part 200 will be equivalent to the circuit part 275 of Fig. 2 J, and it can be schematically shown by the Figure 100 of signal shown in Figure 1A.Shown in Fig. 2 J, two gate poles of cascade transistor circuit 275 (for example gate pole B 202b and gate pole A 202a) are used to control from source electrode 205a the electric current to the 205b that drains and flow.

Circuit part shown in Figure 1B 150 (it represents a cascade transistor circuit that adopts conventional art to make) is compared with circuit part 275 shown in Fig. 2 J, can find some differences.For example, compare with Figure 1B, the spacing distance of gate pole A and gate pole B is much smaller among Fig. 2 J.More specifically, shown in Fig. 2 J, the spacing distance of gate pole 202b and gate pole 202a approximates the thickness of the second oxide layer part 204b.In addition, shown in Fig. 2 J, poly-2 layer segment 204b not only be positioned in a continuous manner on the poly-1 layer segment 202a and the first oxide layer part 204a but also with the two adjacency.Poly-2 layer segment 202b also with the region overlapping of poly-1 layer segment 202a.According to different embodiment, overlapping quantity can be in 0% overlapping (for example, with the gate region termination) variation to the scope of about 100% overlapping (for example, overlapping with gate region fully).

In addition, shown in Fig. 2 J, compare, remove a whole doped region from silicon substrate with Figure 1B.For example, shown in Fig. 2 J, circuit part 275 comprises two N ⁺ Doped region 205a, 205b.On the contrary, circuit part shown in Figure 1B 150 comprises 3 N ⁺Doped region, i.e. 105a, 105b and 105c.Figure 1B and 2J are compared, can find that promptly the doped region 105b that exists between A of gate pole shown in Figure 1B and the gate pole B is removing in the structure shown in Fig. 2 J.This can reduce the area of logic element on this disk, and the size of circuit small pieces and relevant manufacturing cost are reduced.

Should be appreciated that alternate embodiment of the present invention can comprise the feature that is different from shown in Fig. 2 J circuit part 275.For example, Fig. 2 K shows the alternate embodiment of a circuit part that one specific embodiment is made according to the present invention 280.Shown in embodiment among Fig. 2 K, circuit part 280 comprises two the overlapping polysilicon layer 282a, the 282b that are formed on the substrate 210.In this specific embodiment, substrate 210 is made of N-section bar material, and (p+) doped

region

285a, 285b are formed by P-section bar material.Between the

circuit part

275 and 280 one significantly difference is: the P-well area 208 of circuit part 275 (Fig. 2 J) is the transistorized local substrate as circuit part 275, and circuit part 280 does not comprise that one is different from the independent well area of substrate 210.But, in circuit part 208 (Fig. 2 H), by the transistorized local substrate of substrate 210 as circuit part 280.

Fig. 3 A-D illustrates the different embodiment of the cascade transistor circuit that can make according to the technology of the present invention.The stereogram of circuit part 200 among Fig. 3 A displayed map 2A.Fig. 3 B shows the stereogram of the circuit part 350 of an alternate embodiment, and circuit part 350 can be used for making up the cascade transistor circuit 100 shown in Figure 1A.

With reference to Fig. 3 A, it should be noted that the design of circuit part 300 is different from traditional circuit design aspect some.For example, as mentioned above, use different polysilicon layers to form transistor gates 202a, 202b.In addition, the position of gate structure and structure are different from traditional circuit design (for example design of traditional circuit shown in Figure 1B).For example, as shown in Figure 3A, gate pole 202b is overlapping with the part of a mode and gate pole 202a, and this mode is sandwiched between the active area of gate pole 202b and substrate 208 part of gate pole 202a.In addition, be different from conventional gate shown in Figure 1B structure (it typically is smooth structure), the structure of gate pole 202b and out-of-flatness, but be one to be included in the stepped configuration of the part of extending on level and the vertical both direction.Therefore, the top of gate pole 202b and lower surface are all not smooth substantially.

The design that also it should be noted that circuit part 300 is different from traditional non-volatile memory architecture aspect some.For example, in traditional non-volatile memory cell structure, can use two-layer polysilicon to form a traditional division gate cell that comprises a control gate and a floating gate.Usually, floating gate is designed to the electric insulation zone, it is a single non-volatile memory cells stored charge as a memory node.Be stored charge correctly, every other structure electric insulation in floating gate and the memory cell is very important.On the contrary,

gate structure

202a, 202b shown in Fig. 3 A all are not configured to zone through electric insulation in the mode of the floating gate structure that is similar to nonvolatile memory.But

gate structure

202a, 202b all can be electrically coupled to other parts of integrated circuit through one or more joining zone, so that required gate voltage is put on transistor circuit 300.For example, this is shown in Fig. 3 C illustrated embodiment.

Fig. 3 C shows the vertical view of the circuit layout 360 that a specific embodiment of a use the technology of the present invention designs.More specifically, Fig. 3 C illustrated embodiment represents that one is used for the particular of cascade transistor circuit (for example circuit shown in Fig. 3 A) layout.Illustrate traditional schematic diagram of a series connection transistor circuit among Figure 1A.Yet Fig. 3 D shows that one can be used for schematically showing the example of the schematic diagram 370 of circuit 360 shown in Fig. 3 C.

Shown in Fig. 3 C, cascade transistor circuit 360 comprises two the gate pole 382a, the 382b that have lap on active area 365.According to a specific embodiment, circuit 360 can adopt multiple polysilicon layer technology of the present invention manufacturing, and wherein one first gate pole (for example 382a) is formed by the poly-1 layer, and one second gate pole (for example 382b) is formed by the poly-2 layer.A part of overlaid of two gate poles is shown in zone 367.According to a specific embodiment, the width W 1 of gate pole overlapping region 367 is equal to or greater than the width W 2 of active area 365 at least.Shown in Fig. 3 C, each

gate pole

382a, 382b include corresponding joining zone 362a, a 362b, think that each gate pole provides electric contact.According to a specific embodiment, poly-1 layer and poly-2 layer can be made of for the known suitable electric conducting material of person of ordinary skill in the field polysilicon or other.

In addition, shown in Fig. 3 C, active area 365 can comprise an one source pole joining zone 364 and a drain contact zone 366.In Fig. 3 C example illustrated, gate

pole joining zone

362a, 362b place on the opposite side of active area 365, with guarantee to satisfy with each contact between the relevant design constraint of minimum spacing.Yet, should be appreciated that have many kinds of diverse ways to can be used for circuit 360 shown in the design of graphics 3C.For example, in an alternate implementation (not shown), the contact on each

gate pole

382a, 382b can be positioned at the same side of active area 365.Yet should be appreciated that these different constructing plans all have a common ground: some part of

gate pole

382a, 382b will overlap each other or termination on active area 365.Should be appreciated that circuit part 300 shows a kind of overlapping gate structure type of multilayer polysilicon that can be used for making the integrated circuit (IC) chip logic element among Fig. 3 A.With a problem of the structurally associated of circuit part 300 be: the variable gate length of gate pole 202b may be with respect to gate pole 202a mismatch.Be used for solving an embodiment who makes the gate pole mismatch problems owing to gate length is variable and be shown in graphic Fig. 3 B.

Fig. 3 B shows the stereogram of an alternate embodiment logic element circuit part 350 that one specific embodiment structure forms according to the present invention.Shown in Fig. 3 B, circuit part 350 comprises one first hydride layer 304a, a poly-1 gate pole 302a, one second oxide layer 304b and a poly-2 door-plate 302b.Shown in Fig. 3 B, the both sides of poly-2 gate pole 302b and poly-1 gate pole 302a are all adjacent.In addition, poly-2 gate pole 302b is overlapping with poly-1 gate pole 302a above substrate active area 308.Therefore, shown in Fig. 3 B, at least a portion of gate pole 302a is sandwiched between the active area 308 of gate pole 302b and silicon substrate.In addition, shown in Fig. 3 B, gate pole 302a and the gate pole 302b spacing that approximates the second oxide layer 304b thickness of being separated by.

Gate structure configuration advantage is to alleviate or to eliminate the described variable gate length issue above with reference to Fig. 3 A shown in Fig. 3 B.For example, according to a specific embodiments, because the length of (for example) gate pole 302b is to be determined by the mask edge that can correctly aim at, so the overall width W of gate pole 302b can keep constant.Therefore, the gate configuration of Fig. 3 B can be used for relaxing the problem of mismatch between poly-1 gate pole 302a and the poly-2 gate pole 302b.

It should be noted that

circuit part

300 and 350 only is intended to explain the structure on the active area of each circuit (for example, 208,308), and may not reflect all features of each circuit.Therefore, should be appreciated that

circuit part

300 and 350 can comprise other features that do not show among Fig. 3 A and the 3B.For example, this kind feature relates to the contact that is used to contact

gate structure

202a, 202b, 302a, 302b.Another feature relates to the structure of

gate structure

202a, 202b, 3028,302b.For example, in a constructing plan, each gate structure all can be configured to a polysilicon lines that can extend along either direction in the X-Z plane.Another feature relates to interpolation, and other can be used for making up the transistor of required logic element.

Should be appreciated that the technology that use multilayer polysilicon of the present invention forms logic element can provide the extra degree of freedom aspect the various transistor parameters of accurate adjustment, these parameters are for example allowed gate voltage etc. for oxide thickness, threshold voltage, maximum.For example, according to different embodiment, be the various transistor parameters of accurate adjustment, poly-1 and poly-2 gate can be made for different thickness respectively.According to a specific implementation, two same sizes (for example, width and length can be benefited because of having 2 different threshold voltages, because its gate separately can be made of 2 different oxide layers by) logic transistor.In addition, should be appreciated that in traditional MOS transistor, drain electrode and all horizontal proliferation below gate region of source junction can reduce effective gate length thus and aggravate short-channel effect.Yet, use series transistor circuit configurations of the present invention, get final product (for example) and eliminate a knot (and corresponding horizontal proliferation) in to the transistor that is connected in series at each, improve the short-channel effect of this (a bit) cascade transistor circuit thus.

Employed another common circuit is shown among Fig. 6 A in the conventional logic elements design.Fig. 6 A shows that one comprises the circuit part 600 (being referred to herein as parallel transistor circuit 600) of 2 parallel connected transistors.A kind of conventional design layout that is used for making parallel transistor circuit 600 is shown in Fig. 6 C.Shown in Fig. 6 C, traditional parallel transistor circuit layout 670 is included in and forms 2 poly-1

gate pole

652a, 652b on the active area 681 of silicon

substrate.Gate pole

652a, 652b are to use the single polysilicon layer to form.According to traditional design rule, those gate poles minimum spacing 679 that need be separated from each other.In the embodiment shown in Fig. 6 C, source area 672a, the 672b of parallel transistor circuit via an electric connection line 677 electrical couplings together.

Fig. 6 B illustrates a profile that uses the parallel transistor circuit part 650 that traditional IC manufacturing technology makes.Circuit part 650 shown in Fig. 6 B is to use the single polysilicon layer, adopts the technology that is similar to cascade transistor circuit part 150 among above-mentioned manufacturing Figure 1B to make.Shown in Fig. 6 B, circuit part 650 comprises the first oxide layer part 604a, 604b (its two all formed by the first identical oxide layer), poly-1 gate pole part 602a, 602b (it is all formed by a single polysilicon layer) and 3 different doped region 605a, 605b, 605c.

Fig. 7 A shows the stereogram of the parallel transistor circuit part 700 that one specific embodiment is made according to the present invention.Shown in Fig. 7 A, circuit part 700 comprises one first oxide layer part 704a, a poly-1 gate pole 702a, one second oxide layer part 704b, a poly-1 gate pole 702b and 2 doped region 705a, 705b, and these 2 doped region 705a, 705b can be used as the source electrode and the drain region of parallel transistor circuit.According to a specific implementation, the technology type that is used for parallel transistor circuit part 700 shown in the shop drawings 7A is similar to the described technology above with reference to graphic Fig. 2 B-2I.Therefore, for example, poly-1 gate pole 702a can be formed by one first polysilicon layer, and poly-2 gate pole 702b can be formed by second polysilicon layer that is different from first polysilicon layer.In addition, oxide layer part 704a can be formed by one first oxide layer, and oxide layer part 704b then can be formed by second oxide layer that is different from first oxide layer.

Fig. 7 C shows that one can be used for making the vertical view of the layout 760 of parallel transistor circuit shown in Fig. 7 A.Fig. 7 D shows a schematic diagram 770, and it is used to schematically show the parallel transistor circuit design 760 shown in Fig. 7 C.Shown in Fig. 7 C, parallel transistor circuit design 760 comprises a poly-1 gate pole 782a and a poly-2 gate pole 782b.Each

gate pole

782a, 782b all to small part source electrode and the drain electrode between active area 765 on.Each gate pole includes corresponding contact areas 762a, 762b.The part of two gate poles is overlapping at regional 767 places as shown in the figure.According to a specific embodiment, the width W 2 of gate pole overlapping region 767 is less than the width W 1 of active area 760.

A difference shown in parallel transistor circuit design shown in Fig. 7 C and Fig. 6 C between traditional parallel circuits design is that circuit shown in Fig. 6 C comprises two via an electric connection line 677 electrical

couplings source area

672a, 672b together.On the contrary, shown in Fig. 7 C, 760 in parallel transistor circuit comprises a single source area 764 and a single drain region 766.

Fig. 7 B shows the stereogram of the alternate embodiment of a parallel transistor circuit part 750 of making according to the technology of the present invention.Shown in Fig. 7 B, circuit part 750 comprises one first oxide layer part 754a, a poly-1 gate pole 752a, one second oxide layer part 754b, a poly-2 gate pole 752b and 2

doped region

755a, 755b, and these 2

doped region

755a, 755b can be used as the source electrode and the drain region of parallel transistor circuit.According to a specific embodiments, the technology type that is used for parallel transistor circuit part 750 shown in the shop drawings 7B is similar to the described technology above with reference to graphic Fig. 2 B-2I.Therefore, for example, poly-1 gate pole 752a can be formed by one first polysilicon layer, and poly-2 gate pole 752b then can be formed by second polysilicon layer that is different from first polysilicon layer.In addition, oxide layer part 754a can be formed by one first oxide layer, and oxide layer part 754b can be formed by second oxide layer that is different from first oxide layer.

It should be noted that one of them structural distinctions between the parallel transistor design is shown in the design of serial transistor shown in Fig. 3 C and Fig. 7 C: shown in Fig. 3 C, each

gate pole

382a, 382b all can cut off the electric current that flow to drain electrode 366 from source electrode 364.Yet shown in Fig. 7 C,

gate pole

782a, 782b but all can not control the electric current that flow to drain electrode 766 from source electrode 764 fully.But each gate pole only control flows is crossed the part of the electric current of active area.Yet,, for example, preferablely apply suitable control voltage to two

gate pole

782a, 782b and stop electric current to flow to drain electrode from source electrode according to embodiment shown in Fig. 7 C.

Should be appreciated that each circuit shown in Fig. 3 A-3D and the 7A-7D can be used for making the different logic element of various formation integrated circuit (IC) chip parts.Those logic elements comprise NAND door, AND door, NOR door, OR door, XOR gate, latch etc.In addition, those logic elements can comprise static storage cell, for example SRAM.Fig. 4 shows that one is used to make the vertical view of the conventional design layout of SRAM memory cell 400.Usually, the SRAM memory cell is to adopt the standard design that only comprises a single polysilicon layer to make.This design makes manufacturing process more uncomplicated relatively and more cheap.Therefore, as shown in Figure 4, traditional sram cell design comprises three poly-1 parts 402,404a, 404b, and wherein each part forms by same polysilicon layer.

Conventional design constraints requires each poly-1 part (for example, 402,404a, 404b) minimum spacing that separates each other (for example, spacing A) to prevent short circuit with (for example).In addition, as shown in Figure 4, traditional sram cell design comprises a P ⁺ Doped region 406 and N ⁺Doped region 408.The part of sram cell 400 is formed on the P-trap 420.In this figure, each metal interconnecting wires between not shown regional 406,408 and 404.

Relevant with traditional sram cell manufacturing technology various design constraints require various structural designs with sram cell be at least one minimum prescribed amount of separation of other structures in the sram cell (or with SRAM in other structures overlapping).For this reason, the size of traditional sram cell can not reduce to less than minimum designated size.For example, if minimum feature size is 100nm, then the sram cell size has 1m at least usually ²Area.Yet, use manufacturing technology of the present invention, can reduce the memory array cell size by using multiple polysilicon layer to make each transistor.In this way, can realize reducing of memory array cell dimensioned area corresponding to the IC design rule of minimum poly-1 to poly-1 spacing by reducing.

Fig. 5 shows that one can utilize the example of the SRAM memory cell design layout that the technology of the present invention makes.As shown in Figure 5, sram cell 500 comprises at least one poly-1 layer 502 and multiple poly-2

layer

504a, 504b, and wherein poly-2

layer

504a, 504b are formed by a polysilicon layer that is different from poly-1 layer 502.Each polysilicon layer 502,504a, 504b all comprise a corresponding gate pole district 530 and a corresponding interconnection district 532.According to a specific embodiment, interconnection district can be equivalent to be formed at some part of the polysilicon layer in passive (or) district of sram cell 500.In the embodiment shown in fig. 5, the part of sram cell 500 is to be formed on the P-trap 520.In addition, in this figure, each metal interconnecting wires between not shown regional 506,508 and 504.

According to a specific embodiment, can adopt one with make the various transistors that comprised in the sram cell 500 shown in Figure 5 with reference to the described transistor manufacturing technology of Fig. 2 B-2I similar methods in graphic.In one of many possible embodiment, can make a multiple polysilicon layer sram cell, wherein the transmission gate gated transistors comprises the gate pole that is formed by the poly-1 layer, and on draw and/or pull-down transistor comprises the gate pole that is formed by the poly-2 layer.

As shown in Figure 5, the size of sram cell 500 can (for example) some part by making poly-1 layer 502 and some overlap (shown in 515) of poly-2

layer

504a, 504b reduced.This designing technique also helps to reduce poly-1 layer 502 and N ⁺Spacing (shown in B ') between the zone 508.In addition, shown in embodiment among Fig. 5, overlapping interconnect area 532 places (for example, on the passive region of sram cell 500) that appear at polysilicon layer of 515 place's polysilicon regions.

Although show in Fig. 5, sram cell design 500 also can comprise at least two different oxide layers, insulated from each other and and the surrounding structure insulation to help each polysilicon layer.For example, first oxide layer can be positioned under the poly-1 part 502, and second oxide layer can be positioned under poly-2 layer 504a, the 504b, makes poly-2 layer and poly-1 layer electric insulation thus.

As in circuit shown in Fig. 3 A-D and the 7A-D, use multiple polysilicon layer providing the extra degree of freedom aspect the accurate adjustment transistor parameter in sram cell design shown in Figure 5, these parameters are for example allowed gate voltage or the like for oxidated layer thickness, threshold voltage, maximum.

Although this paper has elaborated some preferred embodiments of the present invention with reference to accompanying drawing, but should be appreciated that, the present invention is not limited only to those definite embodiment, and the person of ordinary skill in the field can carry out various changes and modification to it, and this does not deviate from the present invention's spirit category that is defined in the claims of enclosing.For example, according to some specific embodiment, the transistor gates material that is used to form logic element of the present invention can be made of the combination (for example, titanium silicide) of electric conducting material (for example, titanium), semi-conducting material (for example, polysilicon) or two kinds of materials.In addition, the insulating barrier described in each embodiment of the application's case (for example, oxide layer) can be made of the insulation or the dielectric material of silicon dioxide and/or other types.

Claims

1. A method of forming a logic element of an integrated circuit, said logic element comprising a circuit portion adapted to perform at least one logic operation, said integrated circuit formed on a substrate, said method comprising:

forming a first gate on the substrate;

forming a second gate on the substrate;

wherein a second portion of the second gate is formed on a first portion of the first gate, thereby forming a first overlapping gate region;

After forming the first and second gates, forming a first doped region in the substrate, the first doped region serving as a source region of the circuit portion;

After forming the first and second gates, forming a second doped region in the substrate, the second doped region serving as a drain region of the circuit portion;

A transistor active region is formed between the source region and the drain region on the substrate, the transistor active region being designed to allow current to flow between the source and drain regions Pass;

wherein the first gate includes an active region portion and a contact region portion, the active region portion corresponding to a portion of the first gate above the transistor active region;

removing portions of the second gate in a manner that forms the second gate such that at least a portion of the second gate is formed over the active region portion of the first gate above the whole; and

The logic element is formed in a manner that causes the logic element to perform at least one logic operation.

2. The method of claim 1, wherein a portion of the first overlapping gate region is created over the transistor active region; and

Wherein the width of the first overlapping gate region is at least equal to or greater than the width of the active region of the transistor.

3. The method of claim 1, wherein a portion of the first overlapping gate region is created over the transistor active region;

wherein the first portion of the first gate is formed on the transistor active area; and

Wherein at least a part of the second gate is formed over the entirety of the first part of the first gate.

4. The method of claim 1, wherein the first gate has a first threshold voltage value associated therewith; and

Wherein the second gate has a second threshold voltage associated therewith, and the second threshold voltage is different from the first threshold voltage.

5. The method of claim 4, wherein the first gate is formed so as not to function as a floating gate; and

Wherein the second gate is formed so as not to be a floating gate.

6. The method of claim 1, further comprising forming the logic element in a manner such that the logic element does not perform a memory store operation.

7. A logic unit of an integrated circuit, said logic unit operable to perform at least one logic operation, said integrated circuit fabricated on a substrate, said logic unit comprising:

a first circuit portion adapted to exhibit performance characteristics that are performance characteristics of at least two transistors connected in series;

Wherein the first circuit part includes:

a first doped region formed on the substrate, the first doped region serving as a source region of the first circuit portion;

a second doped region formed on the substrate, the second doped region serving as a drain region of the first circuit portion;

a transistor active region formed on said substrate between said source and drain regions, said transistor active region being adapted to allow current to flow through said source and drain regions;

a first gate formed over a first portion of the transistor active area;

a first dielectric layer formed between the first gate and the substrate such that the first gate is electrically isolated from the substrate;

a second gate formed over a second portion of the transistor active area;

a second dielectric layer formed between the second gate and the substrate such that the second gate is insulated from the substrate conductor;

Wherein the first gate includes an active region portion and a contact region portion, the active region portion of the first gate is corresponding to the active region above the transistor active region in the first gate part of; and

Wherein the second gate is formed such that at least a portion of the second gate is formed over the entirety of the active region portion of the first gate.

8. The logic cell of claim 7, wherein the logic element includes a single source region and a single drain region.

9. The logic unit of claim 7, wherein the logic element corresponds to an element selected from the group consisting of: NAND gate, AND gate, NOR gate, OR gate, XOR gate, and latch device.

10. A circuit portion of a logic element, said logic element being part of an integrated circuit, said logic element operable to perform at least one logic operation, said integrated circuit fabricated on a substrate, said circuit Sections include:

a first doped region formed on the substrate, the first doped region serving as a source region of the circuit portion;

a second doped region formed on the substrate, the second doped region serving as a drain region of the circuit portion;

a transistor active region formed on said source and drain regions on said substrate, said transistor active region being designed to allow current to flow through said source and drain regions;

a first gate formed on a first portion of the transistor active region, the first gate adapted to control a first active channel of current flow between the source and drain regions;

a second gate formed on a second portion of the transistor active region, the second gate being adapted to control a second active channel of current flow between the source and drain regions ;

wherein the transistor active area comprises the first active channel and the second active channel; and

Wherein the first portion of the transistor active area and the second portion of the transistor active area correspond to the entirety of the transistor active area.

11. The circuit portion of claim 10, wherein a first portion of the first gate is formed over a portion of the second gate, thereby forming a first overlapping gate region.

12. The circuit portion of claim 10, wherein the circuit portion includes a single source region and a single drain region.

13. The circuit portion of claim 10, wherein the circuit portion corresponds to a transistor, the transistor comprising:

a source corresponding to the source region;

a drain corresponding to the drain region;

a first transistor gate corresponding to the first gate; and

A second transistor gate corresponding to the second gate.

14. The circuit portion of claim 10, wherein the logic unit corresponds to an element selected from the group consisting of: NAND gates, AND gates, NOR gates, OR gates, XOR gates, and latches device.

15. A logic unit of an integrated circuit, said logic unit operable to perform at least one logic operation, said integrated circuit fabricated on a substrate, said logic unit comprising:

a first circuit portion adapted to exhibit performance characteristics that are performance characteristics of at least two transistors connected in parallel;

Wherein said first circuit part comprises:

a transistor active region formed on said source and drain regions on said substrate, said transistor active region being adapted to allow current to flow through said source and drain regions;

a first gate formed on a first portion of the transistor active region, the first gate being adapted to control a first active channel of electrical current between the source and drain regions;

a second gate formed on a second portion of the transistor active region, the second gate being adapted to control a second active channel of electrical current between the source and drain regions; and

Wherein the logic unit corresponds to an element selected from the following group: NAND gate, AND gate, NOR gate, OR gate, XOR gate and a latch.

16. The logic unit of claim 15, wherein the first circuit portion comprises:

a single source corresponding to the source region;

a single drain corresponding to the drain region; and

Wherein the transistor active area includes the first active channel and the second active channel.