CN101022113A - Non-volatile memory and methods of manufacturing and operating the same - Google Patents

Abstract

The invention discloses a nonvolatile memory, which is provided with a plurality of grid structures, a plurality of charge storage layers and two doped regions. The grid structures are arranged on the substrate in series. The charge storage layers are respectively arranged between two adjacent grid structures, and the charge storage layers and the grid structures form a storage unit column. The two doped regions are respectively arranged in the substrate at two sides of the memory cell row.

Description

Non-volatile memory and methods of manufacturing and operating the same

technical field

The present invention relates to a semiconductor device, and in particular to a non-volatile memory and its manufacturing method and operation method.

Background technique

Among all kinds of non-volatile memory products, the electrically erasable ones have the advantage of being able to store, read, and erase data multiple times, and the stored data will not disappear after power off. Programmable read-only memory (EEPROM) has become a memory element widely used in personal computers and electronic equipment.

A typical EEPROM uses doped polysilicon to make a floating gate and a control gate. Moreover, in order to avoid the problem of misjudgment of data due to excessive erasing phenomenon is too serious during erasing of typical EEPROMs. A select gate is additionally provided on the sidewalls of the control gate, the floating gate, and the substrate to form a split-gate structure.

In addition, in the known technology, a charge trapping layer is also used to replace the polysilicon floating gate, and the material of the charge trapping layer is, for example, silicon nitride. The silicon nitride charge trapping layer usually has a layer of silicon oxide above and below, forming a silicon oxide/silicon nitride/silicon oxide (oxide-nitride-oxide, ONO for short) composite layer. As disclosed in US Pat. No. 5,930,631, there is an electrically erasable programmable read-only memory with a split-gate structure. However, since the split gate structure requires a larger split gate area and thus has a larger memory cell size, its memory cell size is larger than that of an EEPROM with stacked gates. , resulting in the so-called inability to increase the integration of components.

On the other hand, since the AND-OR gate (NAND) type array connects memory cells in series, its integration level is higher than that of the NOR-gate (NOR) type array. Therefore, making the split-gate flash memory cell array into an AND-OR gate (NAND) array structure can make the elements denser. However, the program of writing and reading memory cells in an AND-OR gate (NAND) array is more complicated, and because many memory cells are connected in series in the array, the read current of the memory cells is small, and The operation speed of the memory unit is slowed down, and the performance of the device cannot be improved.

Contents of the invention

In view of this, an object of the present invention is to provide a non-volatile memory and its manufacturing method and operation method. This kind of non-volatile memory can store two-bit data in a single memory cell, so the device can be improved. level of integration.

Another object of the present invention is to provide a non-volatile memory and its manufacturing method and operation method. This kind of non-volatile memory can utilize Source-Side Injection (SSI) for programming operation, and The programming speed can be improved, and the performance of the memory can be improved.

Another object of the present invention is to provide a non-volatile memory and its manufacturing method and operation method. The process of the non-volatile memory is simple and the manufacturing cost can be reduced.

The invention proposes a nonvolatile memory, which includes multiple gate structures, multiple charge storage layers, and two doped regions. A plurality of gate structures are serially arranged on the substrate. A plurality of charge storage layers are respectively arranged between two adjacent gate structures, and the charge storage layers and the gate structures form a row of memory cells, wherein the charge storage layers are arranged in pairs. The two doped regions are respectively arranged in the substrate on both sides of the memory cell row.

In the above non-volatile memory, the gate structure includes: a plurality of first gate structures and a plurality of second gate structures. A plurality of first gate structures are disposed on the base, and there are gaps between two adjacent first gate structures. A plurality of second gate structures are disposed between the first gate structures and fill up the gaps.

In the above non-volatile memory, the charge storage layer is disposed on the sidewall of the first gate structure in the form of a spacer.

In the above non-volatile memory, the charge storage layer is disposed on the sidewall of the first gate structure with an L-shaped cross section.

In the above non-volatile memory, a first dielectric layer is respectively arranged between the charge storage layer and the gate structure. The material of the first dielectric layer includes silicon oxide.

In the above-mentioned nonvolatile memory, a second dielectric layer is respectively arranged between the charge storage layer and the substrate. The material of the second dielectric layer includes silicon oxide.

In the above non-volatile memory, each first gate structure includes: a first gate dielectric layer, a first gate and a top cover layer. The first gate dielectric layer is disposed on the substrate. The first gate is disposed on the first gate dielectric layer. The top cover layer is disposed on the first grid. Each second gate structure includes: a second gate dielectric layer and a second gate. The second gate dielectric layer is disposed on the substrate. The second gate is disposed on the second gate dielectric layer. Materials of the first gate dielectric layer and the second gate dielectric layer include silicon oxide. The material of the first gate and the second gate includes doped polysilicon.

In the above-mentioned nonvolatile memory, the material of the charge storage layer includes silicon nitride or doped polysilicon.

In the nonvolatile memory of the present invention, since the gate structure (the first gate structure and the second gate structure) and the charge storage layer are connected in series without gaps to form a memory cell row, the memory cell can be improved. line integration. Moreover, the charge storage layer between the gate structures (the first gate structure and the second gate structure) can store one bit of data.

In addition, the gate length of the second gate structure can be determined by the gap length between the first gate structures, so by reducing the gap length between the first gate structures, the size of the second gate structure can be reduced. The length of the gate increases the integration of components.

In addition, if the section of the charge storage layer is L-shaped, and part of the charge storage layer is located between the second gate structure and the substrate, when the nonvolatile memory of this embodiment is erased, the second gate The vertical electric field generated between the electrode structure and the substrate can improve the erasing efficiency.

The invention provides a method for manufacturing a nonvolatile memory. Firstly, a substrate is provided, and a plurality of first gate structures are formed on the substrate, and there are gaps between two adjacent first gate structures. After forming the tunneling dielectric layer on the substrate, a plurality of charge storage layers are formed on the sidewall of the first gate structure. A plurality of second gate structures are formed on the substrate, and the second gate structures fill up the gaps between the first gate structures. The charge storage layer, the second gate structure and the first gate structure form a row of memory cells. Then, two doped regions are formed in the substrate on both sides of the row of memory cells.

In the above-mentioned manufacturing method of the non-volatile memory, the steps of forming the first gate structure on the substrate are as follows: after forming the first gate dielectric layer on the substrate, forming the first conductor on the first gate dielectric layer layer. A top cover layer is formed on the first conductive layer. patterning the top cover layer, the first conductor layer and the first gate dielectric layer.

In the above-mentioned manufacturing method of the nonvolatile memory, the material of the first gate dielectric layer includes silicon oxide.

In the above-mentioned manufacturing method of the non-volatile memory, the step of forming a plurality of charge storage layers on the sidewall of the first gate structure is as follows: firstly, after forming the first dielectric layer and the charge storage material layer on the substrate, performing anisotropic etching to remove part of the first dielectric layer and part of the charge storage material layer. The material of the charge storage layer includes silicon nitride.

In the above-mentioned manufacturing method of the nonvolatile memory, after the step of forming the charge storage layer on the sidewall of the first gate structure, patterning the charge storage layer is further included to form a plurality of charge storage blocks. Materials for the charge storage block include silicon nitride or doped polysilicon.

In the above-mentioned manufacturing method of the non-volatile memory, the step of forming a plurality of charge storage layers on the sidewall of the first gate structure is as follows: firstly, the first dielectric layer and the charge storage material layer are formed on the substrate, and then A sacrificial layer is formed on the substrate. Next, anisotropic etching is performed to remove part of the sacrificial layer and form a plurality of spacers on the surface of the charge storage material layer. Using the spacer as a mask, part of the charge storage material layer and part of the first dielectric layer are removed to expose the base, and then the spacer is removed.

In the above method of manufacturing the nonvolatile memory, the cross section of the charge storage layer is L-shaped. The material of the charge storage layer includes silicon nitride.

In the above-mentioned manufacturing method of the nonvolatile memory, after the step of forming the charge storage layer on the sidewall of the first gate structure, patterning the charge storage layer is further included to form a plurality of charge storage blocks. Materials for the charge storage block include silicon nitride or doped polysilicon.

In the above-mentioned manufacturing method of the nonvolatile memory, the material of the tunneling dielectric layer includes silicon oxide.

In the above-mentioned manufacturing method of the non-volatile memory, the steps of forming the second gate structure on the substrate are as follows: forming a second gate dielectric layer on the substrate, and forming a second conductor on the second gate dielectric layer layer, and the second conductor layer fills the gap between the first gate structures. Part of the second conductor layer is removed until the first gate structure is exposed.

In the above method of manufacturing the nonvolatile memory, the method for removing part of the second conductor layer includes a chemical mechanical polishing method. The material of the second gate dielectric layer includes silicon oxide.

In the above-mentioned manufacturing method of the nonvolatile memory, the material of the first conductive layer and the second conductive layer includes doped polysilicon. In the manufacturing method of the nonvolatile memory of the present invention, since the first gate structure, the charge storage layer and the second gate structure are connected in series without gaps, the integration degree of the memory array can be improved. Moreover, the steps of forming the nonvolatile memory in the present invention are simpler than the known process, so the manufacturing cost can be reduced.

The present invention provides an operation method of a non-volatile memory, which is suitable for a memory cell array. The memory cell array includes: a plurality of memory cell rows, and each memory cell row includes: a plurality of gate structures arranged in series on a substrate ; A plurality of charge storage layers are respectively arranged between the gate structures, wherein the charge storage layers are arranged in pairs; and the first source/drain region and the second source/drain region are respectively arranged In the substrate on both sides of the memory cell row; a plurality of word lines are connected to the gate structure of the same column, and the method includes applying a first voltage to the selected word line when performing a programming operation; other non-selected word lines applying a second voltage to the element line; applying a third voltage to the first source/drain region of the selected memory cell row; applying a fourth voltage to the second source/drain region of the selected memory cell row; wherein the first The voltage is greater than or equal to the threshold voltage of the gate structure, the second voltage is greater than the first voltage, and the fourth voltage is greater than the third voltage, so as to use the source side injection effect to program the selected word line adjacent to the second source/drain The charge storage layer on the side of the region.

In the above operation method of the nonvolatile memory, the first voltage is about 1.5 volts, the second voltage is about 7 volts, the third voltage is about 0 volts, and the fourth voltage is about 2.5 volts.

In the operation method of the above-mentioned non-volatile memory, when performing the erasing operation, the fifth voltage is applied to the word line, and the sixth voltage is applied to the substrate, so that electrons stored in the charge storage layer are introduced into the substrate, wherein The voltage difference between the fifth voltage and the sixth voltage will cause the FN tunneling effect.

In the above-mentioned operation method of the non-volatile memory, the voltage difference is about -12 to -20 volts. The fifth voltage is 0 volts, and the sixth voltage is 12 volts.

In the above-mentioned operation method of the non-volatile memory, when performing the read operation, the seventh voltage is applied to the selected word line; the eighth voltage is applied to other non-selected word lines; the eighth voltage is applied to the selected memory cell row The ninth voltage is applied to the first source/drain region; the tenth voltage is applied to the second source/drain region of the selected memory cell row to read the adjacent selected word line, and is located at the second source/drain The charge storage layer on the side of the drain region, wherein the ninth voltage is greater than the tenth voltage, the seventh voltage is greater than or equal to the threshold voltage of the gate structure, and is less than the voltage difference between the ninth voltage and the tenth voltage, and the eighth voltage is greater than the seventh voltage .

In the above operation method of the nonvolatile memory, the seventh voltage is about 3.5 volts, the eighth voltage is about 7 volts, the ninth voltage is about 1.5 volts, and the tenth voltage is about 0 volts.

In the above operation method of the non-volatile memory, when performing the read operation, when performing the read operation, the eleventh voltage is applied to a certain word line; the twelfth voltage is applied to other non-selected word lines; Applying a thirteenth voltage to the second source/drain region of the selected memory cell row; applying a fourteenth voltage to the first source/drain region of the selected memory cell row to read adjacent selected words Line, and the charge storage layer located on the side of the first source/drain region, wherein the thirteenth voltage is greater than the fourteenth voltage, the eleventh voltage is greater than or equal to the critical voltage of the gate structure, and is less than the fourteenth voltage and the first The voltage difference of the thirteenth voltage, the twelfth voltage is greater than the eleventh voltage.

In the above operation method of the nonvolatile memory, the eleventh voltage is about 3.5 volts, the twelfth voltage is about 7 volts, the thirteenth voltage is about 1.5 volts, and the fourteenth voltage is about 0 volts.

The operation method of the non-volatile memory of the present invention uses Source-Side Injection (SSI) to program a single bit of a single memory cell, and utilizes the FN tunneling effect to perform programming of the memory cell erase. Therefore, its electron injection efficiency is high, so the memory cell current during operation can be reduced, and the operation speed can be increased at the same time. Therefore, the current consumption is small, which can effectively reduce the power loss of the entire chip.

The present invention provides a method for operating a nonvolatile memory, which is suitable for a memory cell array. The memory cell array includes: a plurality of memory cell rows, and each memory cell row includes: a plurality of first gate structures arranged on a substrate , there are gaps between two adjacent first gate structures; a plurality of second gate structures are disposed in the gaps between the first gate structures; a plurality of charge storage layers are respectively disposed between the first gate structures and the second gate structures between the two gate structures, wherein each charge storage layer includes a portion interposed between the first gate structure and the substrate; and the first source/drain region and the second source/drain region , respectively arranged in the substrates on both sides of the memory cell row; a plurality of word lines connected to the first gate structure in the same column; a plurality of selection gate lines connected to the second gate structure in the same column, the method includes: When performing a programming operation, a first voltage is applied to the selected word line; a second voltage is applied to other unselected word lines and the selection gate line; a second voltage is applied to the first source/drain region of the selected memory cell row. Three voltages; applying a fourth voltage to the second source/drain region of the selected memory cell row; wherein the first voltage is greater than or equal to the threshold voltage of the first gate structure, the second voltage is greater than the first voltage, and the fourth voltage is greater than The third voltage is used to program the charge storage layer adjacent to the selected word line and on the side of the second source/drain region by using the source side injection effect.

In the above operation method of the nonvolatile memory, the first voltage is about 1.5 volts, the second voltage is about 9 volts, the third voltage is about 0 volts, and the fourth voltage is about 3.5 volts.

In the above-mentioned operation method of the non-volatile memory, when performing the programming operation, the fifth voltage is applied to the selected word line; the sixth voltage is applied to the other non-selected word lines and the selection gate line; applying a seventh voltage to the second source/drain region of the cell row; applying an eighth voltage to the first source/drain region of the selected memory cell row; wherein the fifth voltage is greater than or equal to the threshold voltage of the first gate structure , the sixth voltage is greater than the fifth voltage, and the eighth voltage is greater than the seventh voltage, so as to use the source side injection effect to program the charge storage layer adjacent to the selected word line and located at the side of the first source/drain region.

In the above operation method of the nonvolatile memory, the fifth voltage is about 1.5 volts, the sixth voltage is about 9 volts, the seventh voltage is about 0 volts, and the eighth voltage is about 3.5 volts.

In the above-mentioned operation method of the non-volatile memory, when performing the erasing operation, the ninth voltage is applied to the word line and the selection gate line, and the tenth voltage is applied to the substrate, so that the electrons stored in the charge storage layer Introduced into the substrate, wherein the voltage difference between the ninth voltage and the tenth voltage will cause the FN tunneling effect.

In the above-mentioned operation method of the non-volatile memory, the voltage difference is about -12 to -20 volts. The ninth voltage is 0 volts, and the tenth voltage is 12 volts.

In the above operation method of the non-volatile memory, when performing the read operation, the eleventh voltage is applied to the selected word line; the twelfth voltage is applied to other unselected word lines and the selection gate line; Applying a thirteenth voltage to the first source/drain region of the selected memory cell row; applying a fourteenth voltage to the second source/drain region of the selected memory cell row to read adjacent selected words Line, and the charge storage layer located on the side of the second source/drain region, wherein the thirteenth voltage is greater than the fourteenth voltage, the eleventh voltage is greater than or equal to the critical voltage of the gate structure when the charge storage layer is not programmed, and is less than The critical voltage of the gate structure after the charge storage layer is programmed, the twelfth voltage is greater than the eleventh voltage.

In the above operation method of the nonvolatile memory, the eleventh voltage is about 2.5 volts, the twelfth voltage is about 6 volts, the thirteenth voltage is about 1.5 volts, and the fourteenth voltage is about 0 volts.

In the above operation method of the non-volatile memory, when performing the read operation, the fifteenth voltage is applied to the selected word line; the sixteenth voltage is applied to other unselected word lines and the selection gate line; Applying the seventeenth voltage to the second source/drain region of the selected memory cell row; applying the eighteenth voltage to the first source/drain region of the selected memory cell row to read adjacent selected words Line, and the charge storage layer located on the side of the first source/drain region, wherein the seventeenth voltage is greater than the eighteenth voltage, and the fifteenth voltage is greater than or equal to the critical voltage of the gate structure when the charge storage layer is not programmed, and less than The critical voltage of the gate structure after the charge storage layer is programmed, the sixteenth voltage is greater than the fifteenth voltage.

In the above operation method of the nonvolatile memory, the fifteenth voltage is about 2.5 volts, the sixteenth voltage is about 6 volts, the seventeenth voltage is about 1.5 volts, and the eighteenth voltage is about 0 volts.

The operation method of the non-volatile memory of the present invention uses Source-Side Injection (SSI) to program a single bit of a single memory cell, and utilizes the FN tunneling effect to perform programming of the memory cell erase. Therefore, its electron injection efficiency is high, so the memory cell current during operation can be reduced, and the operation speed can be increased at the same time. Therefore, the current consumption is small, which can effectively reduce the power consumption of the entire chip.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments are described below in detail together with accompanying drawings.

Description of drawings

FIG. 1A is a top view of a preferred embodiment of the non-volatile memory of the present invention.

FIG. 1B is a cross-sectional view of a preferred embodiment of the non-volatile memory of the present invention.

FIG. 1C is a cross-sectional view of another preferred embodiment of the non-volatile memory of the present invention.

FIG. 2A is a schematic diagram of an example of the programming operation of the non-volatile memory of the present invention.

FIG. 2B is a schematic diagram of an example of the read operation of the non-volatile memory of the present invention.

FIG. 2C is a schematic diagram of another example of the read operation of the non-volatile memory of the present invention.

FIG. 2D is a schematic diagram of an example of the erasing operation of the non-volatile memory of the present invention.

FIG. 3A is a schematic diagram of an example of the programming operation of the non-volatile memory of the present invention.

FIG. 3B is a schematic diagram of an example of the programming operation of the non-volatile memory of the present invention.

FIG. 3C is a schematic diagram of an example of the read operation of the non-volatile memory of the present invention.

FIG. 3D is a schematic diagram of another example of the read operation of the non-volatile memory of the present invention.

FIG. 3E is a schematic diagram of an example of the erasing operation of the non-volatile memory of the present invention.

4A to 4D are cross-sectional views illustrating the manufacturing process of a preferred embodiment of the nonvolatile memory of the present invention.

5A to 5D are cross-sectional views illustrating the manufacturing process of a preferred embodiment of the nonvolatile memory of the present invention.

[Description of main component symbols]

200, 300: Substrate 202: Component isolation structure 204: Active area

206a-206e: first gate structure 208a-208d, 308, 320: second gate structure

210, 210a, 302, 302a, 312, 312a, 316: dielectric layer

212: Gate dielectric layer 214: Gate 216: Top cover layer

218: gate dielectric layer 220: gate 304, 304a, 318: conductor layer

306, 306a: roof layer 310: clearance

313: charge storage material layer 314, 313a, C11～C38: charge storage layer

315, 315a: sacrificial layer 322, 324, SD11～SD32: source/drain region

GL1～GL9: Gate lines R1～R3: Memory cell rows

SG1～SG5: select gate line WL1～WL9: word line

Detailed ways

FIG. 1A is a top view of a preferred embodiment of the non-volatile memory of the present invention. FIG. 1B is a cross-sectional view of the structure of a preferred embodiment of the non-volatile memory of the present invention, and FIG. 1B shows a cross-section along line A-A' in FIG. 1A.

Referring to FIG. 1A, the nonvolatile memory array of the present invention includes a substrate 200, a plurality of gate lines GL1-GL9, a plurality of charge storage layers C11-C38, and a plurality of source/drain regions SD11-SD32.

The substrate 200 is, for example, a silicon substrate. For example, an element isolation structure 202 is disposed in the substrate 200 to define an active region 204 . The active regions 204 are, for example, striped and extend in the X direction. A plurality of gate lines GL1 - GL9 are disposed on the substrate 200 , for example, the gate lines GL1 - GL9 are arranged in parallel and extend in the Y direction. The intersections of the gate lines GL1 - GL9 and the active region 204 are, for example, gate structures. The charge storage layers C11 - C38 are, for example, disposed between two adjacent gate structures. In the X direction (row direction), these gate structures and charge storage layers C11-C38 located on the active region 204 are connected in series without gaps to form memory cell rows R1-R3 respectively; in the Y direction ( Column direction), these gate structures located on the active region 204 are respectively connected in series by gate lines GL1 - GL9 . The source/drain regions SD11˜SD32 are, for example, disposed in the substrate 200 on both sides of the memory cell rows R1˜R3.

Next, the structure of the nonvolatile memory of the present invention will be described. Here, only the memory cell row R1 is taken as an example for illustration.

Please refer to FIG. 1A and FIG. 1B at the same time. The nonvolatile memory structure of the present invention includes a substrate 200, a plurality of first gate structures 206a-206e, a plurality of second gate structures 208a-208d (by a plurality of gate lines Multiple gate structures formed by GL1-GL9 include first gate structures 206a-206e and second gate structures 208a-208d), multiple charge storage layers C11-C18, dielectric layer 210, source/drain area SD11 and source/drain area SD12.

The substrate 200 is, for example, a silicon substrate. The substrate 200 can be a P-type substrate or an N-type substrate. The device isolation structure 202 is disposed in the substrate 200 to define an active region 204 .

The first gate structures 206 a - 206 e are disposed on the substrate 200 , and each of the first gate structures 206 a - 206 e is composed of, for example, a gate dielectric layer 212 , a gate 214 , and a top cover layer 216 . The gate dielectric layer 212 is, for example, disposed on the substrate 200 . The gate 214 is, for example, disposed on the gate dielectric layer 212 . The capping layer 216 is, for example, disposed on the gate 214 . The material of the gate dielectric layer 212 is, for example, silicon oxide; the material of the gate 214 is, for example, doped polysilicon. The material of the cap layer 216 is, for example, silicon oxide.

The second gate structures 208a-208d are disposed on the substrate 200 and located between the adjacent first gate structures 206a-206e. Each of the second gate structures 208 a - 208 d is composed of, for example, a gate dielectric layer 218 and a gate 220 . The gate dielectric layer 218 is, for example, disposed on the substrate 200 . The gate 220 is, for example, disposed on the gate dielectric layer 218 . The material of the gate dielectric layer 218 is, for example, silicon oxide; the material of the gate 220 is, for example, doped polysilicon.

The plurality of charge storage layers C11 - C18 are, for example, respectively disposed between the first gate structures 206 a - 206 e and the second gate structures 208 a - 208 d. Moreover, between the adjacent first gate structures 206 a - 206 e , the charge storage layers are arranged in pairs. Materials of the charge storage layers C11 - C18 include conductive materials (such as doped polysilicon) or charge trapping materials (such as silicon nitride). When the charge storage layers C11-C18 are made of doped polysilicon, the charge storage layers C11-C18 are, for example, in a block shape, and only the first gate structures 206a-206e and the second gate structures located on the active region 204 Between 208a and 208d. When the charge storage layers C11-C18 are made of silicon nitride, the charge storage layers C11-C18 are, for example, striped, that is, the charge storage layers C11, C21, and C31 are the same silicon nitride layer, and there is no cut-off between them. . It is located between the entire gate lines GL1-GL9. The charge storage layers C11 - C18 may be located on the sidewalls of the first gate structures 206 a - 206 e like spacers. The gate dielectric layer 218 between the charge storage layers C11 - C18 and the gate 220 is used as an isolation layer to isolate the charge storage layers C11 - C18 and the gate 220 .

The dielectric layer 210 is, for example, disposed between the first gate structures 206 a - 206 e and the charge storage layers C11 - C18 and between the substrate 200 and the charge storage layers C11 - C18 . The dielectric layer 210 between the first gate structures 206a-206e and the charge storage layers C11-C18 is used as an isolation layer to isolate the first gate structures 206a-206e from the charge storage layers C11-C18. The dielectric layer 210 between the substrate 200 and the charge storage layers C11 - C18 is used as a tunneling dielectric layer. The material of the dielectric layer 210 is, for example, silicon oxide.

The first gate structures 206 a - 206 e , the second gate structures 208 a - 208 d , and the charge storage layers C11 - C18 are connected in series without gaps to form a memory cell row R1 .

The source/drain region SD11 and the source/drain region SD12 are respectively disposed in the substrate 200 on both sides of the memory cell row R1, for example. The source/drain region SD11 and the source/drain region SD12 are, for example, n-type doped regions or p-type doped regions.

In the above-mentioned non-volatile memory, since the first gate structures 206a-206e, the second gate structures 208a-208d, and the charge storage layers C11-C18 are connected in series without gaps to form the memory cell row R1, Therefore, the degree of integration of memory cell rows can be increased. Moreover, the charge storage layers C11 - C18 between the first gate structures 206 a - 206 e and the second gate structures 208 a - 208 d can store one bit of data.

In addition, the gate length of the second gate structures 208a-208d can be determined by the gap length between the first gate structures 206a-206e. Therefore, by reducing the gap length between the first gate structures 206a-206e, Therefore, the gate lengths of the second gate structures 208 a - 208 d can be reduced to improve the integration of components.

FIG. 1C is a structural cross-sectional view of another preferred embodiment of the non-volatile memory of the present invention, and FIG. 1C is shown as a cross-section along line A-A' in FIG. 1A. In FIG. 1C , components that are the same as those in FIGS. 1A and 1B are given the same reference numerals, and description thereof will be omitted. Only the differences are explained here.

Please refer to FIG. 1C , the difference between the nonvolatile memory of this embodiment and the nonvolatile memory shown in FIG. 1B is that the cross-sections of the charge storage layers C11 - C18 are L-shaped. That is, part of the charge storage layers C11 - C18 are respectively located between the second gate structures 208 a - 208 d and the substrate 200 . The gate dielectric layer 218 a located between the charge storage layers C11 - C18 and the gate 220 is used as an isolation layer to isolate the charge storage layers C11 - C18 and the gate 220 .

The dielectric layer 210a is, for example, disposed between the first gate structures 206a-206e and the charge storage layers C11-C18 and between the substrate 200 and the charge storage layers C11-C18. The dielectric layer 210a between the first gate structures 206a-206e and the charge storage layers C11-C18 is used as an isolation layer to isolate the first gate structures 206a-206e from the charge storage layers C11-C18. The dielectric layer 210 a between the substrate 200 and the charge storage layers C11 - C18 is used as a tunneling dielectric layer. The material of the dielectric layer 210a is, for example, silicon oxide.

In the above non-volatile memory, part of the charge storage layers C11 - C18 are respectively located between the second gate structures 208 a - 208 d and the substrate 200 . The charges are stored in part of the charge storage layers C11 - C18 between the second gate structures 208 a - 208 d and the substrate 200 . Therefore, when performing an erasing operation on the nonvolatile memory of this embodiment, the erasing efficiency can be improved by the vertical electric field generated between the second gate structures 208 a - 208 d and the substrate 200 .

In the above-mentioned embodiment, it is described as an example that 9 gate structures and 8 charge storage layers are connected in series. Of course, in the present invention, the number of gate structures and charge storage layers connected in series can be an appropriate number according to actual needs. For example, a memory cell row can be connected in series with 33 to 65 gate structures and 32 to 64 charge storage layers.

Next, the operation mode of a preferred embodiment of the nonvolatile memory of the present invention will be described. FIG. 2A is a schematic diagram of an example of the programming operation of the non-volatile memory of the present invention. FIG. 2B is a schematic diagram of an example of the read operation of the non-volatile memory of the present invention. FIG. 2C is a schematic diagram of another example of the read operation of the non-volatile memory of the present invention. FIG. 2D is a schematic diagram of an example of the erasing operation of the non-volatile memory of the present invention.

Regarding the operation method of the non-volatile memory of the present invention, only a preferred embodiment is provided below for illustration. However, the method of operating the nonvolatile memory of the present invention is not limited to these methods.

This embodiment is described by taking the non-volatile memory shown in FIG. 1A and FIG. 1B as an example. Moreover, in this embodiment, since the gate lines GL1 - GL9 are used as word lines, in FIGS. 2A to 2D , the gate lines GL1 - GL9 are represented as word lines WL1 - WL9 respectively. In the following descriptions, the charge storage layer C13 is taken as an example for illustration.

Please refer to FIG. 2A at the same time. During the programming operation, electrons are stored in the charge storage layer C13 as an example for illustration. In the selected memory cell row R1, a voltage Vp1 is applied to the selected word line WL3 located on the source/drain region SD11 side of the selected charge storage layer C13 and adjacent to the selected charge storage layer C13. The voltage Vp1 is, for example, It's around 2.5 volts. A voltage Vp2 is applied to other unselected word lines WL1 ˜ WL2 , WL4 ˜ WL9 , and the voltage Vp2 is, for example, about 7 volts. A voltage Vp3 is applied to the source/drain region SD12 of the selected memory cell row R1, and the voltage Vp3 is, for example, about 2.5 volts. A voltage Vp4 is applied to the source/drain region SD11 of the selected memory cell row R1, and the voltage Vp4 is, for example, about 0 volts. The voltage Vp1 is greater than or equal to the threshold voltage of the gate structure, the voltage Vp2 is greater than the voltage Vp1, and the voltage Vp3 is greater than the voltage Vp4, so as to use the source side injection effect (Source-Side Injection, SSI) to program the source on the selected word line WL3 / the selected charge storage layer C13 on the side of the drain region SD12.

In the above programming operation, since the programming operation is performed by utilizing the source-side injection (SSI) effect, the programming efficiency is high, and the programming time can be shortened. Moreover, in the above programming method, when programming the charge storage layers in the row of memory cells, it is preferable to program the charge storage layers sequentially from the end of the source region of the row of memory cells. For example, when programming the memory cell row R1, the memory cells can be programmed according to the order of the charge storage layers C18, C17, C16...C11, so as to avoid damage caused by some electrons stored in the charge trapping layer. program disturb situations and improve programming performance.

Please refer to FIG. 2B, when the charge storage layer C13 is read, in the selected memory cell row R1, it is located on the source/drain region SD11 side of the selected charge storage layer C13 and adjacent to the side of the selected charge storage layer C13. A voltage Vr1 is applied to the selected word line WL3, and the voltage Vr1 is, for example, about 3.5 volts. A voltage Vr2 is applied to the other unselected word lines WL1 - WL2 , WL4 - WL9 , and the voltage Vr2 is, for example, about 7 volts. A voltage Vr3 is applied to the source/drain region SD12 of the selected memory cell row R1, and the voltage Vr3 is, for example, about 0 volts. A voltage Vr4 is applied to the source/drain region SD11 of the selected memory cell row R1, and the voltage Vr4 is, for example, about 1.5 volts. The voltage Vr4 is greater than the voltage Vr3, the voltage Vr1 is greater than or equal to the threshold voltage of the gate structure, and is less than the voltage difference between the voltage Vr4 and the voltage Vr3, and the voltage Vr2 is greater than the voltage Vr1. Since the total charge in the charge storage layer is negative at this time, the channel below the charge storage layer is closed and the current is very small; while the total charge in the charge storage layer is slightly positive, the channel below the charge storage layer is open and the current is large, so it can be used Whether the digital information stored in the charge storage layer is "1" or "0" is judged by the magnitude of the channel switch/channel current under the charge storage layer.

Please refer to FIG. 2C to illustrate another read operation method of the present invention. When reading the charge storage layer C12, in the selected memory cell row R1, the source/drain region of the selected charge storage layer C12 is A voltage Vr5 is applied to the selected word line WL3 on the SD12 side and adjacent to the selected charge storage layer C12, and the voltage Vr5 is, for example, about 3.5 volts. A voltage Vr6 is applied to the other unselected word lines WL1 , WL3 ˜ WL9 , and the voltage Vr6 is, for example, about 7 volts. A voltage Vr7 is applied to the source/drain region SD11 of the selected memory cell row R1, and the voltage Vr7 is, for example, about 0 volts. A voltage Vr8 is applied to the source/drain region SD12 of the selected memory cell row R1, and the voltage Vr8 is, for example, about 1.5 volts. The voltage Vr8 is greater than the voltage Vr7 , the voltage Vr1 is greater than or equal to the threshold voltage of the gate structure and less than the voltage difference between the voltage Vr8 and the voltage Vr7 , and the voltage Vr6 is greater than the voltage Vr5 . Since the total charge in the charge storage layer is negative at this time, the channel below the charge storage layer is closed and the current is very small; while the total charge in the charge storage layer is slightly positive, the channel below the charge storage layer is open and the current is large, so it can be used Whether the digital information stored in the charge storage layer is "1" or "0" is judged by the magnitude of the channel switch/channel current under the charge storage layer.

Please refer to FIG. 2D. During erasing, voltage Ve1 is applied to the word lines WL1-WL9, and voltage Ve2 is applied to the substrate to make the source/drain region SD11 and source/drain region SD12 float, so that The electrons stored in the charge storage layer are introduced into the substrate, so that the data in the memory cells are erased. The voltage difference between the voltage Ve1 and the voltage Ve2 will cause the FN tunneling effect. The voltage difference between the voltage Ve1 and the voltage Ve2 is, for example, about -12 to -20 volts. For example, the voltage Ve1 is 0 volts, and the voltage Ve2 is 12 volts.

In the operation method of the non-volatile memory of the present invention, it utilizes the source side injection effect (Source-Side Injection, SSI) to program in the unit of a single bit of a single memory cell, and utilizes the FN tunneling effect to store Cell erasure. Therefore, its electron injection efficiency is high, so the memory cell current during operation can be reduced, and the operation speed can be increased at the same time. Therefore, the current consumption is small, which can effectively reduce the power consumption of the entire chip.

The operation method of the non-volatile memory disclosed in the above embodiments is not limited to be applied only to the non-volatile memory shown in FIG. 1B , and can also be applied to the non-volatile memory shown in FIG. 1C .

Next, the operation mode of another preferred embodiment of the nonvolatile memory of the present invention will be described. FIG. 3A is a schematic diagram of an example of the programming operation of the non-volatile memory of the present invention. FIG. 3B is a schematic diagram of an example of the programming operation of the non-volatile memory of the present invention. FIG. 3C is a schematic diagram of an example of the read operation of the non-volatile memory of the present invention. FIG. 3D is a schematic diagram of another example of the read operation of the non-volatile memory of the present invention. FIG. 3E is a schematic diagram of an example of the erasing operation of the non-volatile memory of the present invention.

This embodiment is described by taking the non-volatile memory shown in FIG. 1A and FIG. 1C as an example. Moreover, in FIG. 2A to FIG. 2D, since the gate lines GL2, GL4, GL6, and GL8 are used as word lines in the operation method of this embodiment, the gate lines GL2, GL4, GL6, and GL8 are respectively Word lines WL1-WL4 are used to represent. On the other hand, the gate lines GL1 , GL3 , GL5 , GL7 , and GL9 are used as selection gate lines, so the gate lines GL2 , GL4 , GL6 , and GL8 are respectively represented by selection gate lines SG1 to SG5 .

Referring to FIG. 3A , during the programming operation, electrons are stored in the charge storage layer C14 as an example for illustration. A voltage Vp1 is applied to the selected word line WL2, and the voltage Vp1 is, for example, about 1.5 volts. A voltage Vp2 is applied to the other unselected word lines WL1 , WL3 , WL4 and the selection gate lines SG1 - SG5 , and the voltage Vp2 is, for example, about 9 volts. A voltage Vp3 is applied to the source/drain region SD12 of the selected memory cell row R1, and the voltage Vp3 is, for example, about 3.5 volts. A voltage Vp4 is applied to the source/drain region SD11 of the selected memory cell row R1, and the voltage Vp4 is, for example, about 0 volts. The voltage Vp1 is greater than or equal to the threshold voltage of the gate structure, the voltage Vp2 is greater than the voltage Vp1, and the voltage Vp3 is greater than the voltage Vp4, so as to use the source side injection effect (Source-Side Injection, SSI) to program the source on the selected word line WL2 / the selected charge storage layer C14 on the side of the drain region SD12.

Referring to FIG. 3B , during the programming operation, electrons are stored in the charge storage layer C13 as an example for illustration. A voltage Vp1 is applied to the selected word line WL2, and the voltage Vp1 is, for example, about 1.5 volts. A voltage Vp2 is applied to the other unselected word lines WL1 , WL3 , WL4 and the selection gate lines SG1 - SG5 , and the voltage Vp2 is, for example, about 9 volts. A voltage Vp3 is applied to the source/drain region SD11 of the selected memory cell row R1, and the voltage Vp3 is, for example, about 3.5 volts. A voltage Vp4 is applied to the source/drain region SD12 of the selected memory cell row R1, and the voltage Vp4 is, for example, about 0 volts. The voltage Vp1 is greater than or equal to the threshold voltage of the gate structure, the voltage Vp2 is greater than the voltage Vp1, and the voltage Vp3 is greater than the voltage Vp4, so as to use the source side injection effect (Source-Side Injection, SSI) to program the source on the selected word line WL2 / the selected charge storage layer C13 on the side of the drain region SD11.

In the above programming operation, since the programming operation is performed by utilizing the source-side injection (SSI) effect, the programming efficiency is high, and the programming time can be shortened.

Referring to FIG. 3C , when the charge storage layer C14 is read, a voltage Vr1 is applied to the selected word line WL2 , and the voltage Vr1 is, for example, about 2.5 volts. A voltage Vr2 is applied to the other unselected word lines WL1 , WL3 , WL4 and the selection gate lines SG1 - SG5 . The voltage Vr2 is, for example, about 6 volts. A voltage Vr3 is applied to the source/drain region SD11 of the selected memory cell row R1, and the voltage Vr3 is, for example, about 1.5 volts. A voltage Vr4 is applied to the source/drain region SD12 of the selected memory cell row R1, and the voltage Vr4 is, for example, about 0 volts. The voltage Vr3 is greater than the voltage Vr4, the voltage Vr1 is greater than or equal to the threshold voltage of the gate structure when the charge storage layer C14 is not programmed, and is less than the threshold voltage of the gate structure after the charge storage layer C14 is programmed, and the voltage Vr2 is greater than the voltage Vr1. Since the total charge in the charge storage layer is negative at this time, the channel below the charge storage layer is closed and the current is very small; while the total charge in the charge storage layer is slightly positive, the channel below the charge storage layer is open and the current is large, so it can be used Whether the digital information stored in the charge storage layer is "1" or "0" is judged by the magnitude of the channel switch/channel current under the charge storage layer.

Referring to FIG. 3D , when the charge storage layer C13 is read, a voltage Vr1 is applied to the selected word line WL2 , and the voltage Vr1 is, for example, about 2.5 volts. A voltage Vr2 is applied to the other unselected word lines WL1 , WL3 , WL4 and the selection gate lines SG1 - SG5 . The voltage Vr2 is, for example, about 6 volts. A voltage Vr3 is applied to the source/drain region SD12 of the selected memory cell row R1, and the voltage Vr3 is, for example, about 1.5 volts. A voltage Vr4 is applied to the source/drain region SD11 of the selected memory cell row R1, and the voltage Vr4 is, for example, about 0 volts. The voltage Vr3 is greater than the voltage Vr4, the voltage Vr1 is greater than or equal to the threshold voltage of the gate structure when the charge storage layer C13 is not programmed, and is less than the threshold voltage of the gate structure after the charge storage layer C13 is programmed, and the voltage Vr2 is greater than the voltage Vr1. Since the total charge in the charge storage layer is negative at this time, the channel below the charge storage layer is closed and the current is very small; while the total charge in the charge storage layer is slightly positive, the channel below the charge storage layer is open and the current is large, so it can be used Whether the digital information stored in the charge storage layer is "1" or "0" is judged by the magnitude of the channel switch/channel current under the charge storage layer.

Please refer to FIG. 3E. During erasing, a voltage Ve1 is applied to the word lines WL1-WL4 and select gate lines SG1-SG5, and a voltage Ve2 is applied to the substrate, so that the source/drain region SD11, source/drain The region SD12 is floating, so that the electrons stored in the charge storage layer are introduced into the substrate, and the data in the memory cells are erased. The voltage difference between the voltage Ve1 and the voltage Ve2 will cause the FN tunneling effect. The voltage difference between the voltage Ve1 and the voltage Ve2 is, for example, about -12 to -20 volts. For example, the voltage Ve1 is 0 volts, and the voltage Ve2 is 12 volts.

In the operation method of the non-volatile memory of the present invention, it utilizes the source side injection effect (Source-Side Injection, SSI) to program in the unit of a single bit of a single memory cell, and utilizes the FN tunneling effect to store Cell erasure. Therefore, its electron injection efficiency is high, so the memory cell current during operation can be reduced, and the operation speed can be increased at the same time. Therefore, the current consumption is small, which can effectively reduce the power loss of the entire chip. Moreover, part of the charge storage layers C11 - C18 are respectively located between the word lines WL1 - WL4 and the substrate. Therefore, during the erasing operation, the erasing efficiency can be improved by the vertical electric field generated between the word lines WL1 - WL4 and the substrate.

The operation method of the non-volatile memory disclosed in the above embodiments is not limited to be applied to the non-volatile memory shown in FIG. 1C , and can also be applied to the non-volatile memory shown in FIG. 1B .

Next, the manufacturing method of the non-volatile memory of the present invention will be described. FIG. 4A to FIG. 4D are cross-sectional views illustrating the manufacturing process of a preferred embodiment of the non-volatile memory of the present invention. FIGS. 4A to 4D are cross sections along line A-A' in FIG. 1A , and FIGS. 4A to 4D are cross sections of the manufacturing process of the nonvolatile memory shown in FIG. 1B .

First, please refer to FIG. 4A , a substrate 300 is provided, such as a silicon substrate. An element isolation structure (not shown) is formed in the substrate 300 to define an active region. The method for forming the device isolation structure is, for example, a shallow trench isolation process.

Next, a dielectric layer 302 , a conductive layer 304 and a capping layer 306 are formed on the substrate 300 . The material of the dielectric layer 302 is, for example, silicon oxide, and its formation method is, for example, thermal oxidation. The material of the conductor layer 306 is, for example, doped polysilicon. The method for forming the conductor layer 306 is, for example, to form a layer of undoped polysilicon layer by chemical vapor deposition, and then perform ion implantation to form it, or to implant impurities in situ. formed by chemical vapor deposition. The material of the cap layer 306 is, for example, silicon oxide, and the method of forming the cap layer 306 is, for example, chemical vapor deposition.

Referring to FIG. 4B , the cap layer 306 , the conductive layer 304 and the dielectric layer 302 are patterned to form a plurality of gate structures 308 . The method for patterning the capping layer 306 , the conductive layer 304 and the dielectric layer 302 is, for example, a photolithographic etching technique. The select gate structure 308 is, for example, composed of a cap layer 306a, a conductive layer 304a and a dielectric layer 302a. For example, there is a gap 310 between two adjacent gate structures 308 . The conductive layer 304a is, for example, used as a gate, and the dielectric layer 302a is, for example, used as a gate dielectric layer.

Next, another dielectric layer 312 is formed on the substrate 300 , and the dielectric layer 312 covers the gate structure 308 . The material of the dielectric layer 312 is, for example, silicon oxide. The method for forming the dielectric layer 312 is, for example, chemical vapor deposition.

Referring to FIG. 4C , a charge storage layer 314 is formed on the sidewall of the gate structure 308 . The material of the charge storage layer 314 includes a conductive material (such as doped polysilicon) or a charge trapping material (such as silicon nitride). The charge storage layer 314 is formed by, for example, firstly forming a layer of charge storage material and then performing an anisotropic etching process. In the step of forming the charge storage layer 314, part of the dielectric layer 312 is also removed until the substrate 300 is exposed, thereby forming the dielectric layer 312a. The dielectric layer 312a is, for example, located between the charge storage layer 314 and the gate structure 308 and between the charge storage layer 314 and the substrate 300 . The dielectric layer 312 a between the charge storage layer 314 and the gate structure 308 is used as an isolation layer to isolate the charge storage layer 314 from the gate structure 308 . The dielectric layer 312 a between the charge storage layer 314 and the substrate 300 is used as a tunneling dielectric layer. If the material of the charge storage layer 314 is a conductive material (for example, doped polysilicon), the charge storage layer 314 needs to be patterned so that the charge storage layer 314 is divided into blocks (charge storage blocks), and the charge storage blocks are, for example, located in on the active area. If the material of the charge storage layer 314 is a charge trapping material (such as silicon nitride), it is not necessary to further divide the charge storage layer 314 into blocks.

Next, another dielectric layer 316 is formed on the substrate 300 , and the dielectric layer 316 covers the gate structure 308 and the charge storage layer 314 . The material of the dielectric layer 316 is, for example, silicon oxide. The dielectric layer 316 is formed by, for example, chemical vapor deposition.

Referring to FIG. 4D , a plurality of conductive layers 318 are formed on the substrate 300 , and the conductive layers 318 fill the gaps 310 between the gate structures 308 . The step of forming the conductive layer 318 is, for example, to form a layer of conductive material on the substrate 300 first, and then planarize by chemical mechanical polishing or etching back until the dielectric layer 316 is exposed. The material of the conductor layer 318 is, for example, doped polysilicon, and its formation method is, for example, to form a layer of undoped polysilicon layer by chemical vapor deposition, and then perform ion implantation; or it can also be formed by implanting impurities on site. formed by chemical vapor deposition.

The conductive layer 318 and the dielectric layer 316 form another gate structure 320 .

The dielectric layer 316 between the charge storage layer 314 and the conductive layer 318 is used as an isolation layer to isolate the charge storage layer 314 from the conductive layer 318 . The dielectric layer 316 between the substrate 300 and the conductive layer 318 serves as a gate dielectric layer.

The gate structure 308 , the charge storage layer 314 and the gate structure 320 are connected in series without gaps to form a row of memory cells. Source/drain regions 322, 324 are then formed in the substrate 300 on both sides of the memory cell row. Subsequent processes for completing the memory array are well known to those skilled in the art and will not be repeated here.

In the above embodiment, since the gate structure 308 , the charge storage layer 214 and the gate structure 320 are connected in series without gaps, the integration of the memory array can be improved. Moreover, the steps of forming the nonvolatile memory in the present invention are simpler than the known process, so the manufacturing cost can be reduced.

5A to 5D are cross-sectional views illustrating the manufacturing process of another embodiment of the non-volatile memory of the present invention. FIGS. 5A to 5D are cross sections along line A-A' in FIG. 1A , and FIGS. 5A to 5D are cross sections of the manufacturing process of the nonvolatile memory shown in FIG. 1C . 5A to 5D follow from FIG. 4B . In FIGS. 5A to 5D , components that are the same as those in 4A to 4D are given the same reference numerals, and detailed description thereof will be omitted.

Referring to FIG. 5A , after the gate structure 308 and the dielectric layer 312 are formed, a charge storage material layer 313 is formed on the substrate 300 . The material of the charge storage material layer 313 includes a conductive material (such as doped polysilicon) or a charge trapping material (such as silicon nitride). The method for forming the charge storage material layer 313 is, for example, chemical vapor deposition.

Then, a sacrificial layer 315 is formed on the substrate 300 . The material of the sacrificial layer 315 is, for example, a material having a different etch selectivity from that of the charge storage material layer 313 . In this embodiment, the material of the sacrificial layer 315 is, for example, silicon oxide. Of course, the sacrificial layer 315 can be appropriately changed corresponding to the material of the charge storage layer 313 .

Referring to FIG. 5B , part of the sacrificial layer 315 is removed, and a sacrificial layer 315 a (intermediate silicon wall) is formed on the sidewall of the gate structure 308 . A method for removing part of the sacrificial layer 315 is, for example, an anisotropic etching method.

Next, using the sacrificial layer 315a (silicon wall) as a mask, part of the charge storage material layer 313 is removed until the dielectric layer 312 is exposed, thereby forming the charge storage layer 313a. A method for removing part of the charge storage material layer 313 is, for example, an etching method. The cross section of the charge storage layer 313 a is, for example, L-shaped.

Referring to FIG. 5C, the sacrificial layer 315a (inter-silicon wall) is removed. During the formation step of removing the sacrificial layer 315a (inter-silicon wall), part of the dielectric layer 312 is also removed until the substrate 300 is exposed, thereby forming Dielectric layer 312a. The dielectric layer 312a is, for example, located between the charge storage layer 313a and the gate structure 308 and between the charge storage layer 313a and the substrate 300 . The dielectric layer 312 a between the charge storage layer 313 a and the gate structure 308 is used as an isolation layer to isolate the charge storage layer 314 from the gate structure 308 . The dielectric layer 312a between the charge storage layer 313a and the substrate 300 serves as a tunneling dielectric layer.

After removing the sacrificial layer 315a (silicon wall) and part of the dielectric layer 312, if the material of the charge storage layer 313a is a conductive material (for example, doped polysilicon), it is necessary to pattern the charge storage layer 313a so that the charge The storage layer 313a is divided into blocks (charge storage blocks), and the charge storage blocks are located on the active region, for example. If the material of the charge storage layer 313a is a charge trapping material (such as silicon nitride), there is no need to further divide the charge storage layer 313a into blocks.

Referring to FIG. 5D , another dielectric layer 316 is formed on the substrate 300 , and the dielectric layer 316 covers the gate structure 308 and the charge storage layer 314 . The material of the dielectric layer 316 is, for example, silicon oxide. The dielectric layer 316 is formed by, for example, chemical vapor deposition.

A plurality of conductive layers 318 are formed on the substrate 300 , and the conductive layers 318 fill the gaps 310 between the gate structures 308 . The step of forming the conductive layer 318 is, for example, to form a layer of conductive material on the substrate 300 first, and then use chemical mechanical polishing or etching back to planarize until the top cover layer 306a is exposed. The material of the conductor layer 318 is, for example, doped polysilicon, and its formation method is, for example, to form a layer of undoped polysilicon layer by chemical vapor deposition, and then perform ion implantation; or it can also be formed by implanting impurities on site. formed by chemical vapor deposition. The conductive layer 318 and the dielectric layer 316 form another gate structure 320 .

The dielectric layer 316 between the charge storage layer 313 a and the conductive layer 318 is used as an isolation layer to isolate the charge storage layer 313 a from the conductive layer 318 . The dielectric layer 316 between the substrate 300 and the conductive layer 318 serves as a gate dielectric layer.

The gate structure 308 , the charge storage layer 313 a and the gate structure 320 are connected in series without gaps to form a row of memory cells. Source/drain regions 322, 324 are then formed in the substrate 300 on both sides of the memory cell row. Subsequent processes for completing the memory array are well known to those skilled in the art and will not be repeated here.

In the above embodiment, since the gate structure 308 , the charge storage layer 313 a and the gate structure 320 are connected in series without gaps, the integration of the memory array can be improved. Moreover, since part of the charge storage layer 313 a is respectively located between the gate structure 320 and the substrate 300 . Therefore, when performing an erasing operation on the nonvolatile memory of this embodiment, the erasing efficiency can be improved by the vertical electric field generated between the gate structure 320 and the substrate 300 . In addition, the steps of forming the non-volatile memory in the present invention are relatively simple compared with the known process, so the manufacturing cost can be reduced.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore The scope of protection of the present invention should be defined by the claims.

Claims (50)

1. A non-volatile memory comprising: A plurality of gate structures are arranged in series on the substrate; A plurality of charge storage layers are respectively arranged between two adjacent gate structures, and the plurality of charge storage layers and the plurality of gate structures form a row of memory cells, wherein the plurality of charge storage layers are paired in pairs configuration; and The two doping regions are respectively arranged in the substrate on both sides of the memory cell row. 2. The non-volatile memory of claim 1, wherein the plurality of gate structures comprise: A plurality of first gate structures disposed on the substrate, with a gap between two adjacent first gate structures; and A plurality of second gate structures are disposed between the plurality of first gate structures and fill up the gap. 3. The nonvolatile memory of claim 2, wherein the plurality of charge storage layers are disposed on sidewalls of the plurality of first gate structures in the form of spacers. 4. The nonvolatile memory as claimed in claim 3, wherein the material of the plurality of charge storage layers comprises silicon nitride or doped polysilicon. 5. The nonvolatile memory as claimed in claim 2, wherein the plurality of charge storage layers are disposed on sidewalls of the plurality of first gate structures in an L-shape. 6. The nonvolatile memory as claimed in claim 5, wherein the material of the plurality of charge storage layers comprises silicon nitride or doped polysilicon. 7. The nonvolatile memory according to claim 1, wherein a first dielectric layer is respectively disposed between the plurality of charge storage layers and the plurality of gate structures. 8. The nonvolatile memory as claimed in claim 7, wherein the material of the plurality of first dielectric layers comprises silicon oxide. 9. The non-volatile memory according to claim 1, wherein a second dielectric layer is respectively disposed between the charge storage layers and the substrate. 10. The nonvolatile memory as claimed in claim 9, wherein the material of the plurality of second dielectric layers comprises silicon oxide. 11. The non-volatile memory of claim 6, wherein: Each first gate structure includes: a first gate dielectric layer disposed on the substrate; a first gate disposed on the first gate dielectric layer; and a top cover layer disposed on the first grid; and Each second gate structure includes: a second gate dielectric layer disposed on the substrate; and The second gate is disposed on the second gate dielectric layer. 12. The nonvolatile memory of claim 11, wherein materials of the first gate dielectric layer and the second gate dielectric layer comprise silicon oxide. 13. The nonvolatile memory as claimed in claim 11, wherein the material of the first gate and the second gate comprises doped polysilicon. 14. A method of manufacturing a non-volatile memory, comprising: provide the basis; forming a plurality of first gate structures on the substrate, with a gap between two adjacent first gate structures; forming a tunnel dielectric layer on the substrate; forming a plurality of charge storage layers on sidewalls of the plurality of first gate structures; Forming a plurality of second gate structures on the substrate, the plurality of second gate structures filling the gaps between the plurality of first gate structures, the plurality of charge storage layers, the plurality of second gate structures structure and the plurality of first gate structures constitute a row of memory cells; and Two doping regions are formed in the substrate on both sides of the row of memory cells. 15. The method of manufacturing a non-volatile memory as claimed in claim 14, wherein the step of forming the plurality of first gate structures on the substrate comprises: forming a first gate dielectric layer on the substrate; forming a first conductor layer on the first gate dielectric layer; forming a capping layer on the first conductor layer; and patterning the cap layer, the first conductor layer and the first gate dielectric layer. 16. The method of manufacturing a nonvolatile memory as claimed in claim 15, wherein a material of the first gate dielectric layer comprises silicon oxide. 17. The method of manufacturing a non-volatile memory according to claim 14, wherein the step of forming a plurality of charge storage layers on the sidewalls of the plurality of first gate structures comprises: forming a first dielectric layer and a charge storage material layer on the substrate; and Anisotropic etching is performed to remove part of the first dielectric layer and part of the charge storage material layer. 18. The method of manufacturing a nonvolatile memory as claimed in claim 17, wherein a material of the charge storage layer comprises silicon nitride. 19. The method of manufacturing a non-volatile memory according to claim 17, further comprising patterning the plurality of charge storage layers after the step of forming the plurality of charge storage layers on the sidewalls of the plurality of first gate structures , forming multiple charge storage blocks. 20. The method of manufacturing a nonvolatile memory as claimed in claim 19, wherein the material of the plurality of charge storage blocks comprises silicon nitride or doped polysilicon. 21. The method of manufacturing a non-volatile memory according to claim 14, wherein the step of forming a plurality of charge storage layers on the sidewalls of the plurality of first gate structures comprises: forming a first dielectric layer on the substrate; forming a charge storage material layer on the substrate; forming a sacrificial layer on the substrate; performing anisotropic etching to remove part of the sacrificial layer and form a plurality of spacers on the surface of the charge storage material layer; using the plurality of spacers as a mask, removing part of the charge storage material layer and part of the first dielectric layer to expose the substrate; and The plurality of spacers are removed. 22. The method of manufacturing a nonvolatile memory as claimed in claim 21, wherein the plurality of charge storage layers are L-shaped. 23. The method of manufacturing a nonvolatile memory as claimed in claim 21, wherein a material of the plurality of charge storage layers comprises silicon nitride. 24. The method of manufacturing a non-volatile memory according to claim 21, further comprising patterning the plurality of charge storage layers after the step of forming the plurality of charge storage layers on the sidewalls of the plurality of first gate structures , forming multiple charge storage blocks. 25. The method of manufacturing a non-volatile memory as claimed in claim 24, wherein the material of the plurality of charge storage blocks comprises silicon nitride or doped polysilicon. 26. The method of manufacturing a nonvolatile memory as claimed in claim 14, wherein a material of the tunneling dielectric layer comprises silicon oxide. 27. The method of manufacturing a nonvolatile memory as claimed in claim 14, wherein the step of forming the plurality of second gate structures on the substrate comprises: forming a second gate dielectric layer on the substrate; forming a second conductor layer on the second gate dielectric layer, the second conductor layer filling the gap; and Part of the second conductor layer is removed until the plurality of first gate structures are exposed. 28. The method of manufacturing a non-volatile memory as claimed in claim 14, wherein the method for removing part of the second conductor layer comprises a chemical mechanical polishing method. 29. The method of manufacturing a nonvolatile memory as claimed in claim 14, wherein a material of the second gate dielectric layer comprises silicon oxide. 30. The method of manufacturing a non-volatile memory according to claim 27, wherein the material of the first conductor layer and the second conductor layer comprises doped polysilicon. 31. An operation method of a non-volatile memory, which is suitable for a memory cell array, and the memory cell array includes: a plurality of memory cell rows, and each of the plurality of memory cell rows includes: a plurality of gate structures, arranged in series on the substrate; a plurality of charge storage layers are respectively arranged between the plurality of gate structures, wherein the plurality of charge storage layers are arranged in pairs; and the first source/drain region and the second source Electrode/drain regions are respectively arranged in the substrate on both sides of the memory cell row; a plurality of word lines are connected to the plurality of gate structures in the same column, and the method includes: When performing a programming operation, a first voltage is applied to a selected word line; a second voltage is applied to other unselected word lines; a third voltage is applied to the first source/drain region of the selected memory cell row ; applying a fourth voltage to the second source/drain region of the selected memory cell row; wherein the first voltage is greater than or equal to the threshold voltage of the plurality of gate structures, and the second voltage is greater than the first voltage, The fourth voltage is greater than the third voltage, so as to program the charge storage layer adjacent to the selected word line and on the side of the second source/drain region by using the source side injection effect. 32. The operation method of the non-volatile memory as claimed in claim 31, wherein the first voltage is about 1.5 volts, the second voltage is about 7 volts, the third voltage is about 0 volts, and the fourth voltage is about 2.5 volts. Volts or so. 33. The operation method of the non-volatile memory according to claim 31 , further comprising applying a fifth voltage to the plurality of word lines and applying a sixth voltage to the substrate when performing an erase operation, so that the data stored in the Electrons in the plurality of charge storage layers are guided into the substrate, wherein the voltage difference between the fifth voltage and the sixth voltage will induce FN tunneling effect. 34. The operating method of the non-volatile memory as claimed in claim 33, wherein the voltage difference is about -12 to -20 volts. 35. The operating method of the nonvolatile memory as claimed in claim 33, wherein the fifth voltage is 0 volts, and the sixth voltage is 12 volts. 36. The operation method of the non-volatile memory as claimed in claim 31, wherein when performing a read operation, the seventh voltage is applied to the selected word line; the eighth voltage is applied to other unselected word lines; applying a ninth voltage to the first source/drain region of the selected memory cell row; applying a tenth voltage to the second source/drain region of the selected memory cell row to read adjacent selected words element line, and the charge storage layer located at the side of the second source/drain region, wherein the ninth voltage is greater than the tenth voltage, the seventh voltage is greater than or equal to the threshold voltage of the plurality of gate structures, and is less than the The voltage difference between the ninth voltage and the tenth voltage, the eighth voltage is greater than the seventh voltage. 37. The operation method of the non-volatile memory as claimed in claim 36, wherein the seventh voltage is about 3.5 volts, the eighth voltage is about 7 volts, the ninth voltage is about 1.5 volts, and the tenth voltage is 0 Volts or so. 38. The method for operating a non-volatile memory according to claim 31 , wherein when performing a read operation, the eleventh voltage is applied to the selected word line; the twelfth voltage is applied to other unselected word lines; Applying a thirteenth voltage to the second source/drain region of the selected memory cell row; applying a 14th voltage to the first source/drain region of the selected memory cell row to read adjacent The selected word line, and the charge storage layer located on the side of the first source/drain region, wherein the thirteenth voltage is greater than the fourteenth voltage, and the eleventh voltage is greater than or equal to the plurality of gate structures The threshold voltage is less than the voltage difference between the thirteenth voltage and the fourteenth voltage, and the twelfth voltage is greater than the eleventh voltage. 39. The operating method of the nonvolatile memory according to claim 38, wherein the eleventh voltage is about 3.5 volts, the twelfth voltage is about 7 volts, the thirteenth voltage is about 1.5 volts, and the tenth voltage is about 7 volts. Four voltages are around 0 volts. 40. A method for operating a nonvolatile memory, suitable for a memory cell array, the memory cell array comprising: a plurality of memory cell rows, each of the plurality of memory cell rows comprising: a plurality of first gate structures disposed on On the substrate, there are gaps between two adjacent first gate structures; multiple second gate structures are arranged in the gaps between the multiple first gate structures; multiple charge storage layers, respectively disposed between the plurality of first gate structures and the plurality of second gate structures, wherein each of the plurality of charge storage layers includes a portion sandwiched between the first gate structure and the substrate and the first source/drain region and the second source/drain region are respectively arranged in the substrate on both sides of the memory cell row; a plurality of word lines are connected to the plurality of first in the same column A gate structure; a plurality of selection gate lines connecting the plurality of second gate structures in the same column, the method comprising: When performing a programming operation, a first voltage is applied to the selected word line; a second voltage is applied to other unselected word lines and the plurality of selection gate lines; applying a third voltage to the drain region; applying a fourth voltage to the second source/drain region of the selected memory cell row; wherein the first voltage is greater than or equal to the threshold voltage of the plurality of first gate structures, the The second voltage is greater than the first voltage, and the fourth voltage is greater than the third voltage, so as to use the source side injection effect to program the charge storage adjacent to the selected word line and located at the second source/drain region side. layer. 41. The operation method of the nonvolatile memory as claimed in claim 40, wherein the first voltage is about 1.5 volts, the second voltage is about 9 volts, the third voltage is about 0 volts, and the fourth voltage is 3.5 Volts or so. 42. The operation method of the non-volatile memory as claimed in claim 40, further comprising applying a fifth voltage to the selected word line when performing the programming operation; other unselected word lines and the plurality of selection gate lines applying a sixth voltage; applying a seventh voltage to the second source/drain region of the selected memory cell row; applying an eighth voltage to the first source/drain region of the selected memory cell row; wherein the The fifth voltage is greater than or equal to the threshold voltage of the plurality of first gate structures, the sixth voltage is greater than the fifth voltage, and the eighth voltage is greater than the seventh voltage, so as to use the source side injection effect to program the adjacent selected word element line, and the charge storage layer located on the side of the first source/drain region. 43. The operation method of the nonvolatile memory as claimed in claim 42, wherein the fifth voltage is about 1.5 volts, the sixth voltage is about 9 volts, the seventh voltage is about 0 volts, and the eighth voltage is 3.5 volts. Volts or so. 44. The operation method of the non-volatile memory according to claim 40, further comprising applying a ninth voltage to the plurality of word lines and the plurality of selection gate lines, and applying a ninth voltage to the substrate when performing an erasing operation. Ten voltages are used to guide the electrons stored in the plurality of charge storage layers into the substrate, wherein the voltage difference between the ninth voltage and the tenth voltage will induce FN tunneling effect. 45. The operating method of the non-volatile memory as claimed in claim 44, wherein the voltage difference is about -12 to -20 volts. 46. The operating method of the nonvolatile memory as claimed in claim 44, wherein the ninth voltage is 0 volts, and the tenth voltage is 12 volts. 47. The operation method of the non-volatile memory as claimed in claim 40, wherein when performing a read operation, an eleventh voltage is applied to the selected word line; applying a twelfth voltage to the electrode line; applying a thirteenth voltage to the first source/drain region of the selected memory cell row; applying a thirteenth voltage to the second source/drain region of the selected memory cell row Fourteen voltages are used to read the charge storage layer adjacent to the selected word line and on the side of the second source/drain region, wherein the thirteenth voltage is greater than the fourteenth voltage, and the eleventh voltage The twelfth voltage is greater than or equal to the threshold voltage of the plurality of gate structures when the charge storage layer is not programmed and is smaller than the threshold voltage of the plurality of gate structures after the charge storage layer is programmed. 48. The operating method of the nonvolatile memory according to claim 47, wherein the eleventh voltage is about 2.5 volts, the twelfth voltage is about 6 volts, the thirteenth voltage is about 1.5 volts, and the tenth voltage is about 6 volts. Four voltages are around 0 volts. 49. The operation method of the non-volatile memory as claimed in claim 40, wherein when performing a read operation, a fifteenth voltage is applied to the selected word line; Applying a sixteenth voltage to the electrode line; applying a seventeenth voltage to the second source/drain region of the selected memory cell row; applying a first voltage to the first source/drain region of the selected memory cell row Eighteen voltages, to read the charge storage layer adjacent to the selected word line and on the side of the first source/drain region, wherein the seventeenth voltage is greater than the eighteenth voltage, and the fifteenth voltage The sixteenth voltage is greater than or equal to the threshold voltage of the plurality of gate structures when the charge storage layer is not programmed and is smaller than the threshold voltage of the plurality of gate structures after the charge storage layer is programmed. 50. The operating method of the non-volatile memory according to claim 49, wherein the fifteenth voltage is about 2.5 volts, the sixteenth voltage is about 6 volts, the seventeenth voltage is about 1.5 volts, and the tenth voltage is about 6 volts. The eight voltage is around 0 volts.

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