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CN101023237B - Memory device having data retention latch and method of operating the same - Google Patents

Memory device having data retention latch and method of operating the same Download PDF

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Publication number
CN101023237B
CN101023237B CN2005800189027A CN200580018902A CN101023237B CN 101023237 B CN101023237 B CN 101023237B CN 2005800189027 A CN2005800189027 A CN 2005800189027A CN 200580018902 A CN200580018902 A CN 200580018902A CN 101023237 B CN101023237 B CN 101023237B
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China
Prior art keywords
bit line
output
coupled
write
value
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CN101023237A (en
Inventor
拉文德拉拉·拉玛拉朱
乔治·P.·霍克斯特拉
普拉山特·U.·肯卡莱
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NXP USA Inc
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Freescale Semiconductor Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)

Abstract

A memory device includes a plurality of pairs of complementary bit lines (200, 202) and a plurality of latch circuits. Each of the plurality of pairs of complementary bit lines is coupled to a column of memory cells (31, 37). Each latch circuit has an input coupled to a data line and first and second outputs providing complementary latched values dependent on the value of the data line. For each latch of the plurality of latches, a first output is coupled to a first bit line of a pair of bit lines of the plurality of pairs of bit lines to continuously determine a value of the first bit line through the first output during operation of the memory device, and a second output is coupled to a second bit line of the pair of bit lines to continuously determine a value of the second bit line through the second output during operation of the memory device.

Description

Memory devices and method of operating thereof with data hold latch
Invention field
The present invention relates to integrated circuit, and more specifically to memory devices.
Background technology
In multiport storage device, memory read operation and memory write operation seriously are subjected to carrying out the influence of the required time quantum of this operation.During write operation, input data (assertion) time of asserting can be depended on the decoding delay relevant with the attribute of memory devices and change.For example, owing to when the time of asserting is inadequate, misdata is written to memory, therefore with to the relevant uncertainty of the dependence of input data can cause processor fault.
Therefore, there are needs to the reservoir designs that is used to improve memory performance.
Summary of the invention
According to a first aspect of the invention, provide a kind of memory devices, comprising: first write bit line; Second write bit line, described second write bit line are the paratope lines of described first write bit line; One row memory cell, this row memory cell and described first write bit line and described second write bit line are coupled; Latch circuit, the output that this latch circuit has the input that is coupled with data wire and is used for providing according to the value of described data wire latched value, this output and described first write bit line are coupled, so that export the value of determining described first write bit line continuously in memory devices operating period by this; First sense bit line, a described row memory cell is coupled to described first sense bit line; Second reading bit line, described second reading bit line are the paratope lines of described first sense bit line, and a described row memory cell is coupled to described second reading bit line.
According to a second aspect of the invention, provide a kind of memory devices, comprising: bit line; One row memory cell, this row memory cell and described bit line are coupled; Latch circuit, the latch output that this latch circuit has the input that is coupled with data wire and is used for providing according to the value of described data wire latched value, the output of this latch is coupled with described bit line, so that export the value of determining described bit line continuously by this latch in memory devices operating period; Sense bit line, a described row memory cell is coupled to described sense bit line; Wherein, described bit line is a write bit line; Wherein, described latch comprises the phase inverter of pair of cross coupling; Wherein, described latch is exported the input of first phase inverter in the phase inverter that is coupled to described pair of cross coupling, and the output of second phase inverter in the phase inverter of described pair of cross coupling; Wherein, described latch comprises the 3rd phase inverter, the output of described the 3rd phase inverter is connected to the output of described latch, and the input of described the 3rd phase inverter is connected to the output of described second phase inverter in the phase inverter of the input of described first phase inverter in the phase inverter of described pair of cross coupling and the coupling of described pair of cross.
According to a third aspect of the invention we, provide a kind of memory devices, comprising: bit line; One row memory cell, this row memory cell and described bit line are coupled; Latch circuit, the output that this latch circuit has the input that is coupled with data wire and is used for providing according to the value of described data wire latched value, this output and described bit line are coupled, so that export the value of determining described bit line continuously in memory devices operating period by this; Wherein said latch comprises second input that is used for the receive clock signal, the output of wherein said latch by the state variation of described clock signal on the determined time according to the value of described data wire and the change value; Word line, the memory cell in a described word line and the described row memory cell is coupled, so that write signal is sent to this memory cell; Word line produces circuit, this word line produces circuit and has the output that is coupled with word line, so that described write signal to be provided, described word line produces circuit and comprises the input that is used for the receive clock signal, wherein, described write signal state variation change state on the determined time of producing clock signal received in the input of circuit at described word line; Wherein, generation produces the received clock signal of circuit and received clock signal in second input of latch by word line from common clock signal.
According to a forth aspect of the invention, provide a kind of being used for that memory devices is carried out method of operating, comprise: memory devices is operated, comprising the memory cell in the row memory cell is carried out via repeatedly reading of sense bit line and complementary sense bit line and repeatedly writing via write bit line and complementary write bit line, wherein said sense bit line and described complementary sense bit line are coupled to a described row memory cell, and described write bit line and described complementary write bit line are coupled to a described row memory cell; During described operating procedure, utilize the output of first latch and second latch to export respectively the value of described write bit line and described complementary write bit line is carried out continuous control.
According to a fifth aspect of the invention, provide a kind of memory devices, comprising: many to paratope line, wherein said many each in the paratope line are to being coupled with a row memory cell; A plurality of latch circuits, each latch circuit has the input that is coupled with data wire, and first output and second output that are used for providing according to the value of data wire the latched value of complementation; Wherein, for each latch in described a plurality of latch circuits, first output is coupled with described many first bit lines to a pair of paratope line in the paratope line, so that the value of coming to determine continuously first bit line by described first output in memory devices operating period, and second output manyly is coupled to this second bit line to paratope line in the paratope line with described, so that the value of coming to determine continuously second bit line by described second output in memory devices operating period; Wherein, described latch comprises second input that is used for the receive clock signal, the output of wherein said latch by the state variation of described clock signal on the determined time according to the value of described data wire and the change value.
According to a sixth aspect of the invention, provide a kind of memory devices, comprising: first write bit line; Second write bit line, described second write bit line are the paratope lines of described first write bit line; One row memory cell, this row memory cell and described first write bit line and described second write bit line are coupled; And latch circuit, this latch circuit has the input that is coupled with data wire, first output of first latched value is provided according to the value of described data wire, second output of second latched value is provided according to the value of described data wire, described first output is coupled with described first write bit line, so that the value of described first write bit line changed when the value that and if only if in described first output of memory devices operating period changed, described second output is coupled with described second write bit line, so as the value that and if only if in memory devices described second output of operating period when changing the value of described second write bit line change; Sense bit line, a described row memory cell and the coupling of described sense bit line.
Description of drawings
The present invention will be described by way of example, and the present invention is not limited to accompanying drawing, and identical in the accompanying drawings reference marker is represented similar element, and wherein:
Fig. 1 has illustrated the block diagram of integrated circuit according to an embodiment of the invention;
Fig. 2 has illustrated memory according to an embodiment of the invention;
Fig. 3 has illustrated column array circuits according to an embodiment of the invention; And
Fig. 4 has illustrated the sequential chart that is used to represent various signals according to an embodiment of the invention.
It will be appreciated by persons skilled in the art that for simple and clear for the purpose of, the element in the accompanying drawing is illustrated, and these elements are not necessarily drawn in proportion.For example, for other elements, some size of component in the accompanying drawing have been amplified, to help to improve understanding to the embodiment of the invention.
The specific embodiment
In one embodiment, memory devices comprises bit line, a row memory cell and a latch circuit.The memory cell and the bit line of these row are coupled.Latch circuit has the input that is coupled with data wire, and the output that is used for providing according to the value of data wire latched value.This output and bit line are coupled, so that come to determine continuously the value of bit line by described output in memory devices operating period.
Embodiment relates to a kind of being used for memory devices is carried out method of operating.Execution is repeatedly read and is repeatedly write to the memory cell in the row memory cell.The value of the bit line that is coupled with this row memory cell is exported continuously by latch in memory devices operating period and is controlled.In one embodiment, the value of latch output can changed in response to the value of latch input on the determined time from the state variation of first state to the second state by clock signal.In one embodiment, can write values in the memory cell in this row memory cell, wherein this writes and for example comprises the state of bit line is changed.In one embodiment, can write values in the memory cell in this row memory cell, wherein this writes and for example comprises and make the state of writing lambda line become write state from non-write state.
In one embodiment, memory devices comprises bit line, a row memory cell and a latch circuit.This row memory cell and bit line are coupled.Latch circuit has the input that is coupled with data wire, and the output that is used for providing according to the value of data wire latched value.This output links to each other with bit line.
In one embodiment, memory devices comprises many to paratope line and a plurality of latch circuit.Many each to paratope line are to being coupled with a row memory cell.Each latch circuit has the input that is coupled with data wire, and first output and second output that are used for providing according to the value of data wire complementary latched value.For each latch of a plurality of latch circuits, first bit line of the pair of bit lines in first output and the many pairs of bit line is coupled, so that the value of coming to determine continuously first bit line by first output in memory devices operating period, and second output is coupled with second bit line of this pairs of bit line, so that the value of coming to determine continuously second bit line by second output in memory devices operating period.
In one embodiment, memory devices comprises bit line, a row memory cell and a latch circuit.This row memory cell and bit line are coupled.Latch circuit has the input that is coupled with data wire, and the output that is used for providing according to the value of data wire latched value.This output and bit line are coupled, so as the value that and if only if in memory devices this output of operating period when changing the value of bit line just change.
Fig. 1 has illustrated integrated circuit 2 according to an embodiment of the invention.Integrated circuit 2 comprises core 3 and Bus Interface Unit (BIU) 6.Core 3 comprises clock circuit 4, performance element 5, memory control unit 7 and memory 10.In one embodiment, core 3 for example can be a processor core, and memory 10 is characterised in that for example multiport register file.
In one embodiment, during the normal running of integrated circuit 2, carry out write access or read access according to the 8 pairs of memories of control signal 10 that offer memory control unit 7 from performance element 5.Control signal 8 can be used to start memory read operation or memory write operation.Performance element 5 for example can be that CPU (CPU) or be used for is sent control signal 8 data stored into memory 10 or to read the digital signal processing unit of the data in the memory 10.Clock circuit 4 offers memory control unit 7, performance element 5 and memory 10 with following clock signal 29 (CLK 29), and wherein said clock signal 29 is used as chronograph mechanism in one embodiment to determine when the data that write data into memory 10 or read memory 10.Memory control unit 7 receives clock signal 29 and the control signal 8 from performance element 5, and is request read operation or request write operation according to performance element 5, asserts and writes enable signal 60 (WR EN 60) or read enable signal 14 (READ EN14).
During read operation, from memory control unit 7 RD ADDRESS 15 and READ EN 14 are offered memory 10. memories 10 reception READ EN 14, and enable memory address locations by RD ADDRESS 15 appointments.Read by the data the specified memory address locations of RD ADDRESS 15 from memory 10, and it is offered performance element 5 as DATA-OUT (data output) 212 by data wire 214.
During write operation, WR ADDRESS 75 and WREN 60 are offered memory 10 from memory control unit 7.Memory 10 receives WR EN 60, and enables by the memory address locations in the memory 10 of WRADDRESS 75 appointments for use in write operation.To offer memory 10 from the data (DATA-IN (data input) 211) of performance element 5 by data wire 213, and be written into memory address locations by the specified memory 10 of WR ADDRESS 75.In other embodiments, integrated circuit 2 can have other structures.
Fig. 2 has illustrated memory 10 according to an embodiment of the invention.Memory 10 comprises to be read row decoder 13, read word line driver 38, write word line drivers 39, write bitline latch 76, row control logic 25, column array circuits 11, column array circuits 12, phase inverter 70, writes row decoder 62 and column circuits 77.Read word line driver 38 comprises read word line driver 16, read word line driver 19 and read word line driver 22.Write 39 comprises write 58, write 61 and write 64.Column array circuits 11 comprises write bitline latch 28, bit location (memory cell) 31, bit location 34, bit location 37 and column circuits 40.Column array circuits 12 comprises write bitline latch 43, bit location 46, bit location 49, bit location 52 and column circuits 55.For convenience of explanation, bit location 46, bit location 49, bit location 52, bit location 31, bit location 34 and bit location 37 can be called bit cell array 69, and can and write row decoder 62 with write 39 and be called word line and produce circuit.In an illustrated embodiment, bit location 31 is arranged in the row identical with bit location 46.
In one embodiment, during read operation, the row decoder 13 read of memory 10 receives from the reading enable signal 14 and read address 15 of memory control unit 7 (Fig. 1), and receives the clock signal 29 from clock circuit 4 (Fig. 1).Read 13 pairs of row decoders and read address 15 and decode, and will enable that delegation's bit location that is used to carry out read access in definite bit cell array 69.Bit cell array 69 comprises delegation or multirow bit location, perhaps row or a multiple row bit location.Read row decoder 13 will exercise can signal 18 output in the read word line driver 38, with corresponding at least one read word line driver 38 of row address of being decoded.Corresponding this read word line driver of the row address with being decoded in the read word line driver 38 is asserted the read word line signal that offers selected delegation or multirow bit location.In the illustrated embodiment, read word line driver 16, read word line driver 19 or read word line driver 22 are asserted any one among read word line signal RWL0, RWL1, the RWLN respectively.The bit location of selected row offers column circuits 40 with read bitline signal (RBL0 and RBLB0) as input, and read bitline signal (RBL1 and RBLB1) is offered column circuits 55 as input.For the situation when bit cell array 69 has the multirow bit location, can being offered column circuits 40 and column circuits 55 as input before, read bitline signal RBL0 and RBLB0 and read bitline signal RBL1 and RBLB1 provide it to additional delegation or multirow bit location.Similarly, for the situation when bit cell array 69 has the multiple row bit location, read word line signal RWL0, RWL1 and RWLN are offered additional row or a multiple row bit location.
Column circuits 40 and column circuits 55 receive read bitline signal RBL0 and RBLB0 and read bitline signal RBL1 and RBLB1 respectively.Column circuits 40 uses read bitline signal RBL0 and RBLB0 to produce output data (DATA-OUT 0 and DATA-OUT B0), opens and column circuits 55 uses read bitline signal to produce output data (DATA-OUT 1 and DATA-OUT B1).After this, output data can be offered all performance element 5 such performance elements as shown in Figure 1 so that further handle.Alternative embodiment that it should be noted that memory 10 can comprise single column array circuits 11 or a plurality of column array circuits, but is not limited to described in Fig. 2 those.
In one embodiment, during write operation, write row decoder 62 receptions and write enable signal 60, clock signal 29, and write address 75. is write 62 pairs of write addresses 75 of row decoder and is decoded, and the bit location which is determined will be enabled and be used for carrying out write access. write row decoder 62 and will exercise energy signal 68 and output to write 39, assert the write word line signal that offers selected delegation or multirow bit location with corresponding this write of the row address with being decoded in corresponding at least one write 39. write 39 of the row address of being decoded. in the illustrated embodiment, write 58, write 61, and write 64 is asserted write word line signal WWL0 respectively by the write word line that is used to make write 39 and bit cell array 69 to be coupled, WWL1, among the WWLN any one. in one embodiment, by the state variation of clock signal 29 on the determined time, write word line signal can for example become write state from non-write state. and the input data (DATA-IN 0 and DATA-IN 1) that will for example be provided from performance element 5 (not shown) are sent to write bitline latch 76 (write bitline latch 28 and write bitline latch 43).Write bitline latch 76 receives these input data and passes through phase inverter 70 and anti-phase inversion clock signal 29 (CLKB 30).Write bitline latch 76 is used CLKB 30 will import data and is driven into as complementary signal WBLB0, the WBLB of write bitline signal WBL0, WBL1 and this write bitline signal and is used to write bit line that write bitline latch 76 and bit cell array 69 are coupled.After this, this write bitline signal is written on the bit location of the selected row in the bit cell array 69.For the situation when bit cell array 69 has the multirow bit location, write bitline signal WBL0 and WBLB0 and write bitline signal WBL1 and WBLB1 are offered additional delegation or multirow bit location.Similarly, for the situation when bit cell array 69 has the multiple row bit location, write word line signal WWL0, WWL1 and WWLN are offered additional row or a multiple row bit location.In other embodiments, memory 10 can have other structures.
Fig. 3 has illustrated an embodiment of column array circuits 11.As described, column array circuits 11 comprises write bitline latch 28, bit location 31, bit location 37 and column circuits 40.Write bitline latch 28 is coupled with bit location 31 and bit location 37 by write bit line 200 and write bit line 202.In one embodiment, write bit line 202 is paratope lines of write bit line 200.Bit location 31 and bit location 37 are coupled with column circuits 40 by sense bit line 204 and sense bit line 206.In alternative embodiment, additional bit location can be added on the column array circuits 11.The not shown bit location 34 of Fig. 3.
During write operation, the write bitline latch of column array circuits 11 28 receives from the clock bar signal (clockbar signal) 30 (CLKB 30) of phase inverter 70 (Fig. 2) and from the input data (DATA-IN 0) of performance element 5 (Fig. 1).Or non-(NOR) 107 couples of DATA-IN 0 of door and clock bar signal 30 carry out NOR-operation, and its output is offered nmos pass transistor 119.The inversion signal of 103 pairs of clock bar signals of nor gate 30 and input data DATA-IN 0 carries out NOR-operation, and its output is offered nmos pass transistor 116.
Usually, DATA-IN 0 and clock bar signal 30 can have the value of asserting or cancellation and assert the scope of (deassertion) value.In one embodiment, when clock bar signal 30 when being high, the output of nor gate 107 and nor gate 103 are output as low.Consequently, nmos pass transistor 119 and nmos pass transistor 116 disconnects, and the latch 180 that includes the phase inverter 110 that is coupling in phase inverter 113 two ends keeps before being written to the data value (if any) in the latch 180 on one's own initiative.
In one embodiment, when clock bar signal 30 be low and DATA=IN 0 when high, it is low that nor gate 107 is output as, and nor gate 103 is output as height.Consequently, nmos pass transistor 119 disconnects, nmos pass transistor 116 conductings, and node 114 is dragged down, and phase inverter 110 is output as height.The output of phase inverter 110 is undertaken anti-phase by phase inverter 113 and phase inverter 124.Phase inverter 113 makes the output of phase inverter 110 anti-phase, and its output is offered phase inverter 127.Be switched to that the phase inverter 127 as write bitline signal WBL0 is output as height on the write bit line 200.Be switched to that the phase inverter 124 as write bit line bar signal (bar signal) WBLB0 is output as low on the write bit line 202.Write bitline signal WBL0 and write bit line bar signal WBLB0 are offered bit location 31.
In one embodiment, when clock bar signal 30 be low and DATA-IN 0 when low, nor gate 107 is output as height, and nor gate 103 is output as low.Consequently, nmos pass transistor 119 conductings, and nmos pass transistor 116 disconnects.Because nmos pass transistor 119 conductings, so node 115 dragged down, and phase inverter 113 is output as height.Be switched to that the phase inverter 124 as write bit line bar signal WBLB0 is output as height on the write bit line 202, and be switched to that the phase inverter 127 as write bit line bar signal WBL0 is output as low on the write bit line 204.Therefore, the value of write bitline signal WBL0 in the output of write bitline latch 28 and write bit line bar signal WBLB0 is by the state variation of clock bar signal 30 on the determined time, according to the value of the DATA-IN on the input data line 0 and the change value.Similarly, the value of the write bitline signal WBL0 of write bit line 200 and write bit line 202 and write bit line bar signal WBLB0 can changed in response to the value DATA-IN on the input data line 0 on the determined time by the state variation of clock signal.Write bitline signal WBL0 and write bit line bar signal WBLB0 are offered bit location 31.
Bit location 31 receives write bitline signal WBL0 from the output of phase inverter 127 at the current terminal of nmos pass transistor 133, and receives write bit line bar signal WBLB0 from the output of phase inverter 124 at the current terminal of nmos pass transistor 136.As the write word line signal WWL0 of the control end that offers nmos pass transistor 133 and nmos pass transistor 136 when being high, nmos pass transistor 133 and nmos pass transistor 136 conductings.Move node 122 to be switched on the write bit line 200 that value, and move node 123 to be switched on the write bit line 202 that value.Therefore, as WWL0 when being high, bit location 31 will store in the column array circuits 11 as the input data DATA-IN 0 that input provides.When WWL0 when low, nmos pass transistor 133 and nmos pass transistor 136 disconnect, and utilize phase inverter 121 and phase inverter 130 to store the data value that writes from write bit line 200 and write bit line 202.
During read operation, as the read word line signal RWL0 on the readout word line 208 when being high, nmos pass transistor 139 and nmos pass transistor 145 conductings.The inverse value of utilizing nmos pass transistor 142 and nmos pass transistor 148 will be stored in the inverse value of the value on the node 122 respectively and being stored in the value on the node 123 is sent to sense bit line 204 and is sent to sense bit line 206 as read bitline signal RBL0 as sense bit line bar signal RBLB0.When the precharging signal (PCH) that offers column circuits 40 as input when high, PMOS transistor 151 and PMOS transistor 154 disconnect, and the value of the read bitline signal RBLB0 on the sense bit line 204 is offered phase inverter 157, and the value of the read bitline signal RBL0 on the sense bit line 206 is offered phase inverter 163.The output of phase inverter 157 is offered the performance element (not shown) as output data DATA-OUT0, and offer the control end of PMOS transistor 160.Similarly, the output of phase inverter 163 is offered the performance element (not shown) as output data (DATA-OUT B0), and offer the control end of PMOS transistor 166.According to the value of read bitline signal RBL0 and read bitline signal RBLB0, PMOS transistor 160 or 166 disconnections of PMOS transistor.In other embodiments, write bitline latch 28, bit location 31, bit location 37 and/or column circuits 40 can have other structures.In an illustrated embodiment, DATA-IN 0 signal is single-ended (single-ended) signal, but in other embodiments, it can be such as the so other forms of signal of differential signal.
The sequential chart of the various signals of the read-write that Fig. 4 has illustrated according to an embodiment of the invention, expression is used to realize bit cell 31.As described in one embodiment, during read operation, when reading enable signal 14 and clock signal 29 when high, read word line signal RWL0 be a height.Can for example since read row decoder 13 and read word line driver 38 caused delays after assert out read word line signal RWL0 for the height.In case read word line signal RWL0 is high, so read bitline signal RBL0 be low and sense bit line bar signal RBLB0 for high, perhaps read bitline signal RBL0 is that height and sense bit line bar signal RBLB0 are low.When sense bit line RBL0 or sense bit line bar signal RBLB0 when low, DATA-OUT 0 or DATA-OUT B0 be height.When clock signal 29 when low, read word line signal RWL0 is low, read bitline signal RBL0 and sense bit line bar signal RBLB0 be height, and DATA-OUT0 and DATA-OUT B0 are low.
As illustrated in fig. 4, when DATA-IN 0 and clock signal 29 were high (clock bar signal 30 is for low), write bitline signal WBL0 be a height, and write bit line bar signal WBLB0 is low.During write operation, when writing enable signal 60 and clock signal 29 when high, write word line signal WWL0 be a height.Can for example since write row decoder 62 and write 39 caused delays after assert out write word line signal WWL0 for the height.When clock signal 29 when low, write word line signal WWL0 is low.
Can learn that from the sequential chart of Fig. 4 decoding delay is with relevant to being asserted to asserting of write word line signal WWL0 of clock signal 29.Latch delay is with relevant to being asserted to asserting of write bitline signal WBL0 of clock signal 29.In one embodiment, during write operation, write bitline signal WBL0 remains high value, till write word line signal WWL0 is low.Similarly, write bit line bar signal WBLB0 remains low value, till write word line signal WWL0 is low.DATA-IN 0 remains height, till clock signal 29 is low.As described, DATA-IN 0 asserts that the time is irrelevant with the decoding delay relevant with write word line signal WWL0.
In above-mentioned manual, invention has been described with reference to specific embodiment.Yet, it will be appreciated by one skilled in the art that under the situation of the scope of the present invention that does not break away from appended claims to be set forth and can make various modifications and variations.Therefore, think that manual and accompanying drawing are illustrative and not restrictive, and all this modifications comprise within the scope of the present invention all.
With regard to specific embodiment, benefit, other advantages and the scheme of dealing with problems are described.Yet, these benefits, advantage, the scheme of dealing with problems and may cause and any benefit, advantage or solution occur or make its any element that becomes outstanding more should not be considered to critical, necessary or necessary feature or the element that any claim or all authority require.

Claims (10)

1.一种存储器设备，包括：1. A memory device comprising: 第一写位线；first write bit line; 第二写位线，所述第二写位线是所述第一写位线的互补位线；a second write bit line, the second write bit line being the complementary bit line of the first write bit line; 一列存储器单元，该一列存储器单元与所述第一写位线和所述第二写位线相耦合；a column of memory cells coupled to the first write bit line and the second write bit line; 锁存器电路，该锁存器电路具有与数据线相耦合的输入以及用于根据所述数据线的值来提供锁存值的输出，该输出与所述第一写位线相耦合，以便在存储器设备操作期间通过该输出来连续地确定所述第一写位线的值；a latch circuit having an input coupled to a data line and an output for providing a latched value based on the value of said data line, the output being coupled to said first write bit line so that continuously determining the value of the first write bit line from the output during operation of the memory device; 第一读位线，所述一列存储器单元耦合到所述第一读位线；a first read bit line to which the column of memory cells is coupled; 第二读位线，所述第二读位线是所述第一读位线的互补位线，所述一列存储器单元耦合到所述第二读位线。A second read bit line, the second read bit line being the complement of the first read bit line, the column of memory cells coupled to the second read bit line. 2.一种存储器设备，包括：2. A memory device comprising: 位线；bit line; 一列存储器单元，该一列存储器单元与所述位线相耦合；a column of memory cells coupled to the bit line; 锁存器电路，该锁存器电路具有与数据线相耦合的输入以及用于根据所述数据线的值来提供锁存值的锁存器输出，该锁存器输出与所述位线相耦合，以便在存储器设备操作期间通过该锁存器输出来连续地确定所述位线的值；a latch circuit having an input coupled to a data line and a latch output for providing a latch value based on the value of the data line, the latch output being in phase with the bit line coupled so that the value of the bit line is continuously determined by the latch output during operation of the memory device; 读位线，所述一列存储器单元耦合到所述读位线；a read bit line to which the column of memory cells is coupled; 其中，所述位线是写位线；Wherein, the bit line is a write bit line; 其中，所述锁存器包括一对交叉耦合的反相器；Wherein, the latch includes a pair of cross-coupled inverters; 其中，所述锁存器输出耦合到所述一对交叉耦合的反相器中的第一反相器的输入，以及所述一对交叉耦合的反相器中的第二反相器的输出；wherein the latch output is coupled to an input of a first inverter of the pair of cross-coupled inverters, and an output of a second inverter of the pair of cross-coupled inverters ; 其中，所述锁存器包括第三反相器，所述第三反相器的输出连接到所述锁存器的输出，并且所述第三反相器的输入连接到所述一对交叉耦合的反相器中的所述第一反相器的输入和所述一对交叉耦合的反相器中的所述第二反相器的输出。Wherein, the latch includes a third inverter, the output of the third inverter is connected to the output of the latch, and the input of the third inverter is connected to the pair of cross The input of the first inverter of the coupled inverters and the output of the second inverter of the pair of cross-coupled inverters. 3.一种存储器设备，包括：3. A memory device comprising: 位线；bit line; 一列存储器单元，该一列存储器单元与所述位线相耦合；a column of memory cells coupled to the bit line; 锁存器电路，该锁存器电路具有与数据线相耦合的输入以及用于根据所述数据线的值来提供锁存值的输出，该输出与所述位线相耦合，以便在存储器设备操作期间通过该输出来连续地确定所述位线的值；a latch circuit having an input coupled to a data line and an output for providing a latched value based on the value of the data line, the output coupled to the bit line for use in the memory device The value of the bit line is continuously determined by the output during operation; 其中所述锁存器包括用于接收时钟信号的第二输入，其中所述锁存器的输出在由所述时钟信号的状态变化所确定的时间上根据所述数据线的值而改变值；wherein the latch includes a second input for receiving a clock signal, wherein the output of the latch changes value in accordance with the value of the data line at times determined by changes in state of the clock signal; 字线，所述字线与所述一列存储器单元中的存储器单元相耦合，以便将写信号传送到该存储器单元；a word line coupled to a memory cell in the column of memory cells for delivering a write signal to the memory cell; 字线产生电路，该字线产生电路具有与字线相耦合的输出，以提供所述写信号，所述字线产生电路包括用于接收时钟信号的输入，其中，所述写信号在所述字线产生电路的输入上所接收到的时钟信号的状态变化所确定的时间上改变状态；a word line generation circuit having an output coupled to a word line to provide said write signal, said word line generation circuit including an input for receiving a clock signal, wherein said write signal is changing state in time determined by a state change of a clock signal received on an input of the word line generating circuit; 其中，从公共时钟信号中产生由字线产生电路所接收到的时钟信号以及在锁存器的第二输入上所接收到的时钟信号。Therein, the clock signal received by the word line generation circuit and the clock signal received at the second input of the latch are generated from the common clock signal. 4.根据权利要求3的存储器设备，其中，所述位线是写位线，所述存储器设备进一步包括：4. The memory device of claim 3, wherein the bit line is a write bit line, the memory device further comprising: 读位线，所述一列存储器单元与该读位线相耦合。A read bit line to which the column of memory cells is coupled. 5.一种用于对存储器设备进行操作的方法，包括：5. A method for operating on a memory device, comprising: 对存储器设备进行操作，其中包括对一列存储器单元中的存储器单元执行经由读位线和互补读位线的多次读取以及经由写位线和互补写位线的多次写入，其中所述读位线和所述互补读位线耦合到所述一列存储器单元，所述写位线和所述互补写位线耦合到所述一列存储器单元；Operating a memory device comprising performing multiple reads via a read bit line and a complementary read bit line and multiple writes via a write bit line and a complementary write bit line to memory cells in a column of memory cells, wherein the a read bit line and the complementary read bit line coupled to the column of memory cells, the write bit line and the complementary write bit line coupled to the column of memory cells; 在所述操作步骤期间，分别利用第一锁存器输出和第二锁存器输出来对所述写位线和所述互补写位线的值进行连续控制。During said operating step, the values of said write bit line and said complementary write bit line are continuously controlled by means of a first latch output and a second latch output, respectively. 6.根据权利要求5的方法，进一步包括：6. The method according to claim 5, further comprising: 将值写入到所述一列存储器单元中的存储器单元中，其中该写入步骤包括改变所述写位线的状态和改变所述互补写位线的状态。Writing a value to a memory cell in the column of memory cells, wherein the writing step includes changing the state of the write bit line and changing the state of the complementary write bit line. 7.根据权利要求6的方法，其中：7. The method according to claim 6, wherein: 该写入步骤还包括在时钟信号从第一状态至第二状态的状态变化所确定的时间上，使写入线的状态从非写入状态变为写入状态。The writing step also includes changing the state of the write line from a non-writing state to a writing state at a time determined by a state change of the clock signal from the first state to the second state. 8.根据权利要求6的方法，其中，所述写入步骤包括：使所述写位线的状态从第一状态变为第二状态，其中该方法进一步包括：8. The method of claim 6, wherein the writing step comprises: changing the state of the write bit line from a first state to a second state, wherein the method further comprises: 在所述写入步骤之后将另一值写入到所述一列存储器单元中的存储器单元中，其中，写入另一值的步骤包括改变所述写位线的状态，其中在所述写入步骤中改变状态的步骤与写入另一值的步骤之间不执行对所述一列存储器单元中的存储器单元的其他写入；After the writing step, another value is written into the memory cells in the column of memory cells, wherein the step of writing another value includes changing the state of the write bit line, wherein after the writing No other writes to memory cells in the column of memory cells are performed between the step of changing the state of the steps and the step of writing another value; 其中，在从所述写入步骤中改变状态至所述写入另一值的步骤中改变状态的时间内，所述写位线保持在第二状态。Wherein, the write bit line remains in the second state during the time from changing state in the step of writing to changing state in the step of writing another value. 9.一种存储器设备，包括：9. A memory device comprising: 多对互补位线，其中所述多对互补位线中的每一对与一列存储器单元相耦合；a plurality of pairs of complementary bit lines, wherein each of the plurality of pairs of complementary bit lines is coupled to a column of memory cells; 多个锁存器电路，每个锁存器电路具有与数据线相耦合的输入，以及用于根据数据线的值来提供互补的锁存值的第一输出和第二输出；a plurality of latch circuits, each latch circuit having an input coupled to a data line, and a first output and a second output for providing a complementary latch value based on the value of the data line; 其中，对于所述多个锁存器电路中的每个锁存器而言，第一输出与所述多对互补位线中的一对互补位线的第一位线相耦合，以便在存储器设备操作期间通过所述第一输出来连续地确定第一位线的值，并且第二输出与所述多对互补位线中的该对互补位线的第二位线相耦合，以便在存储器设备操作期间通过所述第二输出来连续地确定第二位线的值；Wherein, for each latch in the plurality of latch circuits, the first output is coupled to a first bit line of a pair of complementary bit lines in the plurality of pairs of complementary bit lines, so that in the memory The value of the first bit line is continuously determined by the first output during operation of the device, and the second output is coupled to a second bit line of the pair of complementary bit lines of the plurality of pairs for memory continuously determining the value of the second bit line via the second output during operation of the device; 其中，所述锁存器包括用于接收时钟信号的第二输入，其中所述锁存器的输出在由所述时钟信号的状态变化所确定的时间上根据所述数据线的值而改变值。wherein the latch includes a second input for receiving a clock signal, wherein the output of the latch changes value according to the value of the data line at a time determined by a state change of the clock signal . 10.一种存储器设备，包括：10. A memory device comprising: 第一写位线；first write bit line; 第二写位线，所述第二写位线是所述第一写位线的互补位线；a second write bit line, the second write bit line being the complementary bit line of the first write bit line; 一列存储器单元，该一列存储器单元与所述第一写位线和所述第二写位线相耦合；以及a column of memory cells coupled to the first write bit line and the second write bit line; and 锁存器电路，该锁存器电路具有与数据线相耦合的输入、根据所述数据线的值提供第一锁存值的第一输出、根据所述数据线的值提供第二锁存值的第二输出，所述第一输出与所述第一写位线相耦合，以便当且仅当在存储器设备操作期间所述第一输出上的值发生变化时所述第一写位线的值发生变化，所述第二输出与所述第二写位线相耦合，以便当且仅当在存储器设备操作期间所述第二输出上的值发生变化时所述第二写位线的值发生变化；a latch circuit having an input coupled to a data line, a first output providing a first latched value based on the value of the data line, a second latched value based on the value of the data line a second output of the first output coupled to the first write bit line such that the first write bit line is coupled to if and only if the value on the first output changes during operation of the memory device changes in value, the second output is coupled to the second write bit line such that the value of the second write bit line changes if and only if the value on the second output changes during operation of the memory device change; 读位线，所述一列存储器单元与所述读位线耦合。A read bit line to which the column of memory cells is coupled.
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Granted publication date: 20100505

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