CN101060283A - Controller for a DC to DC converter having linear mode and switch mode capabilities - Google Patents
Controller for a DC to DC converter having linear mode and switch mode capabilities Download PDFInfo
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Abstract
A controller for a DC to DC converter. The controller may comprise linear mode circuitry and switch mode control circuitry. The linear mode control circuitry may be capable of providing a first control signal to a controlled device of the DC to DC converter. The controlled device may operate as a variable resistor in response to the first control signal to control an output voltage of the DC to DC converter. The switch mode control circuitry may be capable of providing a second control signal to the controlled device of the DC to DC converter. The controlled device may turn ON and OFF in response to the second control signal to control the output voltage of the DC to DC converter. One of the linear mode control circuitry and the switch mode control circuitry may be enabled. The controller may also include protection circuitry.
Description
[technical field]
The disclosure is about a kind of DC to DC converter, especially about being used for the DC to DC converter controller.
[background technology]
Various electronic equipments all may be used one or more DC to DC converter such as portable computer, mobile phone, personal digital assistant and other portable or non-portable electric appts.DC to DC converter is converted to a DC input voitage VD of calibration usually.In electronic equipment, DC to DC converter can be used for multiple load, and various loads height relatively differ.The differentiation of high capacity and low load is different according to concrete application, system and/or customer requirements.
In the various DC to DC converter, what have is suitable for low load, and what have is suitable for high capacity.The linear model pressurizer promptly is a kind of DC to DC converter that is suitable for to low electric.The linear model pressurizer can be monitored the variation of VD and provide signal to a transistor, makes output voltage remain on required numerical value.A kind of in the linear model pressurizer is low dropout voltage regulator (LDO), can give low relatively electric, and pressure drop is little, and output noise is low.Another kind in the DC to DC converter is the switching mode DC to DC converter, makes output voltage remain on required numerical value by the one or more transistors in switch DC/DC converter.This type of switching mode DC to DC converter can provide the output voltage of calibration under high capacity, efficient is higher relatively.
For can high load that can be low under different condition, conventional method is to use one type DC to DC converter when hanging down load, as LDO, when high capacity, use another DC to DC converter, as the switching mode DC to DC converter, do not coexist according to condition and to switch between two converters.This kind method is used two DC to DC converter, and required element is more, and switching each other also needs extra pin, and cost is high and complicated.
Therefore, need a kind of DC to DC converter, to solve problems of the prior art.
[summary of the invention]
The object of the present invention is to provide a kind of DC to DC converter controller that is used for having simultaneously linear model and switching mode.
The invention provides a kind of controller that is used for DC to DC converter.This controller can comprise linear model circuit, switching mode control circuit and protective circuit.The linear model control circuit can provide one first control signal to the controlled device in the DC to DC converter.Controlled device responds first control signal, can be used as the output voltage of a variable resistor job with the control DC to DC converter.The switching mode control circuit can provide one second control signal to the controlled device in the DC to DC converter.Controlled device responds second control signal, as switch work, controls the output voltage of DC to DC converter by the closed and disconnected of switch.According to the state of enable signal, an in running order and control controlled device in linear model control circuit and the switching mode control circuit.Configurable protective circuit receives a signal of representing the DC to DC converter output voltage; and with it with under-voltage threshold ratio; if the signal of representing the DC to DC converter output voltage less than under-voltage threshold value, then compensates first or second control signal of exporting to controlled device.Also configurable protective circuit receives a signal of representing the DC to DC converter output voltage; and relatively with it and overvoltage threshold; if the signal of representing the DC to DC converter output voltage greater than overvoltage threshold, then compensates first or second control signal of exporting to controlled device.
The present invention also provides a kind of DC to DC converter.This DC to DC converter can comprise that a controlled device and a controller control this device.Controller can comprise linear model circuit and switching mode circuit.The linear model control circuit can provide first control signal to the controlled device in the DC to DC converter.Controlled device responds first control signal, can be used as the output voltage of variable resistor work with the control DC to DC converter.The switching mode control circuit can provide one second control signal to the controlled device in the DC to DC converter.Controlled device responds second control signal, as switch work, controls the output voltage of DC to DC converter by the closed and disconnected of switch.According to the state of enable signal, an in running order and control controlled device in linear model control circuit and the switching mode control circuit.Configurable protective circuit receives a signal of representing the DC to DC converter output voltage; and with it with under-voltage threshold ratio; if the signal of representing the DC to DC converter output voltage less than under-voltage threshold value, then compensates first or second control signal of exporting to controlled device.Also configurable protective circuit receives a signal of representing the DC to DC converter output voltage; and relatively with it and overvoltage threshold; if the signal of representing the DC to DC converter output voltage greater than overvoltage threshold, then compensates first or second control signal of exporting to controlled device.
The present invention also provides a kind of manner of execution of DC to DC converter.This method was included in for first period provides one first control signal to the controlled device in the DC to DC converter, first control signal is provided by the linear model control circuit of controller, and controlled device responds first control signal is controlled DC to DC converter as variable resistor work output voltage.This scheme also can be included in for second period provides one second control signal to the controlled device in the DC to DC converter, second period and first period are not overlapping, second control signal is provided by the switching mode control circuit of controller, controlled device responds second control signal, controls the output voltage of DC to DC converter by switch closure and disconnection.This scheme also can comprise with representing the signal of DC to DC converter output voltage and overvoltage threshold and under-voltage threshold ratio, if this signal greater than overvoltage threshold or less than under-voltage threshold value, then compensates first or second control signal.
The present invention also provides a kind of equipment.The integrated circuit that this equipment comprises can be selected to rechargeable battery in multiple charge mode and charge.Can comprise switching mode and linear model in the multiple charge mode.
[description of drawings]
In the following drawings, the similar numeral of similar portions, in conjunction with the detailed description relevant with accompanying drawing, the characteristic and the advantage of the embodiment of the invention are apparent.
Fig. 1 is according to an electronic apparatus system of the present invention;
Fig. 2 is the block diagram of an embodiment of the DC to DC converter among Fig. 1;
Fig. 3 is for comprising the circuit diagram of the DC to DC converter of controller among Fig. 2;
Fig. 4 is the various signature tune line charts of the pulse-width signal of Fig. 3 middle controller;
Fig. 5 is the driver embodiment circuit diagram of the pulse-width modulation circuit of Fig. 3 middle controller;
Fig. 6 is the overvoltage/under-voltage protecting circuit embodiment circuit diagram of Fig. 3 middle controller;
Fig. 7 provides an embodiment of enable signal for the controller in Fig. 2 or Fig. 3;
Fig. 8 provides another embodiment of enable signal for the controller in Fig. 2 or Fig. 3;
Fig. 9 is the graph of simulation results figure of DC to DC converter among Fig. 3;
Figure 10 be among Fig. 9 curve from the enlarged drawing of LDO pattern when the PWM mode switch;
Figure 11 be among Fig. 9 curve from the enlarged drawing of PWM pattern when the LDO mode switch;
Figure 12 is the curve of DC to DC converter checking result among Fig. 3;
Figure 13 is a Figure 12 middle part component curve from the enlarged drawing of LDO pattern when the PWM mode switch;
Figure 14 is a Figure 12 middle part component curve from the enlarged drawing of PWM pattern when the LDO mode switch;
Figure 15 is the flowchart of DC to DC converter according to an embodiment of the invention;
Figure 16 is the block diagram of another embodiment of DC to DC converter among Fig. 2;
Figure 17 is the circuit diagram of pulse-width modulation circuit among Figure 16.
Below describe in detail and will carry out in conjunction with illustrative embodiment, those skilled in the art will obviously can understand multiple alternatives, modification and variant.
[embodiment]
Fig. 1 is the block diagram of electronic equipment 100 of the present invention, and this equipment comprises 102, one DC to DC converter 104 of a power supply and a load 106.This electronic equipment 100 can be a plurality of devices, for example notebook computer, mobile phone, personal digital assistant or the like.Power supply 102 can be various power supplys, battery (lithium battery) for example, and coming provides direct voltage (Vin) without calibration to DC-DC controller 104.DC to DC converter can provide through the output voltage (Vout) of calibration and give load 106.Only provided a DC to DC converter 104 and a load 106 herein for simplicity, in fact this electronic equipment 100 can have a plurality of DC to DC converter and a plurality of load.
Fig. 2 is the more detailed block diagram of the DC to DC converter 104 among Fig. 1.DC to DC converter 104 generally comprises a controller 201 and is used for the state of oxide-semiconductor control transistors Q1 or controls the output voltage V out that other transistor is controlled DC to DC converter simultaneously.Transistor Q1 may be various transistors.Controller 201 can comprise linear model control circuit 202 and switching mode control circuit 204." circuit " can comprise hardware circuit, programmable circuit, the state machine circuit of single or multiple combinations and/or can store the firmware of the instruction of being carried out by programmable circuit herein.In the time period different, non-overlapping copies, according to the enable signal state of 212 ends, the state of the transistor Q1 in the control DC to DC converter in linear model control circuit 202 and the switching mode control circuit 204.
If enable signal is 0, switching mode control circuit 204 lost efficacy, and did not transmit any control signal to transistor Q1.Linear model control circuit 202 responds these enable signals, comes the state of oxide-semiconductor control transistors Q1 by off switch SW.When switch SW is closed, linear model control circuit 202 provides the first control signal hdr_ldo to transistor Q1, respond this first control signal from linear model control circuit 202, transistor Q1 works in the range of linearity and controls the output voltage of DC to DC converter.First control signal can be analog voltage signal.
If enable signal is 1,204 work of switching mode control circuit also provide one second control signal to transistor Q1.Not gate 209 is output as 0, makes switch SW open.Like this, linear model control circuit 202 uncontrollable transistor Q1.Response is from second control signal of switching mode control circuit 204, and transistor Q1 controls the output voltage of DC to DC converter by the conversion of ON and OFF.Can provide one to represent that current output voltage Vout's feed back signal to linear model control circuit 202 and switching mode control circuit 204, by contrast feedback signal and reference voltage level, or consider simultaneously to send first and second control signals by linear switch control circuit 202 and switching mode control circuit 204 by other necessary factor.
That Fig. 3 shows is an embodiment---the DC to DC converter 104a of DC to DC converter 104 among Fig. 2.Controller 201a can comprise low drop-out voltage pressurizer (LDO) circuit 202a, as linear model circuit 202.Controller 201a also can comprise pulse-width modulation (PWM) circuit 204a, as switching mode control circuit 204.As shown in Figure 3, pwm circuit 204a can be used as the work of the asynchronous PWM controller of voltage mode control.In other embodiments, switching mode control circuit 204 can comprise the controller of other type, comprises the current control mode controller, isochronous controller, or pulse frequency modulated (PFM) controller, but be not limited thereto.Transistor Q1 can be p type metal oxide semiconductor field-effect transistor (MOSFET) or PMOS pipe, according to the difference of the state of enable signal (en), use its gate electrode to receive from first control signal of LDO circuit 202a or from second control signal of pwm circuit 204a.
If enable signal is 0, drive 316 and be in high-impedance state, pwm circuit 204a does not work.LDO circuit 202a work also offers its control signal (hdr_ldo) by off switch SW the control end of PMOS transistor Q1.The control signal (hdr_ldo) that LDO circuit 202a provides can be analog voltage signal, and transistor Q1 responds this control signal and works in the range of linearity, adjusts the size of output voltage V out by the size of regulating institute's conducting electric current.The control signal that responds LDO circuit 202 as transistor Q1 works in the range of linearity, and the ripple voltage of the output voltage of DC to DC converter can remain on an extremely low level, and the quiescent current that controller 201a consumes is also very little.
In dc operation, the difference of 322 pairs of reference voltage signals of amplifier and magnitude of voltage V1 is carried out error and is amplified, and sends a suitable output control signal (hdr_ldo) by the switch SW of closing and gives transistor Q1.Transistor Q1 responds this control signal, is operated in linear zone, simultaneously by adjusting output voltage V out, makes voltage error signal approach zero as far as possible.
For instance, if the output voltage V out at terminal 336 places has surpassed required magnitude of voltage, corresponding feedback voltage value V1 also can increase.At this moment, two inputs of amplifier 322 will have voltage difference, and this voltage difference makes amplifier 322 control signals of output (hdr_ldo) give transistor Q1, and transistor Q1 will reduce electric current to reduce output voltage V out.Opposite, if the output voltage V out at terminal 336 places is lower than required magnitude of voltage, corresponding feedback voltage value V1 also can reduce.This voltage difference makes amplifier 322 control signals of output (hdr_ldo) give transistor Q1, and transistor Q1 will increase electric current to increase output voltage V out.
When enable signal is 1, driver 316 work of pwm circuit 204a also are transferred to PMOS transistor Q1 with pwm control signal (hdl).And the output of inverter 209 will become 0, and switch SW is opened, and stop control signal (hdr_ldo) the control PMOS transistor Q1 that sends from LDO circuit 202a.POMS transistor Q1 adjusts output voltage according to the duty ratio of pwm control signal (hdr) by the cyclic transformation of ON and OFF.Therefore when enable signal is 1, the mode with the PWM controller of controller 201a is worked, and PMOS transistor Q1 is as switch work, and its switching frequency determines that by the ramp signal that crystal oscillator 314 sends efficient is higher than 90%.
Figure 4 shows that the comparison signal 402 that is input to the non-inverting input of comparator 312 among Fig. 3, and the ramp signal 404 (coming from the crystal oscillator 314 among Fig. 3) that is input to its inverting input.Along with the rising and the reduction of comparison signal 402 values, the crosspoint of comparison signal 402 and ramp signal changes thereupon.The pwm_in signal 342 of comparator 312 outputs obtains a pulse duration thus, and duty ratio is by the value decision in crosspoint.When the comparison signal reduction, the duty ratio of pwm_in signal 342 will reduce, and when the comparison signal rising, the duty ratio of pwm signal will improve.Driver 316 receives pwm_in signal 342, produces an output pwm signal (hdr) and gives PMOS transistor Q1, and this output pwm signal (hdr) is the reverse signal of pwm_in signal 342, as shown in Figure 4.
Fig. 5 is an embodiment 316a of the driver 316 of pwm circuit 204a among Fig. 3.Driver 316a can comprise 504, one NAND doors 512 of 502,506,508,510,514,516,518, one NOR doors of a plurality of inverters, and transistor Q2 and Q3.Q2 can manage for PMOS, and Q3 can be n type MOSFET or NMOS pipe.
When enable signal is 0, inverter 502 is output as 1.One of NOR door 504 is input as 1, and its output also is 0.Like this, the output of inverter 506 then is 1, and inverter 508 is output as 0, thus inverter 510 be input as 1.Transistor Q2 is a PMOS pipe in the present embodiment, thereby output 1 state of PMOS pipe response inverter 510 becomes OFF.Simultaneously, when enable signal was 0, NAND door 512 was output as 1, and the output of inverter 514 then is 0 like this, and inverter 516 is output as 1, and inverter 518 be input as 0.Transistor Q3 is a NMOS pipe in the present embodiment, and enable signal is that the state of 0 o'clock transistor Q3 also is OFF, and driver 316a does not work.Because when enable signal was 0, the pair of transistor of hdr control signal is provided: PMOS transistor Q2 and nmos pass transistor Q3 were OFF, do not have output signal hdr to offer the terminal 522 of driver 316a.Therefore, when enable signal was 0, driver 316a was with ineffective.In other words, when enable signal is 0, driver 316a will be high-impedance state.
When enable signal is 1, the hdr signal will be the reverse signal of pwm_in signal, as shown in Figure 4.The pwm_in signal may be 0 or 1.When the pwm_in signal is 1 when simultaneously enable signal is 1, NOR door 504 is output as 0, and like this, the output of inverter 506 then is 1, and inverter 508 is output as 0, thereby inverter 510 is output as 1.Thereby output 1 state of PMOS pipe Q2 response inverter 510 becomes OFF.Simultaneously, when the pwm_in signal is 1 when simultaneously enable signal is 1,3 inputs of NAND door 512 are 1 all, and at this moment it is output as 0.This just makes inverter 518 be output as 1, thereby the state of nmos pass transistor Q3 is ON.
When the pwm_in signal is 0 when simultaneously enable signal is 1, NAND door 512 is output as 1, thereby inverter 518 is output as 0, the output of nmos pass transistor Q3 response inverter 518, and its state becomes OFF.At this moment, 3 inputs of NOR door 504 all are 0, and NOR door 504 is output as 1 like this, thereby inverter 510 is output as 0.Thereby the output state of PMOS pipe Q2 response inverter 510 becomes ON.Therefore, when enable signal was 1, the hdr signal will be the reverse signal of pwm_in signal, as shown in Figure 4.When enable signal was 0, transistor Q2 and Q3 closed, and driver 316a does not work.
Figure 6 shows that overvoltage/under-voltage protecting circuit 326 among Fig. 3.Usually, if do not detect overvoltage or under-voltage, " comp " among Fig. 3 and " hdl_ldo " signal will can not compensated.When detect finding that undervoltage condition is arranged, comp will by on draw and the hdl_LDO signal will be by drop-down, thereby raise output voltage V out.When detect finding that overpressure situation is arranged, comp will by drop-down and hdl_LDO signal will by on draw, thereby force down output voltage V out.
Overvoltage/under-voltage protecting circuit 326a comprises two comparators 602 and 604.On behalf of the feedback signal (fb) of current output voltage and a under-voltage threshold values, 602 pairs of under-voltage comparator make comparisons.If feedback signal is higher than under-voltage threshold values, signal 0 of comparator 602 outputs; If feedback signal is equal to or less than under-voltage threshold values, signal 1 of comparator 602 outputs.Same, 604 pairs of feedback signals of overvoltage comparator and an overvoltage threshold values are made comparisons.If feedback signal is lower than the overvoltage threshold values, signal 0 of comparator 604 outputs; If feedback signal is equal to or higher than the overvoltage threshold values, signal 1 of comparator 604 outputs.
During operation, when enable signal be 1 (pwm circuit 204a work this moment) simultaneously feedback signal be not less than under-voltage threshold values and also be not more than the overvoltage threshold values, comparator 602 and 604 output all are 0.Thereby NAND door 606 is output as 1.PMOS pipe Q4 responds this signal, and state becomes OFF.At this moment inverter 608 is output as 1, thereby NAND door 610 is output as 0.Like this, the state of NMOS pipe Q5 also becomes OFF.Therefore, will offer the comp signal without any compensation in this case.
Equally, when enable signal be 0 (LDO circuit 202a work this moment) simultaneously feedback signal be not less than under-voltage threshold values and also be not more than the overvoltage threshold values, comparator 602 and 604 output all still are 0.Like this, two inputs of NOR door 612 all are 0, thereby it is output as 1.PMOS pipe Q6 responds this signal, and state is OFF.At this moment NOR door 620 is output as 0, and NMOS pipe Q7 responds this signal, and state also is OFF.Therefore, will offer the hdr_LDO signal without any compensation in this case.
When enable signal is 1 (pwm circuit 204a work this moment), feedback signal is lower than under-voltage threshold values simultaneously, and the output of comparator 602 then is 1.At this moment two of NAND door 606 inputs all are 1, thereby it is output as 0.PMOS pipe Q4 responds this signal, thereby state becomes and draws the comp signal to comph on the ON.By signal comp signal is pulled to comph, the duty ratio of pwm_in signal will become greatly, so just can improve output voltage values and feedback voltage value.
When enable signal is 1 (pwm circuit 204a work this moment), simultaneously feedback signal high with the overvoltage threshold values, the output of overvoltage comparator 604 then is 1.Thereby inverter 608 is output as 0.It is 0 that one of the input of NAND door 610 is 1 one, and it is output as 1.NMOS pipe Q5 responds this signal, and state becomes ON, thereby drop-down comp signal is to compl.By signal comp signal is pulled down to compl, the duty ratio of pwm_in signal will diminish, and so just can reduce output voltage values and feedback voltage value.
When enable signal is 0 (LDO circuit 202a work this moment), simultaneously feedback signal high with the overvoltage threshold values, the output of overvoltage comparator 604 then is 1.It is 0 that one of the input of NOR door 612 is 1 one, and it is output as 0.PMOS pipe Q6 responds this signal, and state becomes ON, thus on draw the hdr_ldo signal to hdr_ldoh, so just can reduce output voltage values and feedback voltage value.
Enable signal is 0 (LDO circuit 202a work this moment), and feedback signal is lower than under-voltage threshold values simultaneously, and the output of under-voltage comparator 602 then is 1.Because the output QN of d type flip flop 616 also is 1, two inputs of NAND door 618 all are 1, and its output just is 0.Like this, two inputs of NOR door 620 are 0 all, and it is output as 1.NMOS pipe Q7 responds this signal, and state becomes ON, thereby drop-down hdr_ldo signal so just can improve output voltage values to hdr_ldol.
Overvoltage/under-voltage protecting circuit 326a can realize the smooth transformation of controller 201 equally, comprises from linear model switching to switching mode and switching to linear model from switching mode.Usually, between the transfer period of linear model and switching mode, the reaction speed of feedback control loop is enough to output voltage V out is maintained between overvoltage and the under-voltage threshold values.Yet; if the instantaneous heavy load of following in the handoff procedure causes output voltage V out to be higher than the overvoltage threshold values or is lower than under-voltage threshold values, controller 201 will utilize overvoltage/under-voltage protecting circuit 326a to force comp or hdr_ldo signal to reach a certain magnitude of voltage and be operated in the hysteresis mode of operation.
" hysteresis " this notion also can be used for describing the work of comparator.A desirable comparator (for example Vinp and Vinm) under the situation that two inputs equate can switch between ON and OFF in circulation." hysteresis comparator " can avoid comparator vibration in this case." hysteresis comparator " for example during Vinp=Vinm, is output as 0, and is output as 1 under the situation of Vinp=Vinm+ Δ V under the situation that two inputs equate, the Δ V here can be the sub-fraction of Vinm.
" the hysteresis mode of operation " among Fig. 6 and the operation class of hysteresis comparator are seemingly.For instance; the output voltage of DC to DC converter 104a is controlled by overvoltage shown in Figure 6/under-voltage protecting circuit 326a in Fig. 3; Vout may not can reach the desirable voltage that is provided with, and the peak-to-peak value Δ V of a non-zero is arranged, and the value of Δ V is determined by threshold values: Δ V=ov_th-uv_th.
Therefore; overvoltage/under-voltage protecting circuit 326a can make comparisons to feedback voltage and the overvoltage threshold values of representing the DC to DC converter output voltage by (for example by comparator 604 shown in Figure 6), also can make comparisons to signal and the under-voltage threshold values of representing the DC to DC converter output voltage (for example by comparator 602 shown in Figure 6).When the signal of representing the DC to DC converter output voltage during greater than the overvoltage threshold values, overvoltage/under-voltage protecting circuit 326a can make output voltage reach required magnitude of voltage.And when the signal of representing the DC to DC converter output voltage during less than under-voltage threshold values, overvoltage/under-voltage protecting circuit 326a also can make output voltage reach required magnitude of voltage.This has just guaranteed that in linear model and PWM mode switch process this output voltage remains within the scope by overvoltage threshold values and the definition of under-voltage threshold values.
D type flip flop 616 has a reset signal (resetn) input.Reset signal can be avoided in Soft Start-up Process, and output voltage starts and rise to the under-voltage situation of wrong report the calibration output voltage process from about 0 volt.Under the soft start situation, initial low output voltage may trigger NMOS pipe Q7 and become ON.D type flip flop response reset signal, the QN pin is output as 0, and NAND door 618 is output as 1 like this, and NOR door 620 is output as 0, is OFF thereby keep the state of NMOS pipe Q7.Therefore, overvoltage/under-voltage protecting circuit 326a can start and rise to identification soft start state expectation/calibration output voltage process from about 0 volt at output voltage.Overvoltage/under-voltage protecting circuit 326a can also make comparator 602 quit work under the soft start state effectively, thereby avoids the under-voltage situation of erroneous judgement under the soft start state.
Enable signal can be provided by multiple source.Illustrated among Fig. 7 that a possible source of enable signal is a microcontroller 702.In case the user supresses the power knob 704 of portable equipment, microcontroller 702 will be opened.
Fig. 8 is for providing an embodiment of the controller 201 (201a) of enable signal according to various loading conditions.Inductive reactance 802 is used for inductive load current, and the pressure drop and the load current at its two ends are proportional.Because the resistance of inductive reactance 802 is very little, the pressure drop at its two ends is also very little, and this just needs induction amplifier 804 to come it is amplified, and produces a magnitude of voltage Vil that can represent load current.806 couples of Vil of comparator and a reference voltage ref1 compare, and look comparative result and generate enable signal.If Vil is greater than reference voltage ref1, the enable signal that comparator 806 produces is 1; If Vil is less than reference voltage ref1, the enable signal that comparator 806 produces is 0.In other words, when load was a relatively big load, controller control pwm circuit 204a work was to keep high efficiency; When load was a load that compares less, controller control LDO circuit 202a worked low noise output is provided.
Figure 9 shows that the analog result of the DC to DC converter 104a among Fig. 3.Lines 902 expression enable signals (en), the load current (from 1mA to 100mA) of lines 904 expression DC to DC converter, the output voltage V out of lines 906 expression DC to DC converter, and lines 908 expressions send to the gate drive signal of PMOS pipe Q1 control end.During t0 and t1, enable signal 902 is 0, and this moment, controller 201a was operated in the LDO pattern, and LDO circuit 202a provides gate drive signal to manage Q1 to PMOS.During this period, load current 904 is less relatively, remains on 1mA.Output voltage 906 then remains on 3.3V always.The LDO circuit 202a gate drive signal 908 that sends to PMOS pipe Q1 also keeps stable always during this period.
During t1, enable signal becomes 1 by 0, and to the PWM pattern, change by pwm circuit 204a replacement LDO circuit 202a provides gate drive signal to PMOS pipe Q1 to the indication transistor by the LDO mode switch.Represent the comp signal of building-out capacitor Cc magnitude of voltage to be lower than a certain magnitude of voltage (for example 1V), in the case, the duty ratio of the pwm_in signal 342 of generation is 0.Same, during t1 and t2, the hdr signal (908) that being used to of generation controlled PMOS pipe Q1 door is 1.And during t1 and t2, along with the increase of load current 904, output voltage 906 also decreases.
When t2, in case the comp signal has reached threshold values (for example 1V), the duty ratio of pwm_in signal 342 begins to increase, like this, during t2-t3 in, the hdr signal (908) that driver 316 produces produces vibration (can referring to Figure 10).Output voltage 906 begins to increase also slowly near desirable value 3.3V.During this period, because the cycling switch of PMOS pipe Q1, output voltage has certain ripple.
When t3, enable signal becomes 0 by 1, and to the LDO pattern, change by LDO circuit 202a replacement pwm circuit 204a provides gate drive signal (hdr_ldo signal) to PMOS pipe Q1 to indicating controller by the PWM mode switch.During t3-t4, along with the decline of load current 904, gate drive signal 908 also increases thereupon, so that output voltage 906 remains on the 3.3V of calibration.
Figure 10 shows that the enlarged drawing of the analog result of (before and after the t2) during Fig. 9 middle controller 201a is from the LDO mode switch to the PWM pattern; Figure 11 then be Fig. 9 middle controller 201a from the PWM mode switch to the LDO pattern during the enlarged drawing of analog result of (t3 before and after).
As everyone knows, a big challenge of LDO design is the stability of loop under the load current of wide region.Might become unstable under the situation in high capacity at LDO stable under the situation of low load.This just requires LDO is compensated, and therefore cost and complexity also increase.For example, the equivalent series resistance of capacitor C 1 (Resr) just can be used for compensation among Fig. 3.This just requires to increase an equivalent series resistance that accurately mates with capacitor C 1 in circuit, certainly will influence the temporal effect of output voltage V out.Other feasible compensation scheme also can increase cost and the complexity of LDO.
Table 1 is depicted as the LDO transactional analysis under low load (being 1mA in the example) and high capacity (being 100mA in the example) situation respectively.As shown in table 1, under low loading condition, LDO has the phase margin of 78.5882 enough degree, and under high load condition, the phase margin of LDO is for negative.This LDO needs some compensation to be issued to stable in high load condition.
Advantageously, the present invention controller 201a shown in Figure 3 only needs LDO circuit 202a work under low loading condition, and works at the next pwm circuit 204a that switches to of high load condition.Therefore, LDO circuit 202a only need the increase of a spot of cost and complexity compensate just can be stable work, it is stable that controller 201a then can keep under the load current of a wide region.
Figure 12 is the checking result curve of DC to DC converter among Fig. 3.Curve 1 is the voltage (Ven) of enable signal, and curve 2 is the feedback voltage (Vfb) of representative DC to DC converter output voltage.Curve 3 is the gate drive signal (Vhdr) of transistor Q1, and curve 4 is the load current (Iload) of DC to DC converter.Figure 13 is Ven among Figure 12, Vfb and the Vhdr curve enlarged drawing during from the PWM mode switch to LDO pattern (enable signal becomes 0 from 1).Figure 14 is Ven among Figure 12, Vfb and the Vhdr curve enlarged drawing during from the LDO mode switch to PWM pattern (enable signal becomes 1 from 0).Shown in Figure 12-14, the analog result of checking result and Fig. 9-11 is coincide.
Figure 15 shows that manner of execution 1500 according to the DC to DC converter of one embodiment of the invention.Step 1502 is included in a very first time section and one first control signal is provided for the controlled device of DC to DC converter, this first control signal is provided by the linear model control circuit of controller, controlled device responds this first control signal and is operated in linear zone, the output voltage of control DC to DC converter.Step 1504 is included in one second time period and one second control signal is provided for the controlled device of DC to DC converter, this second control signal is provided by the switching mode control circuit, second time period and very first time section are not overlapping, controlled device responds this second control signal and is operated in switching mode, the output voltage of control DC to DC converter.Step 1506 comprises and will represent signal and the overvoltage threshold and the under-voltage threshold of DC to DC converter output voltage, in the step 1508, if the signal of representing the DC to DC converter output voltage then compensates first or second control signal greater than overvoltage threshold or less than under-voltage threshold value.
Figure 16 is another embodiment 104b of DC to DC converter 104a among Fig. 3.Wherein with Fig. 3 in similarly assembly adopt similar label, repeat no more.DC to DC converter 104b can comprise a switch SW 2 in parallel with inductance L 1.When enable signal is 0, inverter 209 is output as 1, and switch SW 1 and SW2 close.When LDO circuit 202a provides analog control signal to controlled device 604, can obtain better transient effect by switch SW 2.
Controlled device 1604 can be multiple device, only needs to receive analog control signal and with the work of variable resistor form from LDO circuit 202a, can receive pwm control signal and be operated between ON and OFF circulation with switch form from pwm circuit 204b and switch and just can.In one embodiment, controlled device can be transistor, comprises polytype transistor such as bipolar nodal pattern transistor (BJT), field-effect transistor (FET) (PMOS transistor Q1 is MOSFET, for wherein a kind of).
Figure 17 is the circuit diagram of pwm circuit 204b among Figure 16.Pwm circuit can comprise crystal oscillator 314, error amplifier 310, comparator 312, and another embodiment 316b of driver 316 among Fig. 3.Among Figure 17, adopt similar label, do not giving unnecessary details with similar assembly among Fig. 3.Driver 316b can comprise transistor Q8 and the Q9 on the output stage of first inverter 1704, NOR door 1706, second inverter 1708, NAND door 1710, the 3rd inverter 1712 and driver 316b.Transistor Q8 can be the PMOS transistor, and Q9 can be nmos pass transistor.The output control signal hdr of driver 316b can be from node 1724 outputs, and this node is between the drain terminal of PMOS transistor Q8 and nmos pass transistor Q9.
When enable signal is that 0, the first inverter 1704 is output as 1.Because one of NOR door 1706 is input as 1, so it is output as 0.Second inverter 1708 is output as 1.Because transistor Q8 is the PMOS transistor among this embodiment, the output 1 of response inverter 1708, transistor is OFF.When enable signal is that 0 and second inverter 1708 is output as 1 for NAND door 1710, the NAND door is output as 1.The 3rd inverter 1712 is output as 0, and nmos pass transistor Q9 is OFF.Like this, when enable signal is that 0, two transistor Q8 and Q9 are OFF, driver 316b does not work.That is to say that enable signal is that 0 o'clock driver 316b is a high-impedance state.
When enable signal is 1, the hdr signal can be the reverse signal of pwm_in, as shown in Figure 4.The pwm_in signal may also may be 1 for 0.When pwm_in be 0 and enable signal be 1, NAND door 1710 is output as 1, the three inverter 1712 and is output as 0.Nmos pass transistor Q9 is OFF.Three inputs of NOR door 1706 are all 0, so it is output as 1, so second inverter 1708 is output as 0.PMOS transistor Q8 is ON.
When the pwm_in signal be 1 and enable signal be 1, NOR door 1706 is output as 0.Second inverter 1708 is output as 1, and it is OFF that PMOS transistor Q8 responds this output state signal.When the pwm_in signal be 1 and enable signal be 1, three inputs of NAND door 1710 all are 1, so be output as 0.The 3rd inverter 1712 is output as 1, so nmos pass transistor Q9 is ON.Like this, when enable signal is 1, the hdr signal can be the reverse signal of pwm_in, as shown in Figure 4.When enable signal is 0, because transistor Q8 and Q9 are OFF, driver 316b does not work.
Advantageously, can use a controller function linear model circuit and switching mode circuit.The operation that conventional method needs two DC to DC converter and two controllers just can finish only needs a controller and a DC to DC converter to finish now, and cost is minimized.Controller switches between linear model and switching mode, and both have a role to play.For instance, if the linear model circuit comprises the LDO circuit, controller can be with the LDO mode operation when hanging down load, and noise is reduced.The switching mode circuit can comprise pwm circuit, and controller with the PWM mode operation, provides pwm signal for the controlled device of DC to DC converter when high capacity.Efficient is improved during high capacity.In addition, when the LDO circuit only is used for hanging down load, need not costliness and complicated compensation scheme.And when the LDO circuit was used for high capacity, these compensation schemes were unavoidable.
The word of this paper and expression are all descriptive and non-limiting, so do not repel the equivalent (or part equivalent) of characteristic described herein, in the scope that claims defined various modifications can be arranged.Also may there be other modifications, variation and replacement.Therefore, claims are intended to contain all equivalents.
Claims (22)
1. the controller of a DC to DC converter is characterized in that, comprising:
The linear model control circuit, described linear model control circuit sends the controlled device of one first control signal to described DC to DC converter, described controlled device responds this first control signal as variable resistor work, to control the output voltage of described DC to DC converter;
The switching mode control circuit, described switching mode control circuit sends the controlled device of one second control signal to described DC to DC converter, described controlled device responds this second control signal, output voltage by the described DC to DC converter of change over switch State Control, according to the enable signal state, a described controlled device of control in above-mentioned linear model control circuit and the switching mode control circuit; And
Protective circuit; be used to receive the signal of the described DC to DC converter output voltage of representative and with itself and under-voltage threshold comparison; if this signal is less than under-voltage threshold value; protective circuit also can compensate first or second control signal that offers controlled device; this protective circuit also can be with above-mentioned signal and overvoltage threshold contrast; if this signal is greater than overvoltage threshold, the protective circuit compensation offers first or second control signal of controlled device.
2. controller as claimed in claim 1; it is characterized in that; described switching mode control circuit comprises pulse-width modulation (PWM) circuit; described second control signal comprises a pulse-width modulated output signal; if pwm circuit work; described controlled device is switched between opening and closing according to the duty ratio of PWM output signal; if the signal of wherein described representative DC to DC converter output voltage is less than under-voltage threshold value; protective circuit recently compensates the PWM output signal by improving duty, if this signal is greater than overvoltage threshold then recently compensate by reducing duty.
3. controller as claimed in claim 2, it is characterized in that, described pwm circuit comprises that a driver provides described PWM output signal, when described enable signal is in a kind of state, this actuator response enable signal provides PWM output signal, when enable signal is in another state, do not provide second control signal.
4. controller as claimed in claim 3 is characterized in that, described driver comprises:
One first inverter is used to receive enable signal and generates an output signal;
A NOR door receives the output of first inverter and receives the PWM input signal from comparator of described pwm circuit;
One second inverter receives the output signal of above-mentioned NOR door and first control signal is provided;
A first transistor receives first control signal;
A NAND door receives first control signal from described second inverter, receives enable signal and PWM input signal;
One the 3rd inverter receives the output of above-mentioned NAND door and generates second control signal; And
A transistor seconds receives above-mentioned second control signal.
5. controller as claimed in claim 4 is characterized in that, when described enable signal is 0, responds this enable signal, and its first and second transistor all is OFF.
6. controller as claimed in claim 4 is characterized in that, described first and second transistors have one to be ON according to the value of input pwm signal, and the PWM output signal that makes described driver provide is the reverse signal of described PWM input signal.
7. a DC to DC converter is characterized in that, comprising:
A controlled device;
A controller is used to control above-mentioned controlled device, and this controller comprises:
Linear model control circuit, this circuit provide the controlled device of one first control signal to described DC to DC converter, controlled device respond this first control signal as variable resistor work to control the output voltage of described DC to DC converter;
The switching mode control circuit, this circuit provides the controlled device of one second control signal to described DC to DC converter, controlled device responds this second control signal and is operated in the switching that circulates between ON and the OFF to control the output voltage of described DC to DC converter as switch, according to the enable signal state, a control controlled plant in described linear model control circuit and the switching mode control circuit; And
Protective circuit; be used to receive a described DC to DC converter output voltage of representative signal and with it with under-voltage threshold ratio; if this signal is less than under-voltage threshold value; protective circuit also can compensate first or second control signal that offers controlled device; this protective circuit also can compare above-mentioned signal and overvoltage threshold; if this signal is greater than overvoltage threshold, protective circuit also can compensate first or second control signal that offers controlled device.
8. DC to DC converter as claimed in claim 7 is characterized in that, described controlled device comprises a transistor, and this transient response first control signal responds second control signal as switch work in linear regional work.
9. DC to DC converter as claimed in claim 8, it is characterized in that wherein having an inductance to be connected to a transistorized end, other has a switch in parallel with this inductance, when the linear model control circuit transmitted first control signal to this transistor, above-mentioned switching response enable signal was closed.
10. DC to DC converter as claimed in claim 7; it is characterized in that; described switching mode control circuit comprises pulse-width modulation (PWM) circuit; described second control signal comprises the PWM output signal; when the work of switching mode control circuit and when controlling controlled device; controlled device is switched between ON and OFF according to the duty ratio of PWM output signal; if the signal of representing output voltage is less than under-voltage threshold value; protective circuit recently compensates the PWM output signal by increasing duty; if the signal of representing output voltage is greater than overvoltage threshold, protective circuit then recently compensates the PWM output signal by reducing duty.
11. DC to DC converter as claimed in claim 10, it is characterized in that, described pwm circuit comprises that a driver provides PWM output signal, when enable signal is in a kind of state, this driver provides PWM output signal, when enable signal is in another state, do not provide described second control signal.
12. DC to DC converter as claimed in claim 11 is characterized in that, described driver comprises:
One first inverter receives described enable signal and an output signal is provided;
NOR door receives the output signal of described first inverter and receives a PWM input signal from a comparator of described pwm circuit;
One second inverter receives the output signal of NOR door and first control signal is provided;
A first transistor receives first control signal;
A NAND door receives first control signal from second inverter, receives enable signal, and receives the PWM input signal;
One the 3rd inverter receives the output of NAND door and generates second control signal; And
A transistor seconds receives described second control signal.
13. DC to DC converter as claimed in claim 12 is characterized in that, when enable signal was 0, the first transistor and transistor seconds all were OFF.
14. DC to DC converter as claimed in claim 12, it is characterized in that, according to the value of PWM input signal, described the first transistor and transistor seconds have one to be ON, make that the PWM output signal that described driver provided is the reverse signal of PWM input signal.
15. the manner of execution of a DC to DC converter is characterized in that, comprising:
Provide the controlled device of one first control signal in very first time section to DC to DC converter, described first control signal is provided by the linear model control circuit of controller, controlled device responds first control signal, with variable resistor work and control the output voltage of this DC to DC converter;
Give the controlled device of DC to DC converter in one second control signal of the second time period low pass, second time period and very first time section are not overlapping, second control signal is provided by the switching mode control circuit of controller, controlled device responds second control signal, switches the output voltage of controlling described DC to DC converter between ON and OFF;
With the representative signal of described DC to DC converter output voltage and overvoltage threshold and under-voltage threshold ratio; And
If the signal of above-mentioned representative DC to DC converter output voltage greater than overvoltage threshold or less than under-voltage threshold value, then compensates first or second control signal.
16. manner of execution as claimed in claim 15, it is characterized in that, described compensating operation also is included in described very first time section and the transition period between second time period is moved the voltage of described DC to DC converter to a desirable value, makes output voltage remain in the scope that is defined by overvoltage threshold and under-voltage threshold value.
17. manner of execution as claimed in claim 15 is characterized in that, described switching mode control circuit comprises pulse-width modulation (PWM) circuit, and described second control signal comprises the PWM output signal, and its compensating operation comprises:
If the signal of representing output voltage then increases the duty ratio of PWM output signal less than under-voltage threshold value;
If the signal of representing output voltage greater than overvoltage threshold, then reduces the duty ratio of PWM output signal.
18. manner of execution as claimed in claim 15 is characterized in that, also comprises:
The feedback signal of the described DC to DC converter output current intensity of representative is compared with threshold value, if this feedback signal is less than this threshold value, then selection wire sexual norm control circuit provides first control signal to controlled device, if this feedback signal is more than or equal to this threshold value, then the selector switch mode control circuit provides second control signal to controlled device.
19. an equipment is characterized in that, comprising:
A kind of integrated circuit that can from multiple charge mode, make one's options to the rechargeable battery charging.
20. equipment as claimed in claim 19 is characterized in that, described multiple charge mode comprises switching mode and linear model.
21. an equipment is characterized in that, comprises controller as claimed in claim 1.
22. an equipment is characterized in that, comprises DC to DC converter as claimed in claim 7.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/250,048 | 2005-10-13 | ||
| US11/250,048 US7508176B2 (en) | 2004-05-14 | 2005-10-13 | Controller for a DC to DC converter having linear mode and switch mode capabilities |
Publications (2)
| Publication Number | Publication Date |
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| CN101060283A true CN101060283A (en) | 2007-10-24 |
| CN100525031C CN100525031C (en) | 2009-08-05 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2006101423155A Expired - Fee Related CN100525031C (en) | 2005-10-13 | 2006-09-28 | Controller for a DC to DC converter having linear mode and switch mode capabilities |
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| TW (1) | TWI314383B (en) |
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Also Published As
| Publication number | Publication date |
|---|---|
| TWI314383B (en) | 2009-09-01 |
| TW200721647A (en) | 2007-06-01 |
| CN100525031C (en) | 2009-08-05 |
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