CN101114832B - Fractional-N PLL Frequency Synthesizer - Google Patents

Abstract

The invention discloses a fractional-N phase-locked loop frequency synthesizer with a simpler circuit structure. It includes: a phase frequency detector for receiving a reference signal having a reference frequency and an overflow output signal, detecting a phase difference between the reference signal and the overflow output signal, and outputting a phase difference signal; the charge pump is used for receiving the phase difference signal and generating an output current related to the phase difference signal according to the magnitude of the phase difference signal; the loop filter is used for receiving the output current, smoothing the output current and converting and outputting a voltage control signal; the voltage control oscillator is used for receiving the voltage control signal and generating an output signal with voltage-controlled frequency according to the voltage control signal; and a delta sigma modulator having a frequency input for receiving the output signal, an overflow output for outputting the overflow output signal, and an integer value input for determining a ratio between the voltage controlled frequency and the reference frequency.

Description

Fractional-N PLL Frequency Synthesizer

technical field

The present invention relates to a fractional N phase-locked loop (Phase Locked Loop, PLL) frequency synthesizer realized by a Delta-Singer modulator (ΔΣModulator), in particular to a method for directly replacing a frequency divider (Divider ) and a fractional-N phase-locked loop frequency synthesizer implemented with a Delta-Singer modulator.

Background technique

Due to the rapid development of communication systems, such as hand-held telephone systems, frequency synthesizers with higher frequency resolution (Frequency Resolution) and faster frequency switching time (Frequency Switching Time) are the research and development personnel of related technologies. The component to be developed. However, the above requirements are difficult to achieve.

Please refer to FIG. 1 , which is an existing PLL frequency synthesizer with integer (Integer) N. The phase locked loop 100 includes a phase frequency detector (Phase Frequency Detector) 10, a charge pump (Charge Pump) 20, a loop filter (Loop Filter) 30, a voltage controlled oscillator (Voltage Controlled Oscillator) 40 and a frequency divider (Divider) 50. Wherein, the reference signal having a reference frequency F _ref is generated by, for example, a reference oscillator (Reference Oscillator, not shown), and the reference signal and a frequency divided signal (Frequency divided signal) are simultaneously input into the phase frequency detector 10 . The phase frequency detector 10 can detect the difference in phase and frequency between the reference signal and the frequency-divided signal, and then output a phase difference signal (Phase Difference Signal) to the charge pump 20 . Next, the charge pump 20 generates an output current corresponding to the phase difference signal to the loop filter 30 according to the magnitude of the phase difference signal. Then, the loop filter 30 smoothes the output current and converts it into a voltage control signal to the voltage controlled oscillator 40 . The VCO 40 can generate an output signal according to the voltage control signal, and the output signal has a voltage control frequency F _vco . The frequency divider 50 can receive the output signal and divide it by N times of an integer to generate the frequency-divided signal for input to the phase frequency detector 10 , so the PLL frequency synthesizer can obtain F _voc =N*F _ref .

Obviously, since N is an integer, the voltage-controlled frequency (F _vco ) of the output signal must be an integer multiple of the reference frequency (F _ref ). Therefore, the frequency resolution of the output of the existing integer-N phase-locked loop frequency synthesizer lower.

In recent years, fractional-N phase-locked loop frequency synthesizers have emerged. Since N is a fraction, the voltage-controlled frequency (F _vco ) of the output signal is a fractional multiple of the reference frequency. Therefore, the frequency resolution output by the phase-locked loop frequency synthesizer with fraction N is relatively high.

Please refer to FIG. 2 , which is a conventional fractional-N PLL frequency synthesizer. The difference between FIG. 2 and FIG. 1 lies in that the integer N of the multimode frequency divider (Divider) 55 can be changed, and the circuit hardware design is relatively complicated. The integer N of the multimode frequency divider 55 is controlled by a first integer (A) provided by a register 70 and a delta-singer modulator (hereinafter referred to as a ΔΣ modulator) 60. a second integer. As can be seen from FIG. 2, the ΔΣ modulator 60 has a frequency input terminal and a first value (n) input terminal, and the frequency input terminal of the ΔΣ modulator 60 is connected to the output terminal of the multimode frequency divider 55 and the ΔΣ modulation The output terminal of the device 60 is connected to an adder 65. Furthermore, the register 70 stores an integer A, the output end of the register 70 is connected to the adder 65 , and the integer N of the divider (Divider) changes according to the output value of the adder 65 .

Figure 3, which is a first-order (First Order) ΔΣ modulator implemented with a digital accumulator (Digital Accumulator). For example, the size (Size) of the adder 62 is d bits (d bits), has a frequency input terminal, a first input terminal (X), a second input terminal (Y), and a total output terminal (X+Y), and an overflow (Overflow) output terminal (O). Furthermore, the first input terminal (X) can input a first value (n), the second input terminal (Y) is connected to the summing output terminal (X+Y), and the overflow output terminal (O) can be viewed It is the output terminal of the first-order ΔΣ modulator. Taking n=5 and d=4 as an example, Table 1 below represents the output values of the summing output terminal (X+Y) and the overflow output terminal (O) as the frequency changes.

Table I:

(X+Y) 5 10 15 4 9 14 3 8 13 2 7 12 1 5 11 0 5 10 15 4 (O) 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 1

According to Table 1, it can be known that the output values of the summing output terminal (X+Y) and the overflow output terminal (O) will take every 16 frequencies as a cycle, and repeatedly generate the same output value. Furthermore, on average every 16 frequencies, the overflow output terminal will be toggled (Toggle) 5 times. Similarly, when the first value (n) is changed to 9, it means that the overflow output terminal will be triggered 9 times for every 16 frequencies on average. Therefore, the first value (n) represents the average number of times the overflow output terminal will be triggered every 16 frequencies. The repetition period of 16 frequencies is determined by the size of the accumulator, and since d=4, 2 ⁴ represents 16 frequencies. Therefore, when the size of the adder 62 is d bits and the first value is n, representing 2 ^d frequencies, the overflow output terminal will be toggled n times, and the sum output (X+Y) and the overflow output The output value of the terminal (O) will repeat the same output value every 2 ^d frequency as a cycle. The first-order ΔΣ modulator in FIG. 3 can also be represented by a discrete time (Discrete Time) function, as shown in FIG. 4 . As shown in Figure 4, when the accumulator overflows, because the value has exceeded the value that can be represented by its size (Size), the comparator 64 will output "1". Does not exceed the value that can be represented by its size (Size), so the comparator 64 will output "0", that is to say, the comparator 64 is based on the maximum value that the adder can represent as the threshold value (Threshold) Compare.

Please refer to FIG. 2 again, since the frequency of the ΔΣ modulator 60 is determined by the output of the multimode frequency divider 55 . Therefore, taking the size d=4 and n=5 of the ΔΣ modulator as an example, every 16 frequencies, the overflow output terminal (O) of the ΔΣ modulator 60 will be triggered 5 times. That is to say, in every 16 frequencies, when the overflow output terminal (O) is not triggered, the multimode frequency divider N=A, on the contrary, when the overflow output terminal (O) is triggered, the multimode frequency divider Device N=A+1. Therefore, on average, F _vco =(A+5/16)*F _ref , that is, N can be regarded as a non-integer (fraction, in this example, A+5/16). Similarly, when the size of the ΔΣ modulator is d and the input value is n, it will make N=A+n/2 ^d , therefore, a fractional-N PLL frequency synthesizer can be realized.

Since the fractional-N PLL frequency synthesizer shown in FIG. 2 must provide a ΔΣ modulator 60 with a register 70 to control the multi-mode frequency divider 55 . However, due to the complicated connection relationship of the above-mentioned circuit, the design of the circuit will be more difficult. And because the single integer frequency divider (N) in FIG. 1 does not need to be controlled by other circuits, the circuit design of the single integer frequency divider 50 in FIG. 1 is simpler and simpler than that of the multi-mode frequency divider 55 in FIG. 2 . Therefore, how to improve the above deficiency and design a fractional-N PLL frequency synthesizer with simple structure is the main purpose of the present invention.

Contents of the invention

The technical problem to be solved by the present invention is to provide a fractional-N phase-locked loop frequency synthesizer, which has a simpler circuit structure and makes the circuit design simpler.

In order to solve the above technical problems, the present invention provides a fractional-N phase-locked loop frequency synthesizer, which includes: a phase frequency detector, which can receive a reference signal with a reference frequency and an overflow output signal and can detect the A phase difference signal is output after the difference between a phase and a frequency between the reference signal and the overflow output signal; a charge pump is used to receive the phase difference signal and generate a phase difference signal corresponding to the phase difference signal according to the magnitude of the phase difference signal An output current of the signal; a loop filter for receiving the output current and smoothing the output current to convert and output a voltage control signal; a voltage-controlled oscillator for receiving the voltage control signal and controlling the signal according to the voltage generating an output signal having a voltage-controlled frequency; and a delta-sigma modulator having a frequency input capable of receiving the output signal, an overflow output capable of outputting the overflow output signal, and an integer value input, It is used to determine a ratio between the voltage control frequency and the reference frequency.

In addition, a fractional-N phase-locked loop frequency synthesizer is provided, which includes: a phase frequency detector, which can receive a reference signal with a reference frequency and an overflow output signal, and can detect the reference signal and the Outputting a phase difference signal after overflowing the difference between a phase and a frequency between the output signals; a charge pump for receiving the phase difference signal and generating an output related to the phase difference signal according to the magnitude of the phase difference signal current; a loop filter, used to receive the output current and smooth the output current to convert and output a voltage control signal; a voltage-controlled oscillator, used to receive the voltage control signal and generate a voltage control signal according to the voltage control signal An output signal of frequency control; prescaler, for outputting a frequency reduction signal after dividing the voltage control frequency by a first integer value; and a ΔΣ modulator, having a frequency input capable of receiving the frequency reduction signal terminal, an overflow output terminal capable of outputting the overflow output signal, and a second integer value input terminal, wherein the fractional-N phase-locked loop frequency synthesizer determines the voltage according to the first integer value and the second integer value A ratio between the control frequency and the reference frequency.

Because the present invention replaces the existing fractional-N phase-locked loop frequency synthesizer with the ΔΣ modulator, the circuit architecture that must be completed by the ΔΣ modulator, buffer, and multi-mode frequency divider, therefore, the fractional-N phase-locked loop of the present invention The frequency synthesizer has the advantages of simple structure and easy design.

Description of drawings

The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments.

Fig. 1 is an existing PLL frequency synthesizer with integer N.

Figure 2 is an existing fractional-N phase-locked loop frequency synthesizer.

Figure 3 is a first-order ΔΣ modulator implemented with a digital adder.

Figure 4 is a first-order ΔΣ modulator represented by a discrete time (Discrete Time) function.

FIG. 5 is a fractional-N PLL frequency synthesizer according to an embodiment of the present invention.

FIG. 6 is a graph showing the relationship between the voltage control signal and time output by the voltage control oscillator of the fractional-N phase-locked loop frequency synthesizer implemented by the first-order ΔΣ modulator.

FIG. 7 is a spectrum diagram of the fast Fourier transform of the first-order ΔΣ modulator in the fractional-N phase-locked loop frequency synthesizer implemented by using the first-order ΔΣ modulator.

FIG. 8 is a schematic diagram of a discrete time function of a second-order ΔΣ modulator.

9 is a graph showing the relationship between the voltage control signal and time output by the voltage control oscillator of the fractional-N phase-locked loop frequency synthesizer implemented by the second-order ΔΣ modulator according to an embodiment of the present invention.

FIG. 10 is a spectrum diagram of the FFT of the second-order ΔΣ modulator in the fractional-N PLL frequency synthesizer implemented by using the second-order ΔΣ modulator according to an embodiment of the present invention.

[Description of main component symbols]

10 phase frequency detector 20 charge pump

30 Loop Filter 40 Voltage Controlled Oscillator

50, 55 frequency divider 60 Δ∑ modulator

62 Adder 64 Comparator

65 Adder 70 Register

100 PLL 200 PLL Frequency Synthesizer

210 phase frequency detector 220 charge pump

230 Loop Filter 240 Voltage Controlled Oscillator

250 Δ∑ modulator 252 First comparator

254 second comparator

Detailed ways

In Fig. 2, taking the size d=4 of the first-order ΔΣ modulator and the first value n=5 as an example, it means that every 16 frequencies, the overflow output terminal (O) of the ΔΣ modulator 60 will be triggered 5 times . From the viewpoint of frequency, it can be regarded as every 16 frequencies, the overflow output terminal (O) will generate 5 frequencies, that is to say, the frequency of the overflow output terminal (O) is 5/16 of the frequency input terminal frequency times, so according to the input first numerical value (n), the frequency of the overflow output terminal (O) can be determined so that the frequency of the overflow output terminal (O) becomes a fractional relationship with the frequency of the frequency input terminal; and the buffer Put the integer 200 in 70 as an example. The output of the adder 65 is 200 or 201 for the multi-mode frequency divider to divide by 55. It seems to be equivalent to the frequency division of 200+5/16 for a long time, but the multi-mode frequency division The implementation of the device 55 is complex and prone to generate spurs on the frequency spectrum.

Please refer to FIG. 5 , which is a fractional-N PLL frequency synthesizer of the present invention. The PLL frequency synthesizer 200 includes a phase frequency detector (Phase Frequency Detector) 210, a charge pump (Charge Pump) 220, a loop filter (LoopFilter) 230, a voltage controlled oscillator (Voltage Controlled Oscillator) 240 and a ΔΣ modulator 250. Wherein, a reference signal with a reference frequency (Fref) is generated by a reference oscillator (not shown), and the reference signal and an overflow output signal (Overflow Output Signal) are input to the phase frequency detector 210 at the same time. The phase frequency detector 210 can detect the phase and frequency difference between the reference signal and the overflow output signal, and then output a phase difference signal (Phase Difference Signal) to the charge pump 220. Next, the charge pump 220 generates an output current related to (for example, proportional to) the phase difference signal to the loop filter 230 according to the magnitude of the phase difference signal. Then, the loop filter 230 smoothes the output current and converts it into a voltage control signal to the voltage controlled oscillator 240 . The VCO 240 can generate an output signal according to the voltage control signal, and the output signal has a voltage control frequency (Fvco). The frequency input terminal of the ΔΣ modulator 250 can receive the output signal, and the overflow output terminal of the ΔΣ modulator 250 can output the overflow output signal for inputting to the phase frequency detector 210 .

Taking the size of the ΔΣ modulator 250 as d and the first value as n as an example, when an output signal with a voltage-controlled frequency (Fvco) is connected to the frequency input of the ΔΣ modulator 250, on average every n/2 ^d Frequency, the overflow output terminal can generate a pulse, therefore, the ΔΣ modulator 250 can output high and low level signals according to the frequency of the frequency input terminal. Therefore, the frequency of the overflow output signal generated by the overflow output terminal is n/2 ^d times the voltage control frequency (Fvco). Since the frequency of the overflow output signal is equal to the reference frequency (Fref), Fref=n/ ^2d *Fvco can be obtained, that is, Fvco= ^2d /n*Fref. Taking d=4, n=5 as an example, the equivalent N=16/5=3+1/5 in the fractional-N PLL frequency synthesizer of the present invention. That is to say, the ΔΣ modulator 250 outputs high and low level frequency signals with a fractional-N relationship according to the frequency at the frequency input terminal. The present invention uses the ΔΣ modulator 250 to replace the existing fractional-N PLL frequency synthesizer which must be completed by a ΔΣ modulator, a register, and a multi-mode frequency divider. Therefore, the fractional-N PLL frequency synthesizer of the present invention has the advantages of simple structure and easy design.

For a practical first example, for d=32, n=235,260,482, N=(2 ³² /235260482)=18.25622. When the reference frequency (Fref) is 4.92MHz, the voltage control frequency (Fvco) is 89.82MHz.

In order to increase the voltage-controlled frequency (Fvco), the present invention can provide a frequency divider with a single integer (N′, such as 33), connected between the voltage-controlled oscillator 240 and the ΔΣ modulator 250 in FIG. 5 . This single integer frequency divider can also be called a pre-scaler (Pre-Scaler). Taking the actual second example, when d=32, n=235, 260, 482, N=(2 ³² /235260482)=18.25622. When the reference frequency (Fref) is 4.92MHz, since the frequency division ratio of the pre-scaler (Pre-Scaler) is 33, the voltage control frequency can reach: Fvco=(33)*(2 ³² /235260482)*Fref(4.92 MHz) = 2.964Ghz.

Please refer to FIG. 6 , which is a graph showing the relationship between the voltage control signal and time output by the voltage control oscillator of the fractional-N phase-locked loop frequency synthesizer implemented by the first-order ΔΣ modulator. And FIG. 7, which is the FFT Spectrum of the Fast Fourier Transformation (FFT) of the first-order ΔΣ modulator in the fractional-N phase-locked loop frequency synthesizer implemented by the first-order ΔΣ modulator. It can be seen from Figure 6 that the voltage control signal output by the voltage-controlled oscillator will generate a ripple (Ripple) in a steady state. This phenomenon can be explained by the first-order ΔΣ modulator represented in Table 1. It can be seen from Table 1 that due to n=5, d=4, with 16 frequencies as a cycle, the first trigger of the overflow output terminal is generated when four input frequencies pass through, while the second to fifth triggers only pass through three frequencies, so periodically. Therefore, it will cause the voltage control signal to oscillate back and forth near the steady state. Furthermore, it can be seen from the frequency spectrum in FIG. 7 that the first-order ΔΣ modulator will generate unwanted spurs (Spurs) at high frequencies.

In order to reduce the surge (Spurs), the present invention can be implemented using a second-order ΔΣ modulator, please refer to FIG. 8 , which is a schematic diagram of a discrete time (Discrete Time) function of the second-order ΔΣ modulator. This second-order ΔΣ modulator is realized by cascading multiple adders into a single loop. This second-order ΔΣ modulator has four gain units a, b, c, and e, which are generally set to 1. Further, the quantization noise can be adjusted appropriately by adjusting the values of a, b, c, and e shape (quantization noise shape), without affecting the desired score relationship, preferably, the gain values of a, b, c, e are properly selected as the power of 2 relationship, such as 1/2, 1/ 4. 1/8... In terms of digital domain circuit design, power-of-two circuits can be implemented with shift registers, so the circuit complexity can be greatly simplified, and the desired quantization noise shape can be obtained. The second-order ΔΣ modulator can select the output terminal of the first comparator 252 or the output terminal of the second comparator 254 of the last stage as the overflow output terminal. Wherein, the first comparator 252 bits are on the output feedback path, and its threshold value is the maximum value that the second-order ΔΣ modulator can display; and the second comparator 254 bits are on the independent output path, and its threshold value The value can be set arbitrarily so that the duty cycle of the signal at the overflow output terminal is variable. Preferably, the value set by the second comparator is half of the maximum value that the second-order ΔΣ modulator can represent. Therefore, the first comparator 252 and the second comparator 254 will output the same phase and the same frequency signal, and the difference is that the duty cycle of the second comparator can reach about 50%. That is to say, when the frequency division ratio (N) is very large, the second-order ΔΣ modulator can still maintain a signal with a duty cycle of about 50%.

Furthermore, the biggest advantage of the second-order ΔΣ modulator is that it can maintain the original frequency division ratio and make the overflow output signal irregular. Taking the second-order ΔΣ modulator with d=4, n=5 as an example, every 16 frequencies as a cycle, the overflow output terminal can still be triggered five times, but the triggering time is not regular, that is to say, the triggering time is irregular. Randomize trigger time.

Please refer to FIG. 9 , which is a diagram showing the relationship between the voltage control signal output by the voltage control oscillator and the time of the fractional-N phase-locked loop frequency synthesizer implemented by the second-order ΔΣ modulator according to an embodiment of the present invention. And FIG. 10 , which is a spectrum diagram of the fast Fourier transform of the second-order ΔΣ modulator in the fractional-N PLL frequency synthesizer implemented by using the second-order ΔΣ modulator according to an embodiment of the present invention. It can be seen from FIG. 9 that the voltage control signal output by the voltage controlled oscillator does not generate ripples in a steady state. Furthermore, it can be seen from the frequency spectrum in FIG. 10 that the high-frequency spurs (Spurs) of the second-order ΔΣ modulator have been effectively reduced.

Therefore, the present invention proposes a fractional N phase-locked loop frequency synthesizer with simple structure, so that the circuit design can be significantly simplified, and effectively reduce the surge (Spurs), and the present invention can be based on the size of the ΔΣ modulator (d ) and the first output value (n) can determine the frequency division value (fraction N) of the fractional N PLL frequency synthesizer.

In summary, although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes without departing from the spirit and scope of the present invention. and retouching, so the scope of protection of the present invention should be defined by the scope of the appended patent application.

Claims (12)

1. mark N phase-locked loop frequency synthesizer is characterized in that it comprises:

One phase-frequency detector, can receive a reference signal with a reference frequency and an overflow output signal and can detect a phase place between this reference signal and this overflow output signal and the difference of a frequency after export a phase signal;

One charge pump is in order to receive this phase signal and to produce an output current that is relevant to this phase signal according to the size of this phase signal;

A voltage control signal is changed and exported to one loop filter after receiving this output current and mild this output current;

One voltage-controlled oscillator is in order to receive this voltage control signal and to have an output signal of a voltage controlled frequency according to this voltage control signal generation; And

One Δ ∑ modulator has the overflow output and an integer value input that can receive this output signal frequency input, exportable this overflow output signal, in order to determine the ratio between this voltage controlled frequency and this reference frequency.

2. mark N as claimed in claim 1 phase-locked loop frequency synthesizer is characterized in that, when the size of this Δ ∑ modulator was d position and this integer value input input n, this ratio was 2 ^d/ n, wherein d and n are all integer.

3. mark N as claimed in claim 1 phase-locked loop frequency synthesizer is characterized in that, this Δ ∑ modulator is a single order Δ ∑ modulator.

4. mark N as claimed in claim 3 phase-locked loop frequency synthesizer, it is characterized in that, this single order Δ ∑ modulator is made up of an accumulator, wherein, this accumulator can have a first input end, one second input and adds up output, add up the back in order to two numerical value and add up output output, and when two numerical value totallings of this first input end and this second input produce an overflow, export a pulse by this overflow output by this with this first input end and this second input; Wherein, this first input end is this integer value input, and this second input and the output of this totalling output interconnect.

5. mark N as claimed in claim 1 phase-locked loop frequency synthesizer is characterized in that, this Δ ∑ modulator is a second order Δ ∑ modulator.

6. mark N as claimed in claim 5 phase-locked loop frequency synthesizer is characterized in that, this overflow output signal of this second order Δ ∑ modulator output has an adjustable duty ratio.

7. mark N as claimed in claim 5 phase-locked loop frequency synthesizer is characterized in that, this second order Δ ∑ modulator has a plurality of gain units, quantize noise-shape that it is adjustable.

8. mark N phase-locked loop frequency synthesizer comprises:

One phase-frequency detector can receive a reference signal and an overflow output signal with a reference frequency, and can detect output one phase signal after the difference of a phase place between this reference signal and this overflow output signal and a frequency;

One charge pump is in order to receive this phase signal and to produce an output current that is relevant to this phase signal according to the size of this phase signal;

A voltage control signal is changed and exported to one loop filter after receiving this output current and mild this output current;

One voltage-controlled oscillator is in order to receive this voltage control signal and to have an output signal of a voltage controlled frequency according to this voltage control signal generation;

Prescaler, in order to this voltage controlled frequency divided by one first integer value after output one frequency reducing signal; And

One Δ ∑ modulator, have one and can receive the frequency input of this frequency reducing signal, the overflow output and the one second integer value input of exportable this overflow output signal, wherein, this mark N phase-locked loop frequency synthesizer determines a ratio between this voltage controlled frequency and this reference frequency according to this first integer value and this second integer value.

9. mark N as claimed in claim 8 phase-locked loop frequency synthesizer is characterized in that the size of this Δ ∑ modulator is the d position, and when this first integer value was m and this second integer value input input n, this ratio was m*2 ^d/ n.

10. mark N as claimed in claim 8 phase-locked loop frequency synthesizer is characterized in that, this Δ ∑ modulator is a single order Δ ∑ modulator.

11. mark N as claimed in claim 8 phase-locked loop frequency synthesizer is characterized in that, this Δ ∑ modulator is a second order Δ ∑ modulator.

12. mark N as claimed in claim 11 phase-locked loop frequency synthesizer is characterized in that, this overflow output signal of this second order Δ ∑ modulator output has an adjustable duty ratio.

Images