CN101110377A - Method for forming welding projection - Google Patents

Abstract

The invention provides a method for forming a welding lug. First, a substrate is provided, and an under bump metallurgy layer is formed on the surface of the substrate. Then, a patterned photoresist layer is formed on the surface of the under bump metallurgy layer, and the patterned photoresist layer includes at least one opening for exposing a portion of the under bump metallurgy layer. And forming a bottom plating layer on part of the surface of the under bump metal layer in the opening, and filling solder in the opening. Then, a photoresist stripping step is performed to remove the patterned photoresist layer, an etching process step is performed to etch a portion of the bottom plating layer and a portion of the under bump metallurgy layer by using the solder as a mask, and a reflow process is performed to form the solder bump.

Description

Method of forming solder bumps

【Technical field】

The present invention relates to a method for chip welding, in particular to a method for forming welding bumps.

【Background technique】

Flip-chip bonding (flip-chip) technology is currently a widely used electronic packaging technology. Different from the traditional packaging technology, in the flip-chip bonding technology, the die is no longer electrically connected to the package substrate by wire bonding, but reversed. It is electrically connected and mounted on the package substrate through solder bumps. Since the flip-chip bonding technology does not require the connection of gold wires, the size of the package can be greatly reduced and the speed of circuit transmission between the chip and the package substrate can be increased.

Please refer to FIG. 1 to FIG. 6 , which are schematic views of a conventional method for forming solder bumps 10 . As shown in FIG. 1 , firstly, a substrate 12 is provided, for example, a wafer with internal components and circuits completed. The surface of the substrate 12 includes a patterned passivation layer 14 , and the passivation layer 14 exposes a plurality of welding pads 16 . The pads 16 may be made of copper or aluminum, and are used to electrically connect internal circuits (not shown) formed in the substrate 12 and external circuits (not shown) on the package substrate.

As shown in FIG. 2 , several layers of stacked under bump metallurgy layer 18 (under bump metallurgy layer) are then formed by sputtering, deposition and etching processes, and cover each pad 16 and protective layer 14 . The UBM layer 18 may be sequentially composed of aluminum/nickel vanadium/copper or titanium/nickel vanadium/copper. As shown in FIG. 3 , a photoresist layer 20 is then formed on the entire surface of the substrate 12 to cover the passivation layer 14 and the UBM layer 18 . The material of the photoresist layer 20 can be dry film photoresist or liquid photoresist.

Next, as shown in FIG. 4 , exposure and development processes are performed to pattern the photoresist layer 20 to form a plurality of openings 22 in the photoresist layer 20 , correspondingly exposing the UBM layer 18 above each solder pad 16 . As shown in FIG. 5 , solder 24 is filled in each opening 22 by electroplating, wherein the solder 24 can be made of tin or copper. Then the photoresist layer 20 is stripped off. As shown in FIG. 6 , a reflow process is finally performed to form a plurality of solder bumps 10 on the corresponding solder pads 16 , completing the conventional method for forming solder bumps 10 .

However, in the prior art, when several openings 22 are formed in the photoresist layer 20, it will be impossible to be affected by factors such as the exposure light reflected by the UBM layer 18 and the developing solution and chemical solvent used in the developing process. Avoid corroding the bottom of the photoresist layer 20 at the part of each opening 22 connected to the UBM layer 18, resulting in an undercut phenomenon, forming undercut holes 26 of different sizes, and then causing the subsequent filling of the solder in the opening 22 24 not only covers the UBM layer 18 exposed in the opening 22 , but also fills the undercut hole 26 at the bottom of the etched photoresist layer 20 at the same time. Therefore, when the subsequent reflow process is performed, the solder 24 filled into the opening 22 will be due to the solder 24 filled in the undercut hole 26, resulting in a bottom area of the solder bump 10 that is larger than originally predetermined, and the size is different. First, it will affect the yield and stability of the entire process. Therefore, how to effectively control the size of the solder bumps during the reflow process is one of the current important issues.

【Content of invention】

The main purpose of the present invention is to provide a method for forming solder bumps to solve the above-mentioned problems in the prior art.

According to the foregoing objects of the present invention, the present invention provides a method of forming solder bumps, the method comprising the following steps. First, a substrate is provided, and at least one pad, a patterned protection layer covering the surface of the substrate and exposing part of the pad, and an under bump metal layer (UBM layer) are sequentially formed on the surface of the substrate. Then a patterned photoresist layer is formed on the surface of the UBM layer, and the patterned photoresist layer includes at least one opening for exposing part of the UBM layer. Then a foot plating is formed on the surface of the UBM layer in the opening, and solder is filled in the opening. A photoresist stripping step is then performed to remove the patterned photoresist layer, and an etching process step is performed, using the solder as a mask to etch part of the underplating layer and part of the UBM layer, followed by reflow. ) process to form the solder bump.

Since the present invention first utilizes the patterned photoresist layer to form an opening on the surface of the UBM layer and expose part of the UBM layer, and then forms an undercoating layer in the opening to cover part of the exposed UBM layer and the UBM layer. Undercut the hole, then fill the opening with solder and remove part of the underplating layer and part of the UBM layer not covered by the solder, so that the structure between the solder filled in the opening and the UBM layer can be effectively enhanced , so as to control the size of the bump when the subsequent reflow process is performed to form the solder bump, thereby improving the yield and stability of the process.

【Description of drawings】

1 to 6 are schematic diagrams of conventional methods for forming solder bumps.

7 to 12 are schematic diagrams of a method for forming solder bumps in an embodiment of the present invention.

【Detailed ways】

Please refer to FIG. 7 to FIG. 12 . FIG. 7 to FIG. 12 are schematic diagrams of a method for forming solder bumps according to a preferred embodiment of the present invention. As shown in FIG. 7 , a substrate 30, such as a wafer, is first provided, and a plurality of conductor structures, such as pads 32, are formed on the surface of the substrate 30, and its material is usually copper or aluminum for electrical connection formed in the substrate 30. The internal circuit (not shown in the figure) and the external circuit on the package substrate (not shown in the figure). Next, a patterned protective layer 34 is formed to cover the surface of the substrate 30 and expose part of the surface of each pad 32 to protect the internal circuits in the wafer (not shown in the figure). Then, processes such as sputtering, deposition and etching are performed to form an under bump metallurgy layer 36 (under bump metallurgy layer, referred to as abbreviation) covering the partially exposed pad 32 and the surface of the patterned protective layer 34. UBM layer). Wherein, the UBM layer 36 is generally composed of an adhesion layer, a barrier layer, and a wetting layer (not shown). The adhesive layer can provide good adhesion of the bonding pad 32 and the patterned protection layer 34 , and its material can be aluminum, titanium, chromium, titanium tungsten and so on. The barrier layer is used to prevent metal diffusion between the solder ball and the pad, and its material can be nickel vanadium, nickel and the like. The wetting layer provides good adhesion between the UBM layer 36 and the solder balls, and its material can be copper, molybdenum, platinum, and the like.

As shown in FIG. 8 , a patterned mask, such as a photoresist layer 38 , is then formed on the surface of the UBM layer 36 . Generally speaking, the photoresist layer 38 can be a liquid photoresist or a dry film photoresist. Then an exposure and development process is performed to correspondingly expose the UBM layer 36 above each solder pad 32 , and simultaneously form an opening 40 for subsequent solder bumps. In other words, the opening 40 is the bonding area between the subsequently filled solder and the UBM layer 36 , and its thickness is related to the height of the solder bump to be formed later. In addition, in this embodiment, the opening 40 is located right above the pad 32 . However, in other embodiments, the opening 40 can also be formed on the UBM layer 36 adjacent to the pad 32, so as to meet the need to change the contact due to the design of the contact configuration in the RDL (Redistribution Layer, RDL) process. s position.

Then, a footplating layer 42 , such as a copper metal layer, is formed on a portion of the UBM layer 36 in the opening 40 . As shown in FIG. 9 , the bottom plating layer 42 is formed on the bottom of the opening 40 of the photoresist layer 38 and covers the UBM layer 36 exposed to the opening 40 . Then, after filling the underplating layer 42 , an electroplating process is performed to fill the opening 40 with solder 44 and completely cover the underplating layer 42 .

When the openings 40 are formed in the photoresist layer 38, the exposure light reflected by the UBM layer 36 and the developer and chemical solvent used in the development process will inevitably corrode the openings 40. The bottom of the photoresist layer 38 at the portion connected to the UBM layer 36 causes an undercut phenomenon, forming undercut holes 45 of different sizes. Therefore, the present invention first fills the undercoating layer 42 at the bottom of the opening 40 to fill the undercut hole 45 at the bottom of the eroded photoresist layer 38, and then performs an electroplating process to fill the opening 40 with solder 44 to completely cover the bottom. Plating 42. Finally, using the control parameters of the etching selectivity ratio such as the material, thickness, and lattice structure of the undercoating layer 42 and the solder 44, the part of the undercoating layer 42 and part of the UBM layer 36 not covered by the solder 44 are removed until the patterned protection layer 34 surface, thereby effectively controlling the size of solder bumps formed by subsequent reflow.

As shown in FIG. 10 , a photoresist stripping step is then performed to remove the photoresist layer 38 . As shown in FIG. 11 , an etching process step is then performed, using the solder 44 as a mask to etch part of the underplating layer 42 and part of the UBM layer 36 until the surface of the patterned passivation layer 34 is reached. Finally, as shown in FIG. 12 , a reflow process is performed on the solder 44, so that the solder 44 becomes spherical due to surface tension, so as to form a solder bump on the corresponding solder pad 32 and the UBM layer 36. Block 46.

Compared with the prior art, the method for forming solder bumps in the present invention is to first use a patterned photoresist layer to form an opening on the surface of the UBM layer and expose part of the UBM layer, and then form a solder bump in the opening. An underplating layer and cover part of the exposed UBM layer and undercut hole, then fill the opening with solder and remove part of the underplating layer and part of the UBM layer not covered by the solder, so it can be used in subsequent When the reflow process is performed to form solder bumps, the size of the bumps is effectively controlled and the yield and stability of the process are improved.

Claims (9)

1. method that forms soldering projection, this method includes following steps: provide a substrate, and this substrate surface is formed with the step of a projection lower metal layer; Form a patterning photoresist layer on this projection lower metal layer surface, and this patterning photoresist layer includes at least one opening, in order to the step of this projection lower metal layer of expose portion; In this opening, insert the step of scolder; Carry out photoresistance and peel off, to remove the step of this patterning photoresist layer; Carry out the etch process step, utilize this scolder to be used as the step of shielding with this projection lower metal layer of etching part; And carry out back welding process to form the step of this soldering projection: it is characterized in that: it also is included in inserts the scolder step of a prime coat of the surface of the part projection lower metal layer in this opening formation before in the opening, also comprise in carrying out the etch process step and utilize this scolder to be used as this prime coat of shielding etching part.

2. the method for claim 1, it is characterized in that: aforementioned substrates is a wafer.

3. the method for claim 1; it is characterized in that: between the step that substrate surface forms a projection lower metal layer also is included in this substrate and this projection lower metal layer, be provided with at least one weld pad in addition and be electrically connected the circuit of being located in this substrate; aforementioned opening is positioned at this weld pad top, and patterning protective layer is covered in the step of this substrate surface and this weld pad of expose portion.

4. the method for claim 1, it is characterized in that: this prime coat is a copper metal layer.

5. the method for claim 1, it is characterized in that: this projection lower metal layer includes an adhesion layer, a barrier layer and a wettable layer.

6. the method for claim 1, it is characterized in that: this projection lower metal layer is to utilize sputter process to form.

7. the method for claim 1, it is characterized in that: this inserts the scolder step is to utilize a plating mode to reach.

8. lug manufacturing process, this lug manufacturing process includes: provide a wafer as substrate, and this substrate surface is formed with the projection lower metal layer, this projection lower metal layer includes an adhesion layer, a barrier layer and a wettable layer, include at least one weld pad in addition between this substrate and this projection lower metal layer and be electrically connected the circuit of being located in this substrate, and a patterning protective layer is covered in this substrate surface and this weld pad of expose portion; Form a patterning shielding on this projection lower metal layer surface, this patterning shield pack contains at least one opening above aforementioned weld pad, is used for this projection lower metal layer of expose portion; Part projection lower metal layer surface in this opening forms a prime coat; And in this opening, form a projection.

9. lug manufacturing process as claimed in claim 8 is characterized in that: the shielding of this patterning is a patterning photoresist layer, form this projection in this opening after, other includes a photoresistance strip step, in order to remove this patterning photoresist layer; After removing this patterning photoresist layer, other includes an etch process step, utilizes this projection to be used as shielding with this prime coat of etching part and this projection lower metal layer of part; After the etch process step, other comprises a back welding process.

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