CN101110584B - a driving circuit - Google Patents

Abstract

The invention discloses a driving circuit, which includes a voltage translation circuit and a driving voltage output circuit, and is characterized in that: the driving voltage output circuit includes a first input line connected to the input end of the voltage translation circuit, and a first input line connected to the output end The second input line is the power supply voltage input line; a P-type first MOS transistor and an N-type second MOS transistor are sequentially connected between the first input line and the second input line, and the source of the first MOS transistor is connected to the first MOS transistor. Two input lines, the source of the second MOS transistor is connected to the first input line, the gates of the first MOS transistor and the second MOS transistor are connected to the power supply voltage input line, and the drains are connected to each other as the drive voltage output terminal; A first current compensation circuit is connected in parallel with the first MOS transistor, and a second current compensation circuit is connected in parallel with the second MOS transistor. The invention realizes the linear output of the driving voltage within the range of 0-2VDD, and the withstand voltage of each tube does not exceed the power supply voltage VDD.

Description

a driving circuit

technical field

The invention relates to the design of a CMOS integrated circuit, in particular to a circuit structure of an output stage of a drive circuit whose drive voltage is 0 to 2 times the power supply voltage, which can realize the linear relationship between input and output. the

Background technique

In the prior art, common CMOS driving circuits are mainly used to improve the ability to drive loads, increase the driving current and so on. Among them, for voltage driving, the driving voltage range is usually within 0-VDD, and circuits capable of increasing the driving voltage are relatively rare. The charge pump structure is a structure that can reach twice the power supply voltage. It has two basic circuits: double voltage type and reverse voltage type, but it is relative to two states, that is, its output is high and low level, The driving voltage between high and low levels cannot be output. the

In order to obtain a higher output voltage, the MOS tube in the driving circuit is generally required to have a higher breakdown voltage, which in turn causes difficulties in the design of the CMOS circuit. the

Chinese invention patent application CN1440124A discloses a driving circuit, including a level shifting circuit (or voltage shifting circuit) and an amplitude amplifying circuit, through voltage shifting, under the control of the control circuit, can realize twice the driving voltage output, and Among them, the MOS tube can adopt components with lower breakdown voltage. However, such a driving circuit for PWM outputs a pulse signal whose voltage amplitude is doubled, and cannot realize continuous output of a driving voltage of 0-2VDD. the

Therefore, it can be considered that it is very difficult to realize a circuit that continuously outputs a driving voltage of 0-2VDD, especially for the design of the above-mentioned driving circuit that can be applied to the design of CMOS integrated circuits, which is a difficulty faced by this field. the

Contents of the invention

The purpose of the present invention is to provide a driving circuit capable of continuously outputting a driving voltage in the range of 0-2VDD, wherein the operating voltage of the power switching elements used does not exceed the power supply voltage VDD. the

In order to achieve the above object, the technical solution adopted by the present invention is: a driving circuit, comprising a voltage translation circuit and a driving voltage output circuit, the driving voltage output circuit comprising a first input line connected to the input end of the voltage translation circuit, A second input line connected to the output end of the voltage translation circuit, a power supply voltage input line; a P-type first MOS transistor and an N-type second MOS tube are sequentially connected between the first input line and the second input line The source of the first MOS transistor is connected to the second input line, the source of the second MOS transistor is connected to the first input line, the gates of the first MOS transistor and the second MOS transistor are connected to the power supply voltage input line, and the drains are common connected and used as a drive voltage output terminal; a first current compensation circuit is connected in parallel to the first MOS transistor, and a second current compensation circuit is connected in parallel to the second MOS transistor. The voltage translation circuit includes a translation circuit power line equivalent to twice the power supply voltage, the fifth, sixth, seventh, and eighth four P-type MOS tubes, and the source of the fifth MOS tube is connected to the translation circuit power supply line, the drain is connected to the source of the sixth MOS transistor, the drain of the sixth MOS transistor is connected to the source of the seventh MOS transistor, the drain of the seventh MOS transistor is connected to the source of the eighth MOS transistor, the eighth The drain of the MOS transistor is grounded; the gate and drain of the fifth, sixth, and seventh MOS transistors are connected to form a diode mode, and the gate of the eighth MOS transistor is connected to the first input line; the drain of the fifth MOS transistor The pole and the source of the sixth MOS transistor are commonly connected to the second input line to form the output end of the translation circuit. the

In the above technical solution, the traditional inverter structure is improved by using the working state that the N-type field effect transistor and the P-type field effect transistor are turned on at the same time, and the gate input is changed to the source input. The two sources are connected to the first input and the second input respectively, and the gates of the two tubes are connected to the power supply voltage VDD. In this way, the output range is 0-2VDD under the condition that the V _DS and V _GS of each tube do not exceed the power supply voltage. within the drive voltage. The current compensation circuit can ensure the linearity of the output driving voltage.

In the above technical solution, the first current compensation circuit is a P-type third MOS transistor, the source of the third MOS transistor is connected to the first input line, and the gate and drain are commonly connected to the output terminal; the second current The compensation circuit is an N-type fourth MOS transistor, the source of the fourth MOS transistor is connected to the second input line, and the gate and drain are both connected to the output terminal. the

In the above technical solution, the difference between the output voltage and the input voltage of the voltage translation circuit is equivalent to the power supply voltage. the

In the above technical solution, the purpose of the voltage shifting circuit is to obtain the second input voltage by shifting the first input voltage, which can also be called a bootstrap boost circuit. the

Due to the use of the above-mentioned technical solutions, the present invention has the following advantages compared with the prior art:

1. The present invention realizes the output of the drive voltage in the range of 0-2VDD through the design of the connection structure of a pair of P-type and N-type MOS tubes, and the cooperation with the voltage translation circuit, and the withstand voltage of each tube is different. It exceeds the power supply voltage VDD, so when used in CMOS circuit design, it can effectively improve the area efficiency;

2. The driving voltage output by the present invention can follow the input voltage and vary between 0 and 2VDD. By adjusting the parameters of the driving stage MOS tube, the swing and slope of the driving voltage can be adjusted arbitrarily. the

3. Due to the arrangement of the first and second current compensation circuits, the linear output of the driving voltage is guaranteed within the range of 0-2VDD. the

Description of drawings

Accompanying drawing 1 is the circuit block diagram of embodiment one of the present invention;

Accompanying drawing 2 is the structural schematic diagram of the voltage translation circuit in embodiment one;

Accompanying drawing 3 is the structural principle diagram of driving voltage output circuit in embodiment one;

Accompanying drawing 4 is the equivalent circuit diagram of a kind of working state in Fig. 3;

Accompanying drawing 5 is the equivalent circuit diagram of another kind of working state among Fig. 3;

Accompanying drawing 6 is the input and output schematic diagram of the voltage translation circuit of embodiment one;

Accompanying drawing 7 is the test diagram of the output result of the driving circuit in the first embodiment. the

Detailed ways

The present invention will be further described below in conjunction with accompanying drawing and embodiment:

Embodiment 1: Referring to Fig. 1 , a driving circuit is composed of a voltage translation circuit and a driving voltage output circuit. The input of the whole circuit is the first input line Vin_L, and the output is Vout. the

As shown in accompanying drawing 2, the voltage shifting circuit of this embodiment includes the shifting circuit power line VDDH equivalent to twice the power supply voltage VDD, the fifth, sixth, seventh, and eighth four P-type MOS tubes, the The source of the fifth MOS transistor M5 is connected to the translation circuit power line VDDH, the drain is connected to the source of the sixth MOS transistor M6, the drain of the sixth MOS transistor M6 is connected to the source of the seventh MOS transistor M7, and the seventh MOS The drain of the tube M7 is connected to the source of the eighth MOS tube M8, and the drain of the eighth MOS tube M8 is grounded; the gates and drains of the fifth, sixth, and seventh MOS tubes M5, M6, and M7 are connected , forming a diode mode, the gate of the eighth MOS transistor M8 is connected to the first input line Vin_L; the drain of the fifth MOS transistor M5 and the source of the sixth MOS transistor M6 are jointly connected to the second input line Vin_H, constituting the output of the translation circuit end. the

The voltage translation circuit can also be called a bootstrap boost circuit, and is used to generate the input value Vin_H required in FIG. 3 . the

By adjusting the width-to-length ratio of the four tubes, a suitable translation input voltage can be obtained; adjusting the width-to-length ratio of M5 and M8 can ensure that the translation is equal in different situations. The value of VDDH is 2VDD. Figure 6 shows the input voltage and the boosted output voltage. the

As shown in accompanying drawing 3, the driving voltage output circuit of this embodiment includes, the first input line Vin_L connected with the input terminal of the voltage translation circuit, the second input line Vin_H connected with the output terminal of the voltage translation circuit, the power supply voltage input line VDD; a P-type first MOS transistor M1 and an N-type second MOS transistor M2 are sequentially connected between the first input line and the second input line, and the source of the first MOS transistor M1 is connected to the second input Line Vin_H, the source of the second MOS transistor M2 is connected to the first input line Vin_L, the gates of the first MOS transistor M1 and the second MOS transistor M2 are connected to the power supply voltage input line VDD, and the drains are connected to each other and output as a driving voltage Terminal Vout; a first current compensation circuit is connected in parallel with the first MOS transistor M1, and a second current compensation circuit is connected in parallel with the second MOS transistor M2. the

In this embodiment, the first current compensation circuit is a P-type third MOS transistor M3, the source of the third MOS transistor M3 is connected to the second input line Vin_H, and the gate and drain are both connected to the output terminal Vout, forming Diode connection; the second current compensation circuit is an N-type fourth MOS transistor M4, the source of the fourth MOS transistor is connected to the first input line Vin_L, and the gate and drain are connected to the output terminal Vout to form a diode connection . the

The above drive voltage output circuit not only has an output swing of 0-2VDD, but also has a linear relationship between input and output. the

The above circuit structure ensures that there is always a path between Vin_L and Vin_H, and the path current remains unchanged, so that Vout changes linearly with changes in Vin_L and Vin_H. Wherein, due to the effect of the voltage translation circuit, Vin_H=Vin_L+VDD. Assuming that the two threshold voltages of the MOS tube are VL and VH respectively, the working process of the above circuit is explained as follows:

1. When the input is 0≤Vin_L≤VL, through the action of the voltage translation circuit, VDD≤Vin_H≤VL+VDD, at this time, M1 is turned off, M2 is turned on, and M3 and M2 form a path, forming an amplifier circuit in the linear region , because the voltage drop on M2 is very small, it does not reach the turn-on threshold of M4, and its equivalent circuit diagram is shown in Figure 4. With the increase of Vin_L, the output voltage Vout increases, the VGS of M2 decreases, and the current decreases. the

2. When VL≤Vin_L≤VH is input, after voltage translation, VDD+VL≤Vin_H≤VH+VDD, at this time, M1 and M2 are turned on at the same time, and M3 and M4 are used as compensation to ensure the channel current. Compensation, the linearity of the output can be guaranteed. the

3. When VH≤Vin_L≤VDD is input, after voltage translation, VDD+VH≤Vin_H≤2VDD, at this time, M1 is turned on, M2 is turned off, M1 and M4 form a path, and the currents are equal. Its equivalent circuit diagram is shown in Figure 5. the

Figure 7 shows the output of this drive circuit. Here, the range of Vin_L is 0-3.3v, and the range of Vin_H is 3.3v-6.6v. the

It can be seen from FIG. 7 that the circuit of this embodiment obtains a linear output within the range of 0 to 2VDD.

Claims (3)

1. drive circuit, comprise voltage translation circuit and driving voltage output circuit, it is characterized in that: described driving voltage output circuit comprises, first incoming line that is connected with the input of voltage translation circuit, second incoming line and the supply voltage incoming line that are connected with the output of voltage translation circuit; Between described first incoming line and second incoming line, connect first metal-oxide-semiconductor of P type and second metal-oxide-semiconductor of N type successively; The source electrode of described first metal-oxide-semiconductor connects described second incoming line, the source electrode of described second metal-oxide-semiconductor connects described first incoming line, the grid of described first metal-oxide-semiconductor and second metal-oxide-semiconductor is connected the supply voltage incoming line jointly, and the drain electrode of described first metal-oxide-semiconductor and second metal-oxide-semiconductor jointly is connected and as the driving voltage lead-out terminal; On described first metal-oxide-semiconductor, be parallel with first current compensation circuit, on described second metal-oxide-semiconductor, be parallel with second current compensation circuit;

Voltage translation circuit comprises the translation circuit power line VDDH that is equivalent to 2 times of supply voltage VDD, five, the metal-oxide-semiconductor of the 6th, the 7th, the 84 P type, the source electrode of described the 5th metal-oxide-semiconductor M5 connects translation circuit power line VDDH, drain electrode is connected with the source electrode of the 6th metal-oxide-semiconductor M6, the drain electrode of the 6th metal-oxide-semiconductor M6 is connected with the source electrode of the 7th metal-oxide-semiconductor M7, the drain electrode of the 7th metal-oxide-semiconductor M7 is connected with the source electrode of the 8th metal-oxide-semiconductor M8, the grounded drain of the 8th metal-oxide-semiconductor M8; The grid of metal-oxide-semiconductor is connected with drain electrode, the grid of the 6th metal-oxide-semiconductor is connected with drain electrode, the grid of the 7th metal-oxide-semiconductor is connected with drain electrode, constitutes the diode mode, and the grid of the 8th metal-oxide-semiconductor M8 connects the first incoming line Vin_L; The source electrode of the drain electrode of the 5th metal-oxide-semiconductor M5 and the 6th metal-oxide-semiconductor M6 is connected the second incoming line Vin_H jointly, constitutes the output of translation circuit.

2. drive circuit according to claim 1 is characterized in that: described first current compensation circuit is the 3rd metal-oxide-semiconductor of P type, and the source electrode of the 3rd metal-oxide-semiconductor connects second incoming line, and grid and drain electrode are connected to lead-out terminal jointly; Described second current compensation circuit is the 4th metal-oxide-semiconductor of N type, and the source electrode of the 4th metal-oxide-semiconductor connects first incoming line, and grid and drain electrode are connected to lead-out terminal jointly.

3. drive circuit according to claim 1 is characterized in that: the output voltage of described voltage translation circuit is suitable with described supply voltage with the difference of input voltage.

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