CN101154938A - Power on reset circuit - Google Patents

Abstract

The invention relates to a power supply starting reset circuit, which comprises a first reset circuit, a second reset circuit and a control circuit, wherein the first reset circuit comprises a first comparator used for outputting a system reset signal; and a second reset circuit for outputting a first reset signal to control the operation of the first reset circuit, so that the first reset circuit outputs the system reset signal when a first voltage is less than a first reference voltage.

Description

Power on reset circuit

technical field

The present invention relates to a power on reset circuit, in particular to a power on reset circuit with two reset circuits connected in series.

Background technique

A power-on reset (POR) circuit is generally used in semiconductor devices to avoid malfunctions when a power supply voltage is supplied to the semiconductor devices. When the semiconductor device is operated with a power supply voltage that has not reached a proper voltage level, erroneous operations may occur. Therefore, the reset signal (RESET) is used to reset the semiconductor circuit when the power supply voltage has been supplied but has not yet reached a predetermined voltage level, and the semiconductor device is not reset after the power supply voltage reaches the predetermined voltage level.

Contents of the invention

The present invention provides a power reset circuit, including a first reset circuit, including a first comparator for outputting a system reset signal; and a second reset circuit for outputting a first reset signal The signal is used to control the action of the first reset circuit, so that the first reset circuit outputs a system reset signal when a first voltage is lower than a first reference voltage.

The present invention also provides a power reset circuit, including a first reset circuit, configured to output a first reset signal when a divided voltage of a power supply voltage is less than a first reference voltage; and a second The reset circuit, connected in series with the first reset circuit, includes a first comparator controlled by the first reset signal to output a system reset signal for resetting an external circuit

The present invention also provides a power reset circuit, including a first reset circuit, including a first comparator with a first input terminal coupled to a first reference voltage, a second input terminal coupled to a The first node, and an output end for outputting a first reset signal; and a second reset circuit, including a second comparator having a second input end coupled to a second reference voltage, a second input The terminal is coupled to a second node, and an input terminal is used to output a system reset signal, wherein the output terminal of the first comparator is coupled to the second comparator.

The present invention also provides a power reset circuit, including a first reset circuit, including a first voltage supply unit, used to provide a first reference voltage; and a first comparator, including a first input terminal is coupled to the first reference voltage, a second input terminal is coupled to a first node in a first resistor string, and an output terminal is used to output a first reset signal, wherein the first resistor string is coupled to between a power supply voltage and a ground voltage; and a second reset circuit including a second voltage supply unit for providing a second reference voltage; and a second comparator including a first input terminal coupling connected to the second reference voltage, a second input terminal coupled to a second node in a second resistor string, and an output terminal used to output a system reset signal, wherein the output terminal of the first comparator is coupled to To the second resistor string, or a power supply terminal of the second comparator or the second input terminal of the second comparator.

The present invention also provides a voltage-initiated reset method, including outputting a first reset signal to a second reset circuit through a first reset circuit when a first voltage is lower than a first reference voltage and outputting a system reset signal according to the first reset signal through a comparator in a second reset circuit.

Description of drawings

FIG. 1 is a schematic diagram of a power on reset circuit of the present invention.

FIG. 2 is an embodiment of a power on reset circuit.

FIG. 3 is an output waveform diagram of a power on reset circuit.

FIG. 4 is another embodiment of the power on reset circuit in the present invention.

FIG. 5 is another embodiment of the power on reset circuit.

FIG. 6 is another output waveform diagram of a power reset circuit.

FIG. 7 is an embodiment of an electronic device.

Figure number:

2, 4, 4A, 4B, 4C: reset circuit;

10, 10A, 10B, 10C: Power start reset circuit;

20: core circuit; 30: electronic device;

V1, V2: voltage; Vdd: power supply voltage;

Vgs, Vbg: reference voltage; RS1; reset signal;

S _RESET : system reset signal; GND: ground voltage;

R1～R5: resistance; M1: MOS transistor;

COM1, COM2: Comparator; N1, N2: Node;

BRC: bandgap voltage reference circuit; AUX1: multiplexer.

Detailed ways

In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is specifically cited below, together with the accompanying drawings, as follows:

FIG. 1 is a schematic diagram of a power on reset circuit of the present invention. As shown in the figure, the power-on reset circuit 10 includes two series-connected reset circuits 2 and 4, wherein the reset circuit 2 is used when the voltage V1 (obtained by dividing the power supply voltage Vdd) is lower than one When the reference voltage Vgs is used, a reset signal RS1 is output, and the reset circuit 4 outputs a system reset signal S _RESET to an external circuit (not shown) when the voltage V2 is lower than the reference voltage Vbg. For example, the reference voltage Vgs is a threshold voltage of a MOS transistor M1 and is smaller than the reference voltage Vbg.

It should be noted that the reset signal RS1 from the reset circuit 2 controls the action of the comparator COM2 in the reset circuit 4 when the voltage V1 is lower than the reference voltage Vgs. When the voltage V1 exceeds the reference voltage Vbg, the reset circuit 2 stops outputting the reset signal RS1, and then the reset circuit 4 outputs a system reset according to the voltage V2 (obtained by dividing the power supply voltage Vdd) and the reference voltage Vbg Signal S _RESET . For example, if the voltage V2 is less than the reference voltage Vbg, the comparator COM2 will continue to output the system reset signal S _RESET , and when the voltage V2 is equal to (meet) the reference voltage Vbg, the comparator COM2 will stop outputting the system reset signal S _RESET . Therefore, the power-on reset circuit 10 can output the reset signal S _RESET to reset the external circuit when the divided voltage of the power voltage Vdd is lower than the reference voltage Vbg, so as to prevent the external circuit from operating at a lower power voltage. Down.

FIG. 2 is an embodiment of a power on reset circuit. As shown, the power on reset circuit 10A includes two serially connected reset circuits 2 and 4A. The reset circuit 2 includes resistors R1 - R3 , -MOS transistor M1 and a comparator COM1. The resistor R1 is coupled between the power supply voltage Vdd and the MOS transistor M1, and the MOS transistor M1 is coupled between the resistor R1 and a ground voltage GND, wherein the resistor R1 and the MOS transistor M1 form a voltage supply unit for providing the MOS transistor M1 The threshold voltage is used as the reference voltage Vgs.

The resistors R2 and R3 are connected in series, the resistor R2 is coupled between the power supply voltage Vdd and the node N1, and the resistor R3 is coupled between the ground voltage GND of the node N1, wherein the resistors R2-R3 form a voltage divider circuit (that is, a resistor string) to divide the power supply voltage Vdd to obtain the voltage V1 on the node N1. The comparator COM1 has two input terminals respectively coupled to the reference voltage Vgs and the voltage V1 on the node N1, two power supply terminals respectively coupled to the power supply voltage Vdd and the ground voltage GND, and an output terminal coupled to the reset circuit 4A. Comparator in COM2. For example, the MOS transistor M1 can be replaced by other types of transistors, such as BJTs, Junction Field Effect Transistors (FETs), . . . and so on.

The reset circuit 4A includes resistors R4 and R5, a bandgap voltage reference circuit (bandgapreference circuit) BRC, and a comparator COM2. The bandgap voltage reference circuit BRC is used to provide a reference voltage Vbg higher than the reference voltage Vgs to the comparator COM2. The resistors R4 and R5 are connected in series, the resistor R4 is coupled between the power supply voltage Vdd and the node N2, and the resistor R5 is coupled between the node Vdd and the ground voltage GND, and the resistors R4-R5 form a voltage divider circuit (that is, another A resistor string) is used to divide the power supply voltage Vdd so as to obtain the voltage V2 on the node N2.

The comparator COM2 includes two input terminals respectively coupled to the reference voltage Vbg and the voltage V2 on the node N2, a first power supply terminal coupled to the output terminal of the comparator COM1, a second power supply terminal coupled to the ground voltage GND and An output terminal is used for outputting a system reset signal S _RESET .

The operation of the power on reset circuit 10A is described below with reference to FIG. 3 . At time T1, the voltage V1 is lower than the reference voltage Vgs, so the comparator will lower its output terminal to the ground voltage GND, that is, the comparator COM1 outputs the reset signal RS1 to the comparator COM2. When the reset signal RS1 is applied to the first power terminal of the comparator COM2, even if the voltage V2 exceeds the reference voltage Vbg provided by the bandgap voltage reference circuit BRC, the comparator COM2 will still pull its output terminal down to Ground voltage GND. In other words, the system reset signal S _RESET (with a low logic level) is output to an external circuit (not shown).

At time T2, since the voltage V1 is still lower than the reference voltage Vgs, the comparator COM1 will continue to output the reset signal RS1, that is, the output terminal of the comparator COM2 will be pulled down to the ground voltage GND, so that the comparator COM2 will not matter whether the voltage V2 at this time Why, the system reset signal S _RESET is still output.

At time T3, since the voltage V1 exceeds the reference voltage Vgs, the output terminal of the comparator COM1 will be pulled up to the power supply voltage Vdd, that is, the comparator COM1 will stop outputting the reset signal RS1 at this time. Since the first power terminal of the comparator COM2 is pulled up to the power voltage Vdd, the comparator COM2 outputs the system reset signal S _RESET according to the voltage V2 and the reference voltage Vbg. Since the voltage V2 is less than the reference voltage Vbg, the output terminal of the comparator COM2 will continue to be pulled down to the ground voltage GND as the system reset signal S _RESET .

At time T4, since the voltage V2 exceeds the reference voltage Vbg, the output terminal of the comparator COM2 is pulled up to the power supply voltage Vdd, that is, the comparator COM2 stops outputting the system reset signal S _RESET .

In short, when the voltage V1 is lower than the reference voltage Vgs, the reset circuit 2 outputs the reset signal RS1 so that the comparator COM2 in the reset circuit 4A outputs the system reset signal S _RESET . When the voltage V1 exceeds the reference voltage Vgs, the reset circuit 4A outputs a system reset signal S _RESET according to the voltage V2 and the reference voltage Vbg. If the voltage V2 is lower than the reference voltage Vbg at this time, the comparator COM2 continues to output the system reset signal S _RESET ; otherwise, the comparator COM2 stops outputting the system reset signal S _RESET .

In other words, by selecting appropriate resistors R1-R5, when the reference voltage Vbg exceeds the voltage V2 (namely, the time T1), the voltage V1 can be smaller than the reference voltage Vgs, so that the power start-reset circuit 10A can be correctly set at the time T1-T4. Output system reset signal S _RESET to reset the external circuit.

FIG. 4 is another embodiment of the power on reset circuit in the present invention. As shown in the figure, the power start and reset circuit 10B is similar to the power start and reset circuit 10A shown in FIG. The first power terminal connected to the multiplexer AUX1 is not the first power terminal of the comparator COM2 in the reset circuit 4A. The multiplexer AUX1 includes a first input terminal coupled to the node N2, a second input terminal coupled to the ground voltage GND, an output terminal coupled to an input terminal of the comparator COM2, and a control terminal coupled to the Reset signal RS1 at the output of comparator COM1. The structures and connections of other elements in the reset circuit and the reset circuit 2 are similar to those shown in FIG. 2 , and will not be repeated here.

The operation of the power on reset circuit 10B is described below with reference to FIG. 3 . At time T1, since the voltage V1 is lower than the reference voltage Vgs, the output terminal of the comparator COM1 is pulled down to the ground voltage GND, that is, the reset signal RS1 is output to the reset circuit 4B. When the reset signal RS1 is applied to the control terminal of the multiplexer AUX1, the multiplexer AUX1 will pull down an input terminal of the comparator COM2 to the ground voltage GND. Therefore, no matter whether the voltage V2 exceeds the reference voltage Vbg of the bandgap voltage reference circuit, the output terminal of the comparator COM2 will be pulled down to the ground voltage GND. In other words, the system reset signal S _RESET (with a low logic level) is output to an external circuit (not shown).

At time T2, since the voltage V1 is still lower than the reference voltage Vgs, the comparator COM1 will continue to output the reset signal RS1, that is, the first power terminal of the comparator COM2 is pulled down to the ground voltage GND, so that the output system of the comparator COM2 resets. Set signal S _RESET .

At time T3, since the voltage V1 exceeds the reference voltage Vgs, the first power terminal of the comparator COM2 is pulled up to the ground voltage GND, that is, the comparator COM1 stops outputting the reset signal RS1 at this time. Therefore, the multiplexer AUX1 couples the voltage V2 on the node N2 to the positive input terminal of the comparator COM2. Since the voltage V2 is lower than the reference voltage Vbg, the output terminal of the comparator COM2 will continue to pull down to the ground voltage GND as the system reset signal S _RESET .

At time T4, since the voltage V2 exceeds the reference voltage Vbg, the output terminal of the comparator COM2 is pulled up to the power supply voltage Vdd, that is, the comparator COM2 stops outputting the system reset signal S _RESET at this time.

FIG. 5 is another embodiment of the power on reset circuit. As shown in the figure, the power on reset circuit 10C is similar to the power on reset circuit 10A shown in FIG. Instead of the first power terminal of the comparator COM2 in the reset circuit 4C. The structures and connections of other components in the reset circuit and the reset circuit 2 are similar to those shown in FIG. 2 , and will not be repeated here.

The operation of the power on reset circuit 10C is described below with reference to FIG. 6 . As shown in the figure, at the time T1, since the voltage V1 is lower than the reference voltage Vgs, the output terminal of the comparator COM1 is pulled down to the ground voltage GND, that is, the reset signal RS1 is output to the reset circuit 4C. When the reset signal RS1 is applied to the resistor R4, both the resistors R4 and R5 are coupled to the ground voltage GND, so the voltage V2 of the node N2 is pulled down to the ground voltage GND. Therefore, the voltage V2 will be lower than the reference voltage Vbg of the reference circuit, so the output terminal of the comparator COM2 will be pulled down to the ground voltage GND, and output to the external circuit as the system reset signal S _RESET .

At time T2, since the voltage V1 is still lower than the reference voltage Vgs, the comparator COM1 will continue to output the reset signal RS1, that is, the voltage V2 on the node N2 will also be pulled down to the ground voltage GND, so that the comparator COM2 will continue to output the reset signal RS1. The system reset signal S _RESET with a low logic level.

At time T3, since the voltage V1 exceeds the reference voltage Vgs, the output terminal of the comparator COM1 is pulled up to the power supply voltage Vdd, that is, the comparator COM1 stops outputting the reset signal RS1 at this time. Therefore, the multiplexer AUX1 couples the voltage V2 on the node N2 to the positive input terminal of the comparator COM2. Since the voltage V2 is lower than the reference voltage Vbg, the output terminal of the comparator COM2 will continue to pull down to the ground voltage GND as the system reset signal S _RESET .

At time T4, since the voltage V2 exceeds the reference voltage Vbg, the output terminal of the comparator COM2 is pulled up to the power supply voltage Vdd, that is, the comparator COM2 stops outputting the system reset signal S _RESET at this time.

FIG. 7 is an embodiment of an electronic device. As shown in the figure, the electronic device 30 includes a power start and reset circuit 10 / 10A / 10B / 10C and a core circuit 20 . For example, the power start and reset circuits 10 and 10A/10B/10C are used to provide the system reset signal S _RESET to reset the core circuit 20 when the power is turned on, so as to prevent the core circuit 20 from operating at a lower power supply Voltage.

The power onset and reset circuits 10 and 10A-10C in the embodiment of the present invention can be used as necessary functional components for an integrated circuit, such as data converters, phase-locked loops, oscillators, power management circuits, random access Memory, flash memory, microprocessor unit, digital signal processor, microcontroller, central processing unit, microprocessor or electronic devices such as digital cameras, portable DVDs, televisions, car monitors, PDAs, notebook computers, Mobile phones, display devices...etc.

The present invention also provides a voltage start reset method to prevent the core circuit 20 from operating at a lower power supply voltage.

In this voltage-initiated reset method, when the voltage V1 obtained by dividing the power supply voltage Vdd is lower than the reference voltage Vgs, the reset circuit 2 will output a reset signal RS1, and the reset circuit 4 will output a reset signal RS1 at the voltage V2 When it is lower than the reference voltage Vbg, a system reset signal S _RESET is generated to reset an external circuit. For example, the reference voltage Vgs is a threshold voltage of a MOS transistor and is smaller than the reference voltage Vbg.

When the voltage V1 exceeds the reference voltage Vgs, the reset circuit 2 stops outputting the reset signal RS1, and the reset circuit 4 then outputs a system reset according to the voltage V2 obtained by dividing the power supply voltage Vdd and the reference voltage Vbg. Signal S _RESET . For example, if the voltage V2 is lower than the reference voltage Vbg, the comparator COM2 will continue to output the system reset signal S _RESET , and when the voltage V2 exceeds the reference voltage Vbg, the comparator COM2 will stop outputting the system reset signal S _RESET . Therefore, when the power supply voltage Vdd is lower than the reference voltage Vbg, the power start reset circuit 10 can output the system reset signal S _RESET to reset the external circuit, so as to prevent the core circuit from operating at a lower working voltage.

For example, as shown in FIG. 2 , when the voltage V1 is lower than the reference voltage Vgs, the output terminal of the comparator COM1 is pulled down to the ground voltage GND, that is, the reset signal RS1 is output to the comparator COM2 . When the reset signal RS1 is applied to the comparator COM2, no matter what the voltage V2 is, the output terminal of the comparator COM2 will be pulled down to the ground voltage GND, that is, the system reset signal S _RESET is output to an external circuit (not shown). When the voltage V1 exceeds the reference voltage Vgs, the output terminal of the comparator COM1 is pulled up to the power supply voltage Vdd, that is, the comparator COM1 stops outputting the reset signal RS1 at this time. Since the first power terminal of the comparator COM2 is pulled up to the power voltage Vdd, the comparator COM2 outputs the system reset signal S _RESET according to the voltage V2 and the reference voltage Vbg. If the voltage V2 is lower than the reference voltage Vbg, the output terminal of the comparator COM2 will continue to be pulled down to the ground voltage GND as the system reset signal S _RESET . If the voltage V2 is not less than the reference voltage Vbg, the output terminal of the comparator COM2 will be pulled up to the power voltage Vdd, which means the comparator COM2 will stop outputting the system reset signal S _RESET .

In other words, as shown in FIG. 4 , the reset signal RS1 is applied to the control terminal of the multiplexer AUX1 (coupled between the node N2 and the positive input terminal of the comparator COM2 ). When the multiplexer AUX1 receives the reset signal RS1, an input end of the comparator COM2 is pulled down to the ground voltage GND, so that the output end of the comparator COM2 is pulled down to the ground voltage GND regardless of the voltage V2. In other words, the system reset signal S _RESET (with a low logic level) is output to the external circuit. When the voltage V1 exceeds the reference voltage Vgs, the output terminal of the comparator COM1 will be pulled up to the power supply voltage Vdd, that is, the comparator COM1 will stop outputting the reset signal RS1 at this time. Therefore, the multiplexer AUX1 couples the voltage V2 to the positive input terminal of the comparator COM2, so the comparator COM2 outputs the system reset signal S _RESET according to the voltage V2 and the reference voltage Vbg. If the voltage V2 is lower than the reference voltage Vbg, the output terminal of the comparator COM2 will continue to be pulled down to the ground voltage GND as the system reset signal S _RESET . If the voltage V2 is not less than the reference voltage Vbg, the output terminal of the comparator COM2 will be pulled up to the power voltage Vdd, which means the comparator COM2 will stop outputting the system reset signal S _RESET .

In other words, as shown in FIG. 5 and FIG. 6, when the voltage V1 is lower than the reference voltage Vgs, the output terminal of the comparator COM1 will be pulled down to the ground voltage GND, that is, the reset signal RS1 will be output to the resistor R4 ( coupled to the positive input of comparator COM2). Since both the resistors R4 and R5 are coupled to the ground voltage GND, the voltage V2 on the node N2 is pulled down to the ground voltage GND. Therefore, the voltage V2 will be lower than the reference voltage Vbg, so the output terminal of the comparator COM2 will be pulled down to the ground voltage GND as the system reset signal S _RESET . When the voltage V1 exceeds the reference voltage Vbg, the output terminal of the comparator COM1 will be pulled up to the power supply voltage Vdd, that is, the comparator COM1 will stop outputting the reset signal RS1 at this time. Therefore, one end of the resistor R4 is coupled to the power supply Vdd, so the voltage V2 on the node N2 can be regarded as a divided voltage of the power supply voltage Vdd. Therefore, the comparator COM2 outputs the system reset signal S _RESET according to the voltage V2 and the reference voltage Vbg. If the voltage V2 is lower than the reference voltage Vbg, the output terminal of the comparator COM2 will continue to be pulled down to the ground voltage GND as the system reset signal S _RESET . If the voltage V2 is not less than the reference voltage Vbg, the output terminal of the comparator COM2 will be pulled up to the power voltage Vdd, which means the comparator COM2 will stop outputting the system reset signal S _RESET .

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any skilled person may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be subject to what is defined by the claims.

Claims (23)

1. power-on reset circuits, described power-on reset circuits comprises:

One first reset circuit comprises that one first comparator is in order to export system's reset signal; And

One second reset circuit in order to export one first reset signal, so that control the action of above-mentioned first reset circuit, makes above-mentioned first reset circuit in one first voltage during less than one first reference voltage, output said system reset signal.

2. power-on reset circuits as claimed in claim 1, it is characterized in that, above-mentioned first reset signal is coupled to a power end of above-mentioned first comparator, makes above-mentioned first reset circuit in above-mentioned first voltage during less than above-mentioned first reference voltage, output said system reset signal.

3. power-on reset circuits as claimed in claim 1, it is characterized in that, above-mentioned first reset circuit comprises that more a multiplexer is coupled to an input of above-mentioned first comparator, when receiving above-mentioned first reset signal, above-mentioned input is pulled low to an earthed voltage, makes above-mentioned first reset circuit export the said system reset signal.

4. power-on reset circuits as claimed in claim 1, it is characterized in that, above-mentioned first reset signal is coupled to an input of above-mentioned first comparator by a voltage partial pressure unit, makes above-mentioned first reset circuit output said system reset signal when receiving above-mentioned first reset signal.

5. power-on reset circuits as claimed in claim 1, it is characterized in that, when above-mentioned second reset circuit surpasses above-mentioned first reference voltage in above-mentioned first voltage, stop to export above-mentioned first reset signal, and when one second voltage was lower than one second reference voltage, above-mentioned first comparator continued output said system reset signal.

6. power-on reset circuits as claimed in claim 5 is characterized in that, when above-mentioned second voltage surpassed above-mentioned second reference voltage, above-mentioned first comparator was in stopping to export the said system reset signal.

7. power-on reset circuits as claimed in claim 5 is characterized in that, above-mentioned first, second voltage obtains by a supply voltage being carried out a voltage dividing potential drop.

8. power-on reset circuits as claimed in claim 5 is characterized in that, above-mentioned first reference voltage is less than above-mentioned second reference voltage.

9. power-on reset circuits as claimed in claim 1 is characterized in that, above-mentioned second reset circuit more comprises a voltage feeding unit, in order to provide a transistorized critical voltage as above-mentioned first reference voltage.

10. power-on reset circuits as claimed in claim 5 is characterized in that, above-mentioned first reset circuit more comprises a band gap Voltage Reference voltage, in order to above-mentioned second reference voltage to be provided.

11. a power-on reset circuits, described power-on reset circuits comprises:

One first reset circuit, the dividing potential drop that is used to a supply voltage are exported one first reset signal during less than one first reference voltage; And

One second reset circuit is connected in series with above-mentioned first reset circuit, comprises that one first comparator is controlled by above-mentioned first reset signal, in order to export system replacement letter, so that reset an external circuit.

12. a power-on reset circuits, described power-on reset circuits comprises:

One first reset circuit comprise that one first comparator has that a first input end is coupled to one first reference voltage, one second input is coupled to a first node, and an output is in order to export one first reset signal; And

One second reset circuit, comprise that one second comparator has that one second input is coupled to one second reference voltage, one second input is coupled to a Section Point, and one input in order to export system's reset signal, the output of wherein above-mentioned first comparator is coupled to above-mentioned second comparator.

13. power-on reset circuits as claimed in claim 12 is characterized in that, above-mentioned second comparator comprises that more a power end is coupled to the output of above-mentioned first comparator.

14. power-on reset circuits as claimed in claim 12, it is characterized in that above-mentioned second reset circuit comprises that more a multiplexer has a first input end and is coupled to that above-mentioned Section Point, one second input are coupled to an earthed voltage, a control end is coupled to the output of above-mentioned first comparator and above-mentioned second input that an output is coupled to above-mentioned second comparator.

15. power-on reset circuits as claimed in claim 12, it is characterized in that, above-mentioned second reset circuit comprises that more one first resistance is coupled between the first input end and above-mentioned Section Point of above-mentioned multiplexer, and one second resistance is coupled between above-mentioned Section Point and the above-mentioned earthed voltage.

16. power-on reset circuits as claimed in claim 12, it is characterized in that, above-mentioned second reset circuit comprises that more one first resistance is coupled between the first input end and above-mentioned Section Point of above-mentioned first comparator, and one second resistance is coupled between above-mentioned Section Point and the above-mentioned earthed voltage.

17. power-on reset circuits as claimed in claim 12 is characterized in that, above-mentioned first reset circuit more comprises:

One the 3rd resistance is coupled between a supply voltage and the above-mentioned first node;

One the 4th resistance is coupled between above-mentioned first node and the above-mentioned earthed voltage; And

One voltage feeding unit is in order to provide above-mentioned first reference voltage.

18. power-on reset circuits as claimed in claim 17 is characterized in that, above-mentioned voltage feeding unit is in order to provide a transistorized critical voltage as above-mentioned first reference voltage.

19. power-on reset circuits as claimed in claim 12 is characterized in that, above-mentioned second reset circuit more comprises a band gap Voltage Reference voltage, in order to above-mentioned second reference voltage to be provided.

20. a power-on reset circuits, described power-on reset circuits comprises:

One first reset circuit comprises:

One first voltage feeding unit is in order to provide one first reference voltage; And

One first comparator, comprise that a first input end is coupled to above-mentioned first reference voltage, one second input is coupled to the first node in one first resistance string, and one output in order to export one first reset signal, wherein above-mentioned first resistance string is coupled between a supply voltage and the earthed voltage; And

One second reset circuit comprises:

One second voltage feeding unit is in order to provide one second reference voltage; And

One second comparator, comprise that a first input end is coupled to above-mentioned second reference voltage, one second input is coupled to the Section Point in one second resistance string, and one output in order to export system's reset signal, the output of wherein above-mentioned first comparator is coupled to a power end of above-mentioned second resistance string or above-mentioned second comparator or second input of above-mentioned second comparator.

21. power-on reset circuits as claimed in claim 20, it is characterized in that, above-mentioned first voltage provides the unit in order to providing a transistorized critical voltage as above-mentioned first reference voltage, and above-mentioned second voltage provides the unit to comprise a band gap reference circuits.

22. power-on reset circuits as claimed in claim 21, it is characterized in that, above-mentioned second reset circuit comprises that more a multiplexer has a first input end and is coupled to above-mentioned Section Point, one second input and is coupled to the output that above-mentioned earthed voltage, a control end are coupled to above-mentioned first comparator, and an output is coupled to second input of above-mentioned second comparator.

23. power-on reset circuits as claimed in claim 21, it is characterized in that, above-mentioned second resistance string comprises that one first resistance is coupled between the output and above-mentioned Section Point of above-mentioned first comparator, and one second resistance is coupled between above-mentioned Section Point and the above-mentioned earthed voltage.

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