CN101197354A - Stacked package structure - Google Patents

Abstract

A stacked packaging structure includes at least: a substrate having a first surface and a second surface opposite to each other; at least one chip disposed on the first surface of the substrate and electrically connected to the first surface of the substrate; a plurality of electrical connection elements disposed around the first surface of the substrate, wherein each electrical connection element is higher than the chip; and a sealing body covering the first surface of the substrate, the chip, and the electrical connection elements, wherein a surface of the sealing body exposes the top of each electrical connection element.

Description

Stacked package structure

technical field

The present invention relates to a system-in-package (System-In-Package; SIP) structure, in particular to a stacked (Stacked) package structure.

Background technique

The demand for low cost, small size and multi-function has become the main driving force for the development of the electronics industry. To achieve these goals, many advanced packaging technologies have been developed, such as flip chip, chip scale package (Chip Scale Package; CSP), wafer level packaging, and three-dimensional packaging (3DPackage) technologies. The three-dimensional packaging technology can integrate the chip, packaging and passive components into a package, and can become a solution for system packaging. The integration of the three-dimensional packaging technology can be side-by-side, stacked or a combination of the above two methods. Three-dimensional packaging has the advantages of small footprint, high performance and low cost

1 to 3 are process cross-sectional views of a conventional package-on-package structure. When fabricating the existing stacked package structure 250 , usually the chip package structure 100 is provided first, wherein the chip package structure 100 is mostly a chip-scale package structure. The chip packaging structure 100 mainly includes a substrate 102 , a chip 104 , an encapsulant 108 and solder balls 110 , as shown in FIG. 1 . The chip 104 is bonded on the upper surface 112 of the substrate 102 and is electrically connected to the pads (not shown) on the substrate 102 by wires 106 . The encapsulant 108 is formed on the upper surface 112 of the substrate 102 and completely covers the chip 104 , the wires 106 and the upper surface 112 of the substrate 102 . The solder balls 110 are disposed on the peripheral area of the lower surface 114 of the substrate 102 , wherein the solder balls 110 are electrically connected to the chip 104 .

Next, another chip package structure 200 is provided, the chip package structure 200 mainly includes a substrate 202 , a chip 204 , an encapsulant 208 and solder balls 210 , as shown in FIG. 2 . Wherein, the chip 204 is bonded on the upper surface 212 of the substrate 202 and is electrically connected to the pad (not shown) on the substrate 202 through the wire 206 . The encapsulant 208 is formed on a portion of the upper surface 212 of the substrate 202 and completely covers the chip 204 and the wires 206 . The solder balls 210 are disposed on the peripheral area of the lower surface 214 of the substrate 202 , wherein the solder balls 210 are electrically connected to the chip 204 . The upper surface 212 of the substrate 202 of the chip package structure 200 further has several bonding pads 216 , and the positions of these bonding pads 216 correspond to the solder balls 110 on the lower surface 114 of the substrate 102 .

Then, the chip package structure 100 is stacked on the chip package structure 200 , and the solder balls 110 of the chip package structure 100 are respectively located on the corresponding bonding pads 216 . Then reflow process is performed, so that the solder balls 110 of the chip package structure 100 can be bonded to the bonding pads 216 of the chip package structure 200 , thereby completing the fabrication of the stacked package structure 250 .

However, during the bonding process of the chip packaging structure 100 and the chip packaging structure 200 , the chip packaging structure 100 and the chip packaging structure 200 may warp, especially the chip packaging structure 100 . In addition, because the space between the substrate 102 of the chip packaging structure 100 and the substrate 202 of the chip packaging structure 200 is still quite large, and the junction between the chip packaging structure 100 and the chip packaging structure 200 falls in the peripheral area, a cold will be formed. Welding (ColdJoint), resulting in incomplete joint problems. This will seriously affect the reliability of the stacked packaging structure, and greatly reduce the yield rate of the packaging process, resulting in a significant increase in cost.

Contents of the invention

The purpose of the present invention is to provide a stacked packaging structure, which can reduce the area occupied by the packaging structure, thereby greatly reducing the area of the printed circuit board.

To achieve the above object, the present invention provides a stacked packaging structure, which at least includes a first chip packaging structure, a second chip packaging structure stacked on the first chip packaging structure, and several first connecting members and second connecting members. member. The first chip packaging structure at least includes: a first substrate having opposite first surfaces and second surfaces; at least one first chip configured on the first surface of the first substrate and connected to the first surface of the first substrate electrical connection; a plurality of first electrical connection elements, arranged around the first surface of the first substrate, wherein each first electrical connection element is higher than the first chip; a first encapsulant, coated on the first On the first surface of the substrate, the first chip, and the first electrical connection elements, wherein a surface of the first encapsulant exposes the top of each first electrical connection element; and several first connection members are arranged on On the second surface of the first substrate, the first chip and the first electrical connection elements are respectively electrically connected to the first connection members. The second chip packaging structure at least includes: a second substrate having opposite first and second surfaces; at least one second chip disposed on the first surface of the second substrate; and a second package covering the on the first surface of the second substrate and the second chip. The second connection members are disposed on the top of each first electrical connection element, and the second connection members are bonded to the second surface of the second substrate, wherein the second chip is electrically connected to the second connection members respectively.

According to the above object of the present invention, a package structure is provided, comprising at least: a substrate having opposite first surfaces and second surfaces; at least one chip configured on the first surface of the substrate and connected to the first surface of the substrate electrical connection; a plurality of electrical connection elements are arranged around the first surface of the substrate, wherein each electrical connection element is higher than the chip; and an encapsulant is coated on the first surface of the substrate, at least one chip, and On the electrical connection elements, one surface of the encapsulant exposes the top of each electrical connection element.

According to a preferred embodiment of the present invention, the above-mentioned first electrical connection element and the second electrical connection element can be wires, conductive studs, pins, electronic components or any combination of the above elements.

Compared with the prior art, one of the advantages of the present invention is that the package-on-package structure can reduce the area occupied by the package structure, so the area of the printed circuit board can be greatly reduced. Another advantage of the present invention is that it can integrate the connection relationship between the upper chip packaging structure and the lower chip packaging structure, and can effectively avoid warping of the chip packaging structure during bonding, and prevent the formation of false welds between the bonded chip packaging structures situation, which can greatly improve the yield rate of the stacked packaging process.

The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

Description of drawings

1 to 3 are process cross-sectional views of a conventional package-on-package structure.

4 to 9B are process cross-sectional views of a package-on-package structure according to the first preferred embodiment of the present invention.

10A and 10B are cross-sectional views of a package-on-package structure according to a second preferred embodiment of the present invention.

11A and 11B are cross-sectional views of a package-on-package structure according to a third preferred embodiment of the present invention.

12A is a cross-sectional view of a substrate of a package-on-package structure according to a fourth preferred embodiment of the present invention.

12B and 12C are cross-sectional views of a package-on-package structure according to a fourth preferred embodiment of the present invention.

Detailed ways

Relevant detailed description and technical contents of the present invention are as follows now in conjunction with the accompanying drawings:

4 to 9B are process cross-sectional views of a package-on-package structure according to a preferred embodiment of the present invention, and please also refer to FIG. 12A . When fabricating the stacked package structure of the present invention, first fabricate the chip package structure 324a, such as the structure shown in FIG. 8 . When fabricating the chip package structure 324a, the substrate 300a or the substrate 300b is provided first, wherein the substrate 300a or the substrate 300b may be a printed circuit board (PCB). The substrate 300a has an opposite surface 326a and a surface 328a, and the substrate 300b has an opposite surface 326b and a surface 328b. It should be noted that when the substrate 300b is provided by the supplier, several electrical connection elements 312d have been provided on the surface 326b, and the electrical connection elements 312d are preferably arranged around the substrate 326b, as shown in FIG. 12A; and the two opposite surfaces 326a and 328a of the substrate 300a are not provided with any components, as shown in FIG. 4 . In this embodiment, the chip packaging structure 324a is fabricated on the substrate 300a.

Next, the chip structure 308 is bonded on the central area of the surface 326a of the substrate 300a, and then wires 316 are formed to connect the chip structure 308 and the pads (not shown) on the surface 326a of the substrate 300a by, for example, wire bonding, so that the chip The structure 308 is electrically connected to the substrate 300a. And bond required passive elements 310 on the surface 326a of the substrate 300a around the chip structure 308 according to requirements, wherein the passive elements 310 may be resistors, inductors or capacitors. In this embodiment, the chip structure 308 includes a multi-chip structure of the chip 302 and the chip 306, wherein the chip 302 and the chip 306 can be bonded by an adhesive layer 304, and the material of the adhesive layer 304 can be epoxy resin (Epoxy). However, it should be noted that the chip structure of the present invention can also be a single chip. A plurality of electrical connection elements 312a are then formed on the peripheral area of the surface 326a of the substrate 300a, wherein the electrical connection elements 312a are preferably located at the periphery of the chip structure 308 and the passive element 310, as shown in FIG. 5 . The height of these electrical connection elements 312 a must be higher than that of the chip structure 308 . The electrical connection element 312a of this embodiment is a wire (Wires).

However, in other embodiments of the present invention, other different types of electrical connection elements can be used, such as the electrical connection element 312b shown in FIG. 10A, the electrical connection element 312c shown in FIG. The electrical connection elements 312d, wherein the electrical connection elements 312b are conductive studs (Conductive Studs), the electrical connection elements 312c are electronic components (Electronic Components), such as passive components, and the electrical connection elements 312d are pins (Pins). In addition, it should be noted that the electrical connection elements of the stacked package structure of the present invention may also be any combination of various electrical connection elements of the above embodiments, such as the chip package structure 324c shown in FIG. 11A . In the present invention, the material of the electrical connection element 312 a , the electrical connection element 312 b , and the electrical connection element 312 d may be gold, aluminum, copper, tin, and alloys of the above materials. In addition, the electrical connection element 312a, the electrical connection element 312b, the electrical connection element 312c, and the electrical connection element 312d can be mounted on the surface 326a of the substrate 300a by using solder or solder alloy and other attachment materials.

Next, the sealing material layer 317 is formed to cover the surface 326a of the substrate 300a by, for example, sealing or coating, and covers the chip structure 308, the wires 316, the passive components 310 and the surface 326a of the substrate 300a. The electrical connection element 312a is shown in FIG. 6 . Then form several connection members, such as solder balls 320, bonded on the peripheral area of the surface 328a of the substrate 300a, and preferably form a heat sink 330 on the central area of the surface 328a of the substrate 300a, to facilitate the element to dissipate heat, as shown in the figure 7C. Wherein, the chip structure 308 and the electrical connection element 312 a are respectively electrically connected to the solder balls 320 . Subsequently, the sealing material layer 317 is ground mechanically or chemically to remove part of the sealing material layer 317 until the top 314a of each electrical connection element 312a is exposed to form a sealing body 318, such as Figure 7A shows.

After the encapsulant 318 is formed, a plurality of connection members, such as solder balls 322a, are formed and respectively bonded to the tops 314a of the electrical connection elements 312a to complete the chip package structure 324a, as shown in FIG. 7B . Wherein, direct ball attach, screen printing, electroplating or electroless plating can be used to manufacture the connecting solder balls 332a.

Next, chip package structure 420a may be fabricated in a manner similar to chip package structure 324a. The chip package structure 420a is mainly composed of the substrate 400, the chip structure 408, and the electrical connection element 412a. The substrate 400 has opposite surfaces 422 and 424 . First bond the chip structure 408 on the central area of the surface 422 of the substrate 400, and then use, for example, wire bonding to form wires 416 to connect the chip structure 408 and the pads (not shown) on the surface 422 of the substrate 400, so that the chip The structure 408 is electrically connected to the substrate 400 . In this embodiment, the chip structure 408 includes a multi-chip structure of a chip 402 and a chip 406 , wherein the chip 402 and the chip 406 can be bonded by an adhesive layer 404 , and the material of the adhesive layer 404 can be epoxy resin. It should be noted that the chip structure of the present invention can also be a single chip. Next, several electrical connection elements 412 a are formed on the peripheral area of the surface 422 of the substrate 400 . In an embodiment of the present invention, required passive elements 410 may be bonded on the surface 422 of the substrate 400 around the chip structure 408 according to element requirements, wherein the passive elements 410 may be resistors, inductors or capacitors. The electrical connection element 412a is preferably located on the periphery of the chip structure 408 and the passive element 410, and the height of the electrical connection element 412a must be higher than that of the chip structure 408, as shown in FIG. 9A. The electrical connection element 412a in this embodiment is a wire. However, the chip package structure 420a may also use other different types of electrical connection elements, such as conductive pillars, electronic elements, leads, or any combination of the above-mentioned various electrical connection elements. The material of the electrical connection elements 412a can be gold, aluminum, copper, tin, and alloys of the above materials, and the electrical connection elements 412a can be mounted on the surface 422 of the substrate 400 using solder or solder alloys and other attachment materials. Next, a sealing material layer (not shown) is coated on the surface 422 of the substrate 400, and covers the chip structure 408, the wire 416, the passive element 410 and the electrical connection element 412a on the surface 422 of the substrate 400. . Then use mechanical grinding or chemical grinding to remove part of the encapsulant material layer until the top 414a of each electrical connection element 412a is exposed to form the encapsulant 418 and complete the chip packaging structure 420a. Then, the chip package structure 420a is stacked and bonded on the chip package structure 324a by soldering, so that the surface 424 of the substrate 400 is bonded to the connection solder ball 322a, and the chip structure 408 and the electrical connection element 412a are respectively electrically connected to the connection solder ball 322a. Sexual connection to complete the package-on-package structure, as shown in FIG. 9A. In the present invention, preferably, the chip package structure 324a has the same size as the chip package structure 420a.

In other embodiments of the present invention, other different types of electrical connection elements or a combination of these electrical connection elements can be used, such as the electrical connection element 412b of the chip package structure 420b (FIG. 10A), the chip package structure 420d (FIG. 12B) electrical connection element 412d, and the combination of the electrical connection element 412c and the electrical connection element 430 of the chip package structure 420c (FIG. The upper and lower ends of the electrical connection element 430 expose the contacts 434 at the top 432 of the electrical connection element 430 . In these embodiments, the encapsulant 418 exposes the top 414b of each electrical connection element 412b, the top 414c of each electrical connection element 412c, and the top 414d of each electrical connection element 412d. Therefore, in addition to the stacked structure shown in FIG. 9A , the package-on-package structure of the present invention may be the structure shown in FIG. 10A , FIG. 11A or FIG. 12B .

In addition, the package-on-package structure of the present invention can further arrange a chip 426 and a passive element 428 on the surface 424 of the substrate 400, use larger-sized connection solder balls 322b, and the height of the connection solder balls 322b is greater than the height of the chip 426, so as to Prevent the chip 426 and the passive element 428 from contacting the underlying chip package structure. At this time, the chip packaging structure 421a of FIG. 9B , the chip packaging structure 421b of FIG. 10B , the chip packaging structure 421c of FIG. 11B , and the chip packaging structure 421d of FIG. 12C can be formed.

In some embodiments of the present invention, a mold can be used to form the encapsulant, wherein the mold includes several columnar structures, and these columnar structures correspond to bonding pads on the substrate. After the encapsulant is injected into the mold and hardened, an encapsulant with a plurality of openings disposed therein exposing the bonding pads on the substrate can be formed. Then, conductive material can be injected into these openings, so that electrical connection elements can be formed in the openings respectively, so as to connect the exposed bonding pads on the substrate. In other embodiments of the present invention, a sealing material layer may be firstly formed on the substrate by using, for example, sealing or coating. Then, the sealing material layer is drilled to form a plurality of openings in the sealing material layer, wherein the openings expose the bonding pads on the substrate. Subsequently, conductive material is injected into these openings, so that electrical connection elements can be respectively formed in the openings to connect the exposed bonding pads on the substrate.

As can be seen from the above exemplary embodiments, since most of the space between the substrates of the two-chip packaging structure of the present invention is filled with the sealing material, the space between the two-chip packaging structures can be greatly reduced. When the chip package structure is stacked, warping of the chip package structure can be avoided, thereby preventing incomplete welding of the two chip package structures.

The above embodiments are only two-chip stacked package structures, but it should be noted that the stacked package structure of the present invention may also be a stacked package structure including more than two chips, and is not limited to the above-mentioned embodiments.

Compared with the prior art, one of the advantages of the present invention is that the package-on-package structure can reduce the area occupied by the package structure, so the area of the printed circuit board can be greatly reduced.

It can be seen from the above-mentioned preferred embodiments of the present invention that another advantage of the present invention is that it can integrate the connection relationship between the upper chip packaging structure and the lower chip packaging structure, and can effectively prevent the chip packaging structure from warping during bonding, and prevent The formation of virtual soldering between bonding chip packaging structures can greatly improve the yield rate of the stacked packaging process.

Claims (10)

1. A stacked package structure, comprising: A first chip package structure, comprising: A first substrate, having a first surface and a second surface opposite; at least one first chip configured on the first surface of the first substrate and electrically connected to the first surface of the first substrate; A first encapsulant covering the first surface of the first substrate and the at least one first chip; and A plurality of first connection members disposed on the second surface of the first substrate, wherein the at least one first chip is electrically connected to the plurality of first connection members; A second chip packaging structure stacked on the first chip packaging structure, the second chip packaging structure comprising: A second substrate has a first surface and a second surface opposite; at least one second chip disposed on the first surface of the second substrate; and a second package, coated on the first surface of the second substrate and the at least one second chip; and A plurality of second connection members are bonded to the second surface of the second substrate, wherein the at least one second chip is electrically connected to the plurality of second connection members; It is characterized in that: the first chip package structure includes a plurality of first electrical connection elements arranged around the first surface of the first substrate, each of the first electrical connection elements is higher than the The at least one first chip, the plurality of first electrical connection elements are electrically connected to the plurality of first connection members, the first encapsulant is coated on the first electrical connection elements, and A surface of the first encapsulant exposes the top of each first electrical connection element; the plurality of second connection members of the second chip packaging structure are arranged on each first electrical connection element on the top. 2. The package-on-package structure according to claim 1, wherein the plurality of first electrical connection elements and the plurality of second electrical connection elements are selected from wires, conductive columns, and guide pins. , electronic components, and any combination of the above components. 3. The package-on-package structure according to claim 1, wherein the second chip package structure further comprises a third chip disposed on the second surface of the second substrate, and each of the The height of the second connecting member is greater than that of the third chip. 4. The package-on-package structure of claim 1, wherein the second chip package structure further comprises a heat sink disposed on the second surface of the second substrate. 5. The package-on-package structure as claimed in claim 1, wherein the materials of the plurality of first electrical connection elements are selected from a group consisting of copper, aluminum, gold, tin and alloys thereof. 6. A packaging structure, comprising: A substrate having a first surface and a second surface opposite; at least one chip disposed on the first surface of the substrate and electrically connected to the first surface of the substrate; and a glue, coated on the first surface of the substrate and the at least one chip; It is characterized in that: the packaging structure further includes several electrical connection elements, the several electrical connection elements are arranged around the first surface of the substrate, each of the electrical connection elements is higher than the The at least one chip; the encapsulant is coated on the plurality of electrical connection elements, and a surface of the encapsulant exposes the top of each electrical connection element. 7 . The package structure according to claim 6 , wherein the plurality of electrical connection components are selected from a group consisting of wires, conductive posts, guide pins, electronic components, and any combination of the above components. 8. The package structure of claim 6, wherein the substrate further comprises a heat sink disposed on the second surface of the substrate. 9. The package structure as claimed in claim 6, wherein the materials of the plurality of electrical connection elements are selected from a group consisting of copper, aluminum, gold, tin and alloys thereof. 10. The package structure according to claim 6, further comprising an electrical component disposed on the package structure, the electrical component is electrically connected to the top ends of some of the plurality of electrical connection components. sexual connection.

Images