CN101217486B - A mobile Internet data load allocation method based on network processor - Google Patents

Abstract

The mobile Internet data load distribution method based on the network processor, firstly, the network processor is used as the realization platform, which can achieve gigabit wire-speed processing capability; The one-to-one correspondence between different users can be identified and distributed through the round-robin algorithm. The processing process is on the network processor IXP2400, for the CDMA2000 mobile communication system, firstly, the information used for load distribution is extracted according to the signaling interface A11 between the packet control function unit PCF and the packet data service node PDSN, that is, the International Mobile Subscriber Identity The information IMSI and universal routing encapsulate the GRE transmission identifier GRE Key, and then distribute the data flow on the data transmission interface A10 to different packet control function units PCF or PDSN according to different transmission identifiers GRE Key.

Description

Mobile internet data load distribution method based on network processor

technical field

The invention relates to a flow distribution method of a mobile communication system, in particular to a data load distribution method for mobile Internet such as CDMA2000 (Code Division Multiple Access 2000 mobile communication system), and belongs to the technical field of mobile communication networks.

Background technique

As a hot spot in recent years, the third-generation mobile communication system (3G) has attracted international attention, and will be one of the most important development directions in the field of communication in the early 21st century. Among them, CDMA2000, WCDMA and TD-SCDMA are three mainstream technology. As the key technology of broadband mobile network, CDMA technology has developed rapidly in the past few years. Moreover, with the continuous advancement of technology and the continuous decline of product prices, its application fields continue to expand. The advent of the 3G era is bound to be accompanied by a rapid increase in network transmission speed, which also leads to an increase in network traffic. However, for any kind of equipment in the network, the load it can bear is limited, and at the same time, its working efficiency varies greatly under different load conditions. If the traffic of a network device is always close to the maximum load, then its processing capacity will be greatly reduced, which may bring great delay. Traffic and efficiency are always a pair of contradictions. How to reasonably distribute huge traffic among different devices with limited loads through effective means, so that each device can play its best role has become a very difficult problem.

The load balancing algorithms used in the current network load distribution system mainly include: Round-Robin algorithm, Weighted Round Robin algorithm, Least Connections algorithm, Weighted Least Connections Algorithm, Destination Hashing Scheduling algorithm, Source Hashing Scheduling algorithm, Random algorithm, etc. In the CDMA2000 packet domain network, the data traffic is very large as stated above, which requires the network equipment we distribute to have fast data packet forwarding capabilities. It is based on this consideration that we choose INTEL IXP2400 as the shunt Due to its special hardware and software structure, it basically meets the performance index of actual network processing. At the same time, in view of the particularity of the special language for the NP hardware platform, we chose the round-robin algorithm as the basis of the system realization.

Contents of the invention

Technical problem: Aiming at the huge data traffic in the core network in the third generation mobile communication system, the purpose of the present invention is to provide a mobile Internet data load distribution method based on the network processor, which can be effectively processed by the fast forwarding capability of the network processor IXP2400 Large flow of data in the CDMA2000 core network.

Technical scheme: the CDMA2000 data load distribution method based on network processor of the present invention is by the analysis to CDMA2000 group domain network data packet and relevant agreement, finds that the GRE Key field of its data packet contains effective user information, and can be connected with by It establishes a one-to-one correspondence relationship with the user (identified by the International Mobile Subscriber Identity IMSI). Based on this discovery, the present invention realizes the reasonable distribution of users by shunting the GRE Key, so that the data of the same user is allocated to the same machine for processing, and the data between different users also achieves a certain degree of balance through the algorithm , so that subsequent network devices can complete tasks with maximum efficiency.

The processing procedure of the mobile Internet data load distribution method based on the network processor of the present invention is on the network processor IXP2400, aiming at the CDMA2000 mobile communication system, at first extract according to the signaling interface A11 between the packet control function unit PCF and the packet data service node PDSN Output the information for load distribution, that is, the international mobile subscriber identification information IMSI and the transmission identification GRE Key of the universal routing encapsulation GRE, and then distribute the data flow on the data transmission interface A10 to different group control functions according to different transmission identification GRE Keys Unit PCF or PDSN.

The network processor IXP2400 divides the 8 micro-engines provided by the IXP2400 into data packet receiving modules corresponding to No. 0 micro-engines, load distribution modules corresponding to No. 1, 2, 3 and 4 micro-engines, and queue management modules corresponding to No. The processing steps of No. 6 micro-engine, scheduling management module corresponding to No. 6 micro-engine, and data packet sending module corresponding to No. 7 micro-engine load distribution are:

Step 1: The data packet receiving module receives all data packets from the link of PCF and PDSN, and transmits them to the load distribution module sequentially in time,

Step 2: According to the IP header and port number, the load distribution module judges whether it is a signaling interface A11 data packet or a data transmission interface A10 data packet to process respectively,

a) If it is a signaling interface A11 data packet, extract its GRE Key and IMSI and fill in different destination host MAC addresses and IP addresses according to the GRE Key,

b) If it is a data packet of the data transmission interface A10, then obtain the corresponding transmission identifier GRE Key, and then also fill in different destination host MAC addresses and IP addresses according to the difference of the transmission identifier GREKey, thus ensuring that the signaling belonging to the same user The data of interface A11 and data transmission interface A10 are sent to the same PCF or PDSN, which is convenient for user confirmation;

Step 3: The load distribution module sequentially transmits the processed data packets to the queue management module, and sends them to the switch through the data packet sending module.

Beneficial effects: the present invention provides a network processor-based CDMA2000 data load distribution method. Because the core network of CDMA2000 aggregates packet data from multiple base stations, a large amount of traffic data will greatly increase the burden on forwarding equipment. The network processor-based CDMA2000 data load distribution system uses the fast forwarding capability of IXP2400 to extract user identification information IMSI according to the A11 signaling protocol between PCF and PDSN, and then distributes A10 data traffic to subsequent processing equipment. Effectively avoid data congestion, thereby improving the processing capacity of the system, and at the same time support the backend to perform additional operations on different users.

Description of drawings

The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

Fig. 1 is a schematic diagram of the CDMA2000-1X core network packet domain structure;

Figure 2 is the A10/A11 protocol stack model;

Figure 3 is a schematic diagram of the structure of the data processing module Dispatch Loop,

Figure 4 is a flow chart of data processing.

Detailed ways

The position of the equipment used in the present invention in the CDMA2000 packet domain network is shown in FIG. 1 .

As far as this system is concerned, the equipment and communication links we consider are PCF and PDSN equipment and the R-P link between them.

Packet Control Function (PCF) equipment is usually installed in the base station controller (BSC) as a wireless network equipment, or installed externally at the same site as the BSC, but it is a necessary functional unit for completing packet services. As an access device for wireless mobile users to access the Internet, the PDSN assumes the function of the data exchange server between the CDMA network and the Internet, and acts as a bridge in the network.

In addition, the interface between the PCF (RN) and the PDSN is the "RN-to-PDSN" interface, that is, the R-P interface. The R-P interface is the boundary between wireless processing and wired processing. The R-P interface includes two elements, the A11 interface and the A10 interface. They are all considered part of the A interface.

The R-P interface between the wireless access node and the PDSN is a standard interface between the PCF and the PDSN. The data packets we actually need to process are A10/A11, and its protocol stack model is shown in Figure 2. Among them, A10 bears user data, while A11 consists of some signaling. The specific method to distinguish between A11 signaling and A10 data is to look at the IP header. If the Protocol field in the IP header is GRE, then it is A10 data; if it is UDP, it is A11 signaling.

In IXP2400, the data packet is divided into two levels: data plane processing and control plane processing. The data packet processing on the data plane can be divided into several functional logic modules, that is, micro-modules, and similarly, the data packet processing on the control plane can also be divided into several functional modules, that is, core modules. The core module (Core Component) is only responsible for initializing and managing the memory resources occupied by the micro-module, managing table lookup structures such as routing tables, and handling a small amount of abnormal packets. A large number of data processing transactions are handed over to micro-modules with parallel advantages.

Software structure of the present invention:

1) The data packet receiving module in the micromodule receives the data packet from the link between PCF and PDSN, and then transmits it to the processing module MSF. The RX module wakes up a thread from thread_free_list. The thread obtains the RSW word storing the status information of the received packet, extracts the port number where the data packet arrives and the RBUF unit number and size where the data packet is stored. Based on the port number on which the packet arrived, the thread finds a path for code execution from the receiving context. The thread stores the data packet received in RBUF to DRAM. If the received mpacket is a start packet (SOP), a new memory buffer is allocated from buffer_free_list, and the relevant state information metatdata of the data packet is stored in SRAM. If the received mpacket is an end-of-packet (EOP), the first 8 bytes of the memory descriptor buffer descriptor are stored in the SRAM. The thread waits for the previous thread signal and all I/O initialization. When an mpacket has been stored in DRAM, the RBUF element is released, and the thread is rewritten back to the free list. If the mpacket is EOP, it means that a complete data packet has been received, and the thread writes the packet pointer (buffer handle) and descriptor ( buffer descriptor) information is written to the scratch ring, waiting for further processing. The thread waits for the completion of the scratch write, and at the same time waits for the MSF to receive the event signal.

2) Load distribution module. This module is the core of the system, and its main function is to decapsulate and classify Ethernet, and distinguish ARP data packets, A11 signaling (UDP data packets) and A10 data (GRE data packets). The ARP data packets are temporarily discarded, and the only data packets that need to be analyzed and intercepted are A10 and A11.

a) If it is UDP, judge whether it is A11 signaling according to the port number. If it is A11 signaling, extract its GRE Key and send it to the corresponding destination host according to the distribution algorithm; if it is other signaling, discard it directly .

b) If it is a GRE data packet, obtain the corresponding user session number (Key) and data packet sequence number (Sequence Number), and then perform distribution according to the key. This ensures that the A11 and A10 data belonging to the same user are sent to the same computer, which is convenient for user confirmation. Then pass this packet to the queue management module,

This processing module will also be introduced in detail later.

3) The queue management micro-module sends the micro-module to the switch, and finally the switch sends it to the destination host for further processing. The program first extracts the processed data packet dl_buffer_handle from the Scratch ring, reads the data status information, and obtains the data packet storage address; then segments the data packet into mpackets, writes them into TBUF, and sends them through the MSF state machine, and the data passes through the MSF -to-DRAM fast channel writes to the TBUF unit; finally writes the send control word TCW to the TBUF_Element_Control_# register to automatically enable TBUF, and then MSF starts to send mpackets.

In the micro-module of this system, data packet reception is designed in an independent micro-engine (No. 0 micro-engine) as a regular function. The functions of Ethernet unpacking/layer 3 protocol classification, storage of required information, shunting and other functions belong to the functional category of data processing, and the content of front and back operations are related. Therefore, they are divided into different sub-modules to form a functional pipeline, and put this pipeline into into 4 microengines (microengines 1-4) for concurrent execution. The queue management function is the realization of a complex queue control function, so it is put into a micro-engine (No. 5 micro-engine) for execution. Scheduling management is responsible for the function of flow control, which is put into No. 6 micro-engine for execution. Finally, the sending module is processed by only one micro-engine (No. 7 micro-engine) because it realizes OC48.

The resource allocation of the micro-engine system is shown in Table 1:

Table 1 Micro-engine system resource allocation table

As shown in Figure 3, the load distribution module is composed of Ethernet Decap/Classify (Ethernet decapsulation/classification), A11/10Decap/Classify (A11/A10 decapsulation/classification), Distribute (load distribution) and other parts. It is implemented in the form of Pipeline and runs on 4 micro-engines (2 micro-engines are selected from the two ME Clusters to make full use of two sets of Command Bus and S Push/Pull Bus). Each Thread on the microengine processes a Packet at a time, so that in the best case there will be 32 threads running in parallel to maximize the speed of packet data processing. The order of packets is guaranteed by the dl_Source and dl_Sink modules. Among them, the dl_source module takes the buffer handle and Metadata out of the Scratch ring and passes them into the Ethernet Decap/Classify submodule. The processing flow of the data packet is shown in Figure 4. According to the buffer handle, take out the IP packet header to judge the IP data protocol type. If it is a UDP packet, it may be A11 signaling. After judging that it is A11 signaling according to the port number, extract the corresponding imsi and key and store it in the corresponding sram address. After the storage is complete, discard the data packet; if it is a GRE packet, first extract the Grekey, then find out the corresponding storage location, extract the corresponding user Imsi information, divide the traffic according to the imsi, write different destination addresses in the IP header and then transmit Go to the next module. The dl_sink module writes the relevant information of the PacKet transmitted earlier into a specific Scratch ring, and hands the packet to the queue management module for processing. Each sub-module is introduced separately as follows:

1) dl_source scheduling ring source submodule

The dl_source sub-module is responsible for obtaining the post-transmission packet information sent from the data packet receiving module from the POS_RX_TO_PACKETDEALING_SCR_RING global Scratch ring. While obtaining the packet information, the order of packet arrival is guaranteed through the cooperation of dl_source and dl_sink and the mechanism of orderly thread execution. After entering the packet data processing module, the program calls the macro dl_source[DL_THREAD_ORDER, sig_mask] to start the receiving packet program of each thread in sequence. Then after entering the receiving loop loop, we call dl_sink[sig_mask, sig_scr_put, $wxfer] to send the processed packets to the queue management module in thread order, and then call dl_source[DL_THREAD_NO_ORDER, sig_mask] to schedule according to the thread Receive packet information out of order. Just continue to circulate successively so that the order of the arrival and transmission of the entire packet is consistent with the data packet receiving micromodule as a whole.

2) Ethernet Decap/Classify Ethernet decapsulation/classification

The Ethernet Decap/Classify module is responsible for removing the Layer 2 protocol header, classifying the data packets, and handing Pacek to different modules for processing according to the classification results.

3) A11/A10 Decap/Classify A11/A10 decapsulation/classification

Determine whether the data area is UDP or GRE data according to the Protocol field in the IP header. If it is UDP, judge whether it is A11 signaling or other signaling according to the port number, and discard it if it is other signaling; if it is A11 signaling, extract imsi and key in the corresponding field and store them in the corresponding continuous In the sram address of the sram address, when the storage is completed, the data packet is discarded. If it is GRE data, extract its GRE key and Sequence Number, and then enter the distribution module.

4) Distribute load distribution sub-module

Find its address in sram according to the GREkey of A10 data. Since the storage address of IMSI and key are continuous, you can find the corresponding IMSI by simple offset after finding the address of the key, and because IMSI and key are the same One-to-one correspondence, so each A10 data has its corresponding user IMSI information. In order to facilitate the follow-up processing, we assume that the data is distributed to three follow-up devices. For this purpose, the lower two digits of the IMSI value are used for judgment, which is divided into three cases: 00 (11), 01, and 10. According to different situations, modify the A10 data The IP header of the packet contains three different destination IP addresses. At the end of module processing, the data must be encapsulated by Ethernet. The program uses the next hop ID in the MetaData pointed to by the Buffer Handle as the MAC address or the index value of the ARP information table to find the corresponding layer 2 packet header information, encapsulate and transmit it. If there is no corresponding layer 2 information in the table, the packet is forwarded to the Xscale core by thread 0 of ME1. The program on the Xscale core generates a corresponding ARP request message for this packet, and creates an entry in the table when an ARP reply is received. If the next hop ID itself is -1, which is illegal, the program will think that the packet has been added with layer 2 header information and send it to the next sub-module.

5) dl_sink dispatching sub-module of ring sink

All the data in the data processing micro-module are finally sent to the queue management micro-module by the dl_sink sub-module. The wxfer transmission register in dl_sink[sig_mask, sig_scr_put, $wxfer] is responsible for storing the dl_buf_handle, dl_eop_buf_handle and Queue_Number required by the queue management module. The first two parameters are still the Buffer Handle of the transmitted data packet, and the queue number indicates that the data is The queue number in the assigned send queue. Through the scratch ring transmission mechanism between modules, it is sent to the POS_PACKETDEALING_TO_QM_SCR_RING global ring to realize the data transmission.

Claims (1)

1. A mobile internet data load distribution method based on network processor, it is characterized in that this distribution method is on network processor IXP2400, for CDMA2000 mobile communication system, at first according to grouping control function unit PCF and packet data service node PDSN The signaling interface A11 extracts the information used for load distribution, that is, the International Mobile Subscriber Identity Information IMSI and the transmission identifier GRE Key of the general routing encapsulation GRE, and then distributes the data traffic on the data transmission interface A10 according to different transmission identifiers GRE Key To different packet control functional units PCF or PDSN; The network processor IXP2400 divides the 8 micro-engines provided by the IXP2400 into data packet receiving modules corresponding to No. 0 micro-engines, load distribution modules corresponding to No. 1, 2, 3 and 4 micro-engines, and queue management modules corresponding to No. No. micro-engine, scheduling management module corresponds to No. 6 micro-engine, and data packet sending module corresponds to No. 7 micro-engine. The processing steps of load distribution are as follows: Step 1: The data packet receiving module receives all data packets from the link of PCF and PDSN, and transmits them to the load distribution module in turn, Step 2: According to the IP header and port number, the load distribution module judges whether it is a signaling interface A11 data packet or a data transmission interface A10 data packet to process respectively, a) If it is a signaling interface A11 data packet, extract its GRE Key and IMSI and fill in different destination host MAC addresses and IP addresses according to the GRE Key, b) If it is a data packet of the data transmission interface A10, then obtain the corresponding transmission identification GRE Key, and then also fill in different destination host MAC addresses and IP addresses according to the difference of the transmission identification GRE Key, thus ensuring that the information belonging to the same user Make interface A11 and data transmission interface A10 send data to the same PCF or PDSN, which is convenient for user confirmation; Step 3: The load distribution module sequentially transmits the processed data packets to the queue management module, and sends them to the switch through the data packet sending module.

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